From nobody Sat Sep 21 09:31:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E34AAC38A02 for ; Fri, 28 Oct 2022 09:43:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229777AbiJ1Jne (ORCPT ); Fri, 28 Oct 2022 05:43:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229670AbiJ1Jna (ORCPT ); Fri, 28 Oct 2022 05:43:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D621819046F; Fri, 28 Oct 2022 02:43:28 -0700 (PDT) X-UUID: 8d74354aaa0a4c4680368bb3202461b5-20221028 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=z8DFcu4Y0BNFTtsi7qLl27vlNLxGCpxNh+bimbHT58w=; b=XjYz+XXC20IYw5QbMMQkoBhceZFUtrrcx7Fc9xKVrBl4lr9M/S1QzyOaOtUx3ARHPdAPijJGUuWUr8094kfs4KBq4BMfUt+Cg5u9DHf5J/w7kMa82XRslVMKBJHFFhdpUTqFMaLbb7qLGEJgTFJlF0+ebOjAv+NdSQtcOBPcH20=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:4f40ab48-9e11-4a00-8eea-27b1c01592fe,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:90 X-CID-INFO: VERSION:1.1.12,REQID:4f40ab48-9e11-4a00-8eea-27b1c01592fe,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:90 X-CID-META: VersionHash:62cd327,CLOUDID:57efe68f-1a78-4832-bd08-74b1519dcfbf,B ulkID:2210281728415RYLX1WJ,BulkQuantity:9,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:41,QS:nil,BEC:nil,COL:0 X-UUID: 8d74354aaa0a4c4680368bb3202461b5-20221028 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1454139993; Fri, 28 Oct 2022 17:43:23 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 28 Oct 2022 17:43:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 28 Oct 2022 17:43:22 +0800 From: Tinghan Shen To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , TingHan Shen Subject: [PATCH v4 1/3] dt-bindings: PCI: mediatek-gen3: Support mt8195 Date: Fri, 28 Oct 2022 17:43:15 +0800 Message-ID: <20221028094317.29270-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221028094317.29270-1-tinghan.shen@mediatek.com> References: <20221028094317.29270-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jianjun Wang In order to support mt8195 pcie node, update the yaml to support new properties of iommu and power-domain, and update the reset-names property to allow only one 'mac' name. Signed-off-by: Jianjun Wang Signed-off-by: TingHan Shen --- .../bindings/pci/mediatek-pcie-gen3.yaml | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml = b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index c00be39af64e..a9013c10131a 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -70,14 +70,21 @@ properties: minItems: 1 maxItems: 8 =20 + iommu-map: + maxItems: 1 + + iommu-map-mask: + const: 0 + resets: minItems: 1 maxItems: 2 =20 reset-names: - minItems: 1 - items: - - const: phy + oneOf: + - items: + - const: phy + - const: mac - const: mac =20 clocks: @@ -107,6 +114,9 @@ properties: items: - const: pcie-phy =20 + power-domains: + maxItems: 1 + '#interrupt-cells': const: 1 =20 --=20 2.18.0 From nobody Sat Sep 21 09:31:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5793BECAAA1 for ; Fri, 28 Oct 2022 09:43:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230005AbiJ1Jno (ORCPT ); Fri, 28 Oct 2022 05:43:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229706AbiJ1Jnc (ORCPT ); Fri, 28 Oct 2022 05:43:32 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD97719344A; Fri, 28 Oct 2022 02:43:30 -0700 (PDT) X-UUID: 70fd3edb1be7420c82e001d6f4e3d548-20221028 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=At7R1JsoYiOiVNo/az+uaSVEIeLq0G380u2fFPIm9bM=; b=aYs9NDzHnDuvOmufim6iczd5qqOhkoEWk7OxIIcX5o1YRpY/BlqHQEp0497dpSl4mmlNLNapLEN9R0HS+DbS34vpUWTMkK9EpkCJNV35R9hHbZ1sxjarCic2NKbw20gDwu3dnpgQVPhGOwBMQMkGPAgxdVb3HZ7h1LYYxVxT90I=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:f205a732-9e9b-46fb-bed2-a9fe09c6edbc,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.12,REQID:f205a732-9e9b-46fb-bed2-a9fe09c6edbc,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:62cd327,CLOUDID:59efe68f-1a78-4832-bd08-74b1519dcfbf,B ulkID:221028174327F2KFD9HJ,BulkQuantity:1,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:11|1,File:nil,Bulk:43,QS:nil,BEC:nil,COL:0 X-UUID: 70fd3edb1be7420c82e001d6f4e3d548-20221028 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1461732064; Fri, 28 Oct 2022 17:43:23 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 28 Oct 2022 17:43:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 28 Oct 2022 17:43:22 +0800 From: Tinghan Shen To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Tinghan Shen Subject: [PATCH v4 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes Date: Fri, 28 Oct 2022 17:43:16 +0800 Message-ID: <20221028094317.29270-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221028094317.29270-1-tinghan.shen@mediatek.com> References: <20221028094317.29270-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pcie and pcie phy nodes for mt8195. Signed-off-by: Jianjun Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 150 +++++++++++++++++++++++ 1 file changed, 150 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 905d1a90b406..97de03267884 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include =20 / { compatible =3D "mediatek,mt8195"; @@ -1182,6 +1183,110 @@ status =3D "disabled"; }; =20 + pcie0: pcie@112f0000 { + compatible =3D "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0 0x112f0000 0 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x20000000 + 0x0 0x20000000 0 0x200000>, + <0x82000000 0 0x20200000 + 0x0 0x20200000 0 0x3e00000>; + + iommu-map =3D <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; + iommu-map-mask =3D <0x0>; + + clocks =3D <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks =3D <&topckgen CLK_TOP_TL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy"; + + power-domains =3D <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + resets =3D <&infracfg_ao MT8195_INFRA_RST2_PCIE_P0_SWRST>; + reset-names =3D "mac"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + status =3D "disabled"; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + pcie1: pcie@112f8000 { + compatible =3D "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0 0x112f8000 0 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x24000000 + 0x0 0x24000000 0 0x200000>, + <0x82000000 0 0x24200000 + 0x0 0x24200000 0 0x3e00000>; + + iommu-map =3D <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; + iommu-map-mask =3D <0x0>; + + clocks =3D <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + /* Designer has connect pcie1 with peri_mem_p0 clock */ + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks =3D <&topckgen CLK_TOP_TL_P1>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys =3D <&u3port1 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + resets =3D <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; + reset-names =3D "mac"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + status =3D "disabled"; + + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + nor_flash: spi@1132c000 { compatible =3D "mediatek,mt8195-nor", "mediatek,mt8173-nor"; @@ -1241,6 +1346,34 @@ reg =3D <0x189 0x2>; bits =3D <7 5>; }; + pciephy_rx_ln1: pciephy-rx-ln1@190,1 { + reg =3D <0x190 0x1>; + bits =3D <0 4>; + }; + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { + reg =3D <0x190 0x1>; + bits =3D <4 4>; + }; + pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { + reg =3D <0x191 0x1>; + bits =3D <0 4>; + }; + pciephy_rx_ln0: pciephy-rx-ln0@191,2 { + reg =3D <0x191 0x1>; + bits =3D <4 4>; + }; + pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { + reg =3D <0x192 0x1>; + bits =3D <0 4>; + }; + pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { + reg =3D <0x192 0x1>; + bits =3D <4 4>; + }; + pciephy_glb_intr: pciephy-glb-intr@193 { + reg =3D <0x193 0x1>; + bits =3D <0 4>; + }; }; =20 u3phy2: t-phy@11c40000 { @@ -1461,6 +1594,23 @@ }; }; =20 + pciephy: phy@11e80000 { + compatible =3D "mediatek,mt8195-pcie-phy"; + reg =3D <0 0x11e80000 0 0x10000>; + reg-names =3D "sif"; + nvmem-cells =3D <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names =3D "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + ufsphy: ufs-phy@11fa0000 { compatible =3D "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; reg =3D <0 0x11fa0000 0 0xc000>; --=20 2.18.0 From nobody Sat Sep 21 09:31:35 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 986E0FA3741 for ; Fri, 28 Oct 2022 09:43:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229670AbiJ1Jnk (ORCPT ); Fri, 28 Oct 2022 05:43:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229691AbiJ1Jna (ORCPT ); Fri, 28 Oct 2022 05:43:30 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B219D1911FA; Fri, 28 Oct 2022 02:43:29 -0700 (PDT) X-UUID: c74a935848be4576b982fcd3366d7d0d-20221028 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; 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Fri, 28 Oct 2022 17:43:26 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 28 Oct 2022 17:43:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 28 Oct 2022 17:43:22 +0800 From: Tinghan Shen To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Tinghan Shen , Irui Wang Subject: [PATCH v4 3/3] arm64: dts: mt8195: Add venc node Date: Fri, 28 Oct 2022 17:43:17 +0800 Message-ID: <20221028094317.29270-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221028094317.29270-1-tinghan.shen@mediatek.com> References: <20221028094317.29270-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add venc node for mt8195 SoC. Signed-off-by: Irui Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 97de03267884..2a29ec3bfdd7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2109,6 +2109,30 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC>; }; =20 + venc: video-codec@1a020000 { + compatible =3D "mediatek,mt8195-vcodec-enc"; + reg =3D <0 0x1a020000 0 0x10000>; + iommus =3D <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts =3D ; + mediatek,scp =3D <&scp>; + clocks =3D <&vencsys CLK_VENC_VENC>; + clock-names =3D "venc_sel"; + assigned-clocks =3D <&topckgen CLK_TOP_VENC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible =3D "mediatek,mt8195-vencsys_core1"; reg =3D <0 0x1b000000 0 0x1000>; --=20 2.18.0