From nobody Sat Apr 11 12:08:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 067DAC67871 for ; Thu, 27 Oct 2022 09:59:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234971AbiJ0J7E (ORCPT ); Thu, 27 Oct 2022 05:59:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233800AbiJ0J6P (ORCPT ); Thu, 27 Oct 2022 05:58:15 -0400 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A62C6CBFF6; Thu, 27 Oct 2022 02:57:57 -0700 (PDT) Received: from anrayabh-desk.corp.microsoft.com (unknown [167.220.238.193]) by linux.microsoft.com (Postfix) with ESMTPSA id 922C3210DC49; Thu, 27 Oct 2022 02:57:52 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com 922C3210DC49 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1666864677; bh=Jv8NcD1chwUmTNicZiXn9+nD54mc1QBuHCDjeK1fu1g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U/EgMw2zZOefvoFHn/RekYsccgXiLi7igBivU1EeT43/i10zRG9Sp43FvZo5Qs99q zHriW17mmsEI/6STWPT+G4FM90PgdPnQszp2RTsSaFtF7QNBC03wN5rjFmFLOujX3E JtlwbfAkTM1ixlbOYTJw9rVIchpMAglivh9Q8c8c= From: Anirudh Rayabharam To: kys@microsoft.com, haiyangz@microsoft.com, sthemmin@microsoft.com, wei.liu@kernel.org, decui@microsoft.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, daniel.lezcano@linaro.org, Arnd Bergmann , linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org Cc: stanislav.kinsburskiy@gmail.com, Anirudh Rayabharam , kumarpraveen@linux.microsoft.com, mail@anirudhrb.com Subject: [PATCH v2 1/2] clocksource/drivers/hyperv: add data structure for reference TSC MSR Date: Thu, 27 Oct 2022 15:27:28 +0530 Message-Id: <20221027095729.1676394-2-anrayabh@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027095729.1676394-1-anrayabh@linux.microsoft.com> References: <20221027095729.1676394-1-anrayabh@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a data structure to represent the reference TSC MSR similar to other MSRs. This simplifies the code for updating the MSR. Signed-off-by: Anirudh Rayabharam Reviewed-by: Michael Kelley --- drivers/clocksource/hyperv_timer.c | 28 ++++++++++++++-------------- include/asm-generic/hyperv-tlfs.h | 9 +++++++++ 2 files changed, 23 insertions(+), 14 deletions(-) diff --git a/drivers/clocksource/hyperv_timer.c b/drivers/clocksource/hyper= v_timer.c index bb47610bbd1c..11332c82d1af 100644 --- a/drivers/clocksource/hyperv_timer.c +++ b/drivers/clocksource/hyperv_timer.c @@ -395,25 +395,25 @@ static u64 notrace read_hv_sched_clock_tsc(void) =20 static void suspend_hv_clock_tsc(struct clocksource *arg) { - u64 tsc_msr; + union hv_reference_tsc_msr tsc_msr; =20 /* Disable the TSC page */ - tsc_msr =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); - tsc_msr &=3D ~BIT_ULL(0); - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr); + tsc_msr.as_uint64 =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); + tsc_msr.enable =3D 0; + hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); } =20 =20 static void resume_hv_clock_tsc(struct clocksource *arg) { phys_addr_t phys_addr =3D virt_to_phys(&tsc_pg); - u64 tsc_msr; + union hv_reference_tsc_msr tsc_msr; =20 /* Re-enable the TSC page */ - tsc_msr =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); - tsc_msr &=3D GENMASK_ULL(11, 0); - tsc_msr |=3D BIT_ULL(0) | (u64)phys_addr; - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr); + tsc_msr.as_uint64 =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); + tsc_msr.enable =3D 1; + tsc_msr.pfn =3D __phys_to_pfn(phys_addr); + hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); } =20 #ifdef HAVE_VDSO_CLOCKMODE_HVCLOCK @@ -495,7 +495,7 @@ static __always_inline void hv_setup_sched_clock(void *= sched_clock) {} =20 static bool __init hv_init_tsc_clocksource(void) { - u64 tsc_msr; + union hv_reference_tsc_msr tsc_msr; phys_addr_t phys_addr; =20 if (!(ms_hyperv.features & HV_MSR_REFERENCE_TSC_AVAILABLE)) @@ -530,10 +530,10 @@ static bool __init hv_init_tsc_clocksource(void) * (which already has at least the low 12 bits set to zero since * it is page aligned). Also set the "enable" bit, which is bit 0. */ - tsc_msr =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); - tsc_msr &=3D GENMASK_ULL(11, 0); - tsc_msr =3D tsc_msr | 0x1 | (u64)phys_addr; - hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr); + tsc_msr.as_uint64 =3D hv_get_register(HV_REGISTER_REFERENCE_TSC); + tsc_msr.enable =3D 1; + tsc_msr.pfn =3D __phys_to_pfn(phys_addr); + hv_set_register(HV_REGISTER_REFERENCE_TSC, tsc_msr.as_uint64); =20 clocksource_register_hz(&hyperv_cs_tsc, NSEC_PER_SEC/100); =20 diff --git a/include/asm-generic/hyperv-tlfs.h b/include/asm-generic/hyperv= -tlfs.h index fdce7a4cfc6f..b17c6eeb9afa 100644 --- a/include/asm-generic/hyperv-tlfs.h +++ b/include/asm-generic/hyperv-tlfs.h @@ -102,6 +102,15 @@ struct ms_hyperv_tsc_page { volatile s64 tsc_offset; } __packed; =20 +union hv_reference_tsc_msr { + u64 as_uint64; + struct { + u64 enable:1; + u64 reserved:11; + u64 pfn:52; + } __packed; +}; + /* * The guest OS needs to register the guest ID with the hypervisor. * The guest ID is a 64 bit entity and the structure of this ID is --=20 2.34.1 From nobody Sat Apr 11 12:08:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1F5EC67871 for ; Thu, 27 Oct 2022 09:59:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234975AbiJ0J7N (ORCPT ); Thu, 27 Oct 2022 05:59:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234610AbiJ0J6U (ORCPT ); Thu, 27 Oct 2022 05:58:20 -0400 Received: from linux.microsoft.com (linux.microsoft.com [13.77.154.182]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B6426186DE; Thu, 27 Oct 2022 02:58:08 -0700 (PDT) Received: from anrayabh-desk.corp.microsoft.com (unknown [167.220.238.193]) by linux.microsoft.com (Postfix) with ESMTPSA id A92F3210DC4A; Thu, 27 Oct 2022 02:58:03 -0700 (PDT) DKIM-Filter: OpenDKIM Filter v2.11.0 linux.microsoft.com A92F3210DC4A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.microsoft.com; s=default; t=1666864688; bh=jZZ6qM4jUHM2tL93sOCGMRdtlaB9Zvma95PgYX3k+/8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Or5dRUFbmQppKY2ubGZ3DaOOE7D2DWgjIkzD9tFR4HwPXfrK/ZNOV8XfCzbPksEzj WhHFyxyqHJbnrhPRze4TbVrIgwbosQbfJ7iVnN1tpQjGz3XO1xEBG9zkOgfzVZQOPl qUgjCvi+xZ6UfCrxrAc+vDgUI3KNcH630oQFXYqU= From: Anirudh Rayabharam To: kys@microsoft.com, haiyangz@microsoft.com, sthemmin@microsoft.com, wei.liu@kernel.org, decui@microsoft.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, daniel.lezcano@linaro.org, Arnd Bergmann , linux-hyperv@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org Cc: stanislav.kinsburskiy@gmail.com, Anirudh Rayabharam , kumarpraveen@linux.microsoft.com, mail@anirudhrb.com Subject: [PATCH v2 2/2] x86/hyperv: fix invalid writes to MSRs during root partition kexec Date: Thu, 27 Oct 2022 15:27:29 +0530 Message-Id: <20221027095729.1676394-3-anrayabh@linux.microsoft.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221027095729.1676394-1-anrayabh@linux.microsoft.com> References: <20221027095729.1676394-1-anrayabh@linux.microsoft.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" hv_cleanup resets the hypercall page by setting the MSR to 0. However, the root partition is not allowed to write to the GPA bits of the MSR. Instead, it uses the hypercall page provided by the MSR. Similar is the case with the reference TSC MSR. Clear only the enable bit instead of zeroing the entire MSR to make the code valid for root partition too. Signed-off-by: Anirudh Rayabharam Reviewed-by: Michael Kelley --- arch/x86/hyperv/hv_init.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c index 29774126e931..80fdfff9266c 100644 --- a/arch/x86/hyperv/hv_init.c +++ b/arch/x86/hyperv/hv_init.c @@ -537,6 +537,7 @@ void __init hyperv_init(void) void hyperv_cleanup(void) { union hv_x64_msr_hypercall_contents hypercall_msr; + union hv_reference_tsc_msr tsc_msr; =20 unregister_syscore_ops(&hv_syscore_ops); =20 @@ -552,12 +553,14 @@ void hyperv_cleanup(void) hv_hypercall_pg =3D NULL; =20 /* Reset the hypercall page */ - hypercall_msr.as_uint64 =3D 0; - wrmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); + hypercall_msr.as_uint64 =3D hv_get_register(HV_X64_MSR_HYPERCALL); + hypercall_msr.enable =3D 0; + hv_set_register(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64); =20 /* Reset the TSC page */ - hypercall_msr.as_uint64 =3D 0; - wrmsrl(HV_X64_MSR_REFERENCE_TSC, hypercall_msr.as_uint64); + tsc_msr.as_uint64 =3D hv_get_register(HV_X64_MSR_REFERENCE_TSC); + tsc_msr.enable =3D 0; + hv_set_register(HV_X64_MSR_REFERENCE_TSC, tsc_msr.as_uint64); } =20 void hyperv_report_panic(struct pt_regs *regs, long err, bool in_die) --=20 2.34.1