From nobody Sat Sep 21 13:58:22 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12787FA373D for ; Thu, 27 Oct 2022 09:55:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235033AbiJ0JzX (ORCPT ); Thu, 27 Oct 2022 05:55:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234886AbiJ0JzR (ORCPT ); Thu, 27 Oct 2022 05:55:17 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB3D34E877; Thu, 27 Oct 2022 02:55:16 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C776166028CF; Thu, 27 Oct 2022 10:55:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1666864515; bh=XOuhqy5hOPdqpQ8sIzWrIZYqHoZW6wPK8VwlJ/w9e6I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UnwvIyUa4IWPVyjXR2fNMiz5qjQnnEkogRbBxsht2kmsemjK7xKOR5FEVXYwQhd1m q3i0iQb7IdfQ7FG4cCSv4IVm8mkyKZPzyyX+g5zxMXa9nOcge6UGnm+f6IVeMCDQoQ 8UTG+p4fGQhBkH6DJpnG54buzqNtEbS3xJRULPDF5eJvP9ZBJW39DkbCMtypU8+Pok 1LcyLAY4DzjxiEWKF2leT5/LsJgtZhBEShdLwPHnYcPSrayWGcaL32xyd0jmSOFWg4 4c5GCCPSTd1tR0FAOBuEpQ1zoqdO1BJJyIpLBKGVnrYyWZmetKCDZIAtkRiQFLH7EX 15LqX6tlkEWsQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, hsinyi@chromium.org, nfraprado@collabora.com, allen-kh.cheng@mediatek.com, sam.shih@mediatek.com, andrew@lunn.ch, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 2/6] arm64: dts: mediatek: mt6795: Replace UART dummy clocks with pericfg Date: Thu, 27 Oct 2022 11:55:00 +0200 Message-Id: <20221027095504.37432-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221027095504.37432-1-angelogioacchino.delregno@collabora.com> References: <20221027095504.37432-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The UART nodes had a dummy clock for early bringup, as it is expected that these are left on by the bootloader: now that the pericfg clock controller is supported, we can replace them with the real clocks. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt6795.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6795.dtsi b/arch/arm64/boot/dts= /mediatek/mt6795.dtsi index 1801cafd9c13..60a07410ff63 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6795.dtsi @@ -314,7 +314,8 @@ uart0: serial@11002000 { "mediatek,mt6577-uart"; reg =3D <0 0x11002000 0 0x400>; interrupts =3D ; - clocks =3D <&clk26m>; + clocks =3D <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; + clock-names =3D "baud", "bus"; status =3D "disabled"; }; =20 @@ -323,7 +324,8 @@ uart1: serial@11003000 { "mediatek,mt6577-uart"; reg =3D <0 0x11003000 0 0x400>; interrupts =3D ; - clocks =3D <&clk26m>; + clocks =3D <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; + clock-names =3D "baud", "bus"; status =3D "disabled"; }; =20 @@ -332,7 +334,8 @@ uart2: serial@11004000 { "mediatek,mt6577-uart"; reg =3D <0 0x11004000 0 0x400>; interrupts =3D ; - clocks =3D <&clk26m>; + clocks =3D <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; + clock-names =3D "baud", "bus"; status =3D "disabled"; }; =20 @@ -341,7 +344,8 @@ uart3: serial@11005000 { "mediatek,mt6577-uart"; reg =3D <0 0x11005000 0 0x400>; interrupts =3D ; - clocks =3D <&clk26m>; + clocks =3D <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; + clock-names =3D "baud", "bus"; status =3D "disabled"; }; }; --=20 2.37.2