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([64.57.193.93]) by smtp.gmail.com with ESMTPSA id de30-20020a05620a371e00b006e99290e83fsm2942089qkb.107.2022.10.26.13.04.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 13:04:02 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Dmitry Baryshkov Subject: [PATCH 1/4] arm64: dts: qcom: sm8450: move SDHCI pin configuration to DTSI Date: Wed, 26 Oct 2022 16:03:54 -0400 Message-Id: <20221026200357.391635-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221026200357.391635-1-krzysztof.kozlowski@linaro.org> References: <20221026200357.391635-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The SDHCI pin configuration/mux nodes are actually common to all upstreamed boards, so define them in SoC DTSI to reduce code duplication. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- In theory drive strength belongs to the board DTS, not SoC DTSI, but I am following the advice here: https://lore.kernel.org/lkml/CAD=3DFV=3DVUL4GmjaibAMhKNdpEso_Hg_R=3DXeMaqah= 1LSj_9-Ce4Q@mail.gmail.com/ --- .../qcom/sm8450-sony-xperia-nagara-pdx223.dts | 20 ------------------- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 +++++++++++++++++++ 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts = b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts index 82918c2d956f..718c690af8ad 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-sony-xperia-nagara-pdx223.dts @@ -572,26 +572,6 @@ &spi10 { &tlmm { gpio-reserved-ranges =3D <28 4>; =20 - sdc2_default_state: sdc2-default-state { - clk-pins { - pins =3D "sdc2_clk"; - drive-strength =3D <16>; - bias-disable; - }; - - cmd-pins { - pins =3D "sdc2_cmd"; - drive-strength =3D <16>; - bias-pull-up; - }; - - data-pins { - pins =3D "sdc2_data"; - drive-strength =3D <16>; - bias-pull-up; - }; - }; - ts_int_default: ts-int-default-state { pins =3D "gpio23"; function =3D "gpio"; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 1d1775334575..1df5c964c6f7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2515,6 +2515,26 @@ tlmm: pinctrl@f100000 { gpio-ranges =3D <&tlmm 0 0 211>; wakeup-parent =3D <&pdc>; =20 + sdc2_default_state: sdc2-default-state { + clk-pins { + pins =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "sdc2_cmd"; + drive-strength =3D <16>; + bias-pull-up; + }; + + data-pins { + pins =3D "sdc2_data"; + drive-strength =3D <16>; + bias-pull-up; + }; + }; + sdc2_sleep_state: sdc2-sleep-state { clk-pins { pins =3D "sdc2_clk"; --=20 2.34.1