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(fttx-pool-80.245.72.174.bambit.de [80.245.72.174]) by mxbox4.masterlogin.de (Postfix) with ESMTPSA id 83CB180ADC; Wed, 26 Oct 2022 09:37:00 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Matthias Brugger , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sam Shih Subject: [RFC v2 2/7] arm64: dts: mt7986: add spi related device nodes Date: Wed, 26 Oct 2022 11:36:45 +0200 Message-Id: <20221026093650.110290-3-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221026093650.110290-1-linux@fw-web.de> References: <20221026093650.110290-1-linux@fw-web.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: f63a6cba-36ee-498e-95fd-b815b87a5642 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sam Shih This patch adds spi support for MT7986. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 35 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 28 ++++++++++++++++ arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 35 ++++++++++++++++++++ 3 files changed, 98 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot= /dts/mediatek/mt7986a-rfb.dts index 6189436fe31d..58f7e6b169bf 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -55,6 +55,20 @@ switch: switch@0 { }; =20 &pio { + spi_flash_pins: spi-flash-pins { + mux { + function =3D "spi"; + groups =3D "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function =3D "spi"; + groups =3D "spi1_2"; + }; + }; + uart1_pins: uart1-pins { mux { function =3D "uart"; @@ -101,6 +115,27 @@ conf { }; }; =20 +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi_flash_pins>; + cs-gpios =3D <0>, <0>; + status =3D "okay"; + spi_nand: spi_nand@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + spi-tx-buswidth =3D <4>; + spi-rx-buswidth =3D <4>; + }; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spic_pins>; + cs-gpios =3D <0>, <0>; + status =3D "okay"; +}; + &switch { ports { #address-cells =3D <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7986a.dtsi index 226648f48df2..6d881095d933 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -112,6 +112,34 @@ infracfg: infracfg@10001000 { #clock-cells =3D <1>; }; =20 + spi0: spi@1100a000 { + compatible =3D "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x1100a000 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk", "hclk"; + status =3D "disabled"; + }; + + spi1: spi@1100b000 { + compatible =3D "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0 0x1100b000 0 0x100>; + interrupts =3D ; + clocks =3D <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names =3D "parent-clk", "sel-clk", "spi-clk", "hclk"; + status =3D "disabled"; + }; + topckgen: topckgen@1001b000 { compatible =3D "mediatek,mt7986-topckgen", "syscon"; reg =3D <0 0x1001B000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot= /dts/mediatek/mt7986b-rfb.dts index 7459ddb6b6f0..7673aa3fa6ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -96,6 +96,20 @@ fixed-link { }; =20 &pio { + spi_flash_pins: spi-flash-pins { + mux { + function =3D "spi"; + groups =3D "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function =3D "spi"; + groups =3D "spi1_2"; + }; + }; + wf_2g_5g_pins: wf-2g-5g-pins { mux { function =3D "wifi"; @@ -128,6 +142,27 @@ conf { }; }; =20 +&spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi_flash_pins>; + cs-gpios =3D <0>, <0>; + status =3D "okay"; + spi_nand: spi_nand@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + spi-max-frequency =3D <10000000>; + spi-tx-buswidth =3D <4>; + spi-rx-buswidth =3D <4>; + }; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spic_pins>; + cs-gpios =3D <0>, <0>; + status =3D "okay"; +}; + &uart0 { status =3D "okay"; }; --=20 2.34.1