From nobody Wed Apr 8 10:04:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9ED05ECDFA1 for ; Tue, 25 Oct 2022 11:33:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230005AbiJYLda (ORCPT ); Tue, 25 Oct 2022 07:33:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231605AbiJYLdV (ORCPT ); Tue, 25 Oct 2022 07:33:21 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6779122772; Tue, 25 Oct 2022 04:33:20 -0700 (PDT) Received: from canpemm500009.china.huawei.com (unknown [172.30.72.57]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4MxVDf69LGzHtpH; Tue, 25 Oct 2022 19:33:06 +0800 (CST) Received: from localhost.localdomain (10.67.164.66) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 19:33:18 +0800 From: Yicong Yang To: Shaokun Zhang , , Jonathan Corbet , Will Deacon , Mark Rutland , John Garry , CC: , , , , , Subject: [PATCH 1/3] drivers/perf: hisi: Fix some event id for hisi-pcie-pmu Date: Tue, 25 Oct 2022 19:32:40 +0800 Message-ID: <20221025113242.58271-2-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20221025113242.58271-1-yangyicong@huawei.com> References: <20221025113242.58271-1-yangyicong@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.164.66] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yicong Yang Some event id of hisi-pcie-pmu is incorrect, fix them. Fixes: 8404b0fbc7fb ("drivers/perf: hisi: Add driver for HiSilicon PCIe PMU= ") Signed-off-by: Yicong Yang Reviewed-by: Jonathan Cameron --- drivers/perf/hisilicon/hisi_pcie_pmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilico= n/hisi_pcie_pmu.c index 21771708597d..071e63d9a9ac 100644 --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c @@ -693,10 +693,10 @@ static struct attribute *hisi_pcie_pmu_events_attr[] = =3D { HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_cnt, 0x10210), HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_latency, 0x0011), HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_cnt, 0x10011), - HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x1005), - HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x11005), - HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x2004), - HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x12004), + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_flux, 0x0804), + HISI_PCIE_PMU_EVENT_ATTR(rx_mrd_time, 0x10804), + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_flux, 0x0405), + HISI_PCIE_PMU_EVENT_ATTR(tx_mrd_time, 0x10405), NULL }; =20 --=20 2.24.0 From nobody Wed Apr 8 10:04:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD5F4FA3740 for ; Tue, 25 Oct 2022 11:33:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231720AbiJYLd1 (ORCPT ); Tue, 25 Oct 2022 07:33:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231921AbiJYLdV (ORCPT ); Tue, 25 Oct 2022 07:33:21 -0400 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD3A6123454; Tue, 25 Oct 2022 04:33:20 -0700 (PDT) Received: from canpemm500009.china.huawei.com (unknown [172.30.72.57]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4MxV7H1q3QzmVJ8; Tue, 25 Oct 2022 19:28:27 +0800 (CST) Received: from localhost.localdomain (10.67.164.66) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 19:33:19 +0800 From: Yicong Yang To: Shaokun Zhang , , Jonathan Corbet , Will Deacon , Mark Rutland , John Garry , CC: , , , , , Subject: [PATCH 2/3] docs: perf: Fix PMU instance name of hisi-pcie-pmu Date: Tue, 25 Oct 2022 19:32:41 +0800 Message-ID: <20221025113242.58271-3-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20221025113242.58271-1-yangyicong@huawei.com> References: <20221025113242.58271-1-yangyicong@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.164.66] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yicong Yang The PMU instance will be called hisi_pcie_core rather than hisi_pcie_. Fix this in the documentation. Fixes: c8602008e247 ("docs: perf: Add description for HiSilicon PCIe PMU dr= iver") Signed-off-by: Yicong Yang Reviewed-by: Jonathan Cameron --- .../admin-guide/perf/hisi-pcie-pmu.rst | 22 +++++++++---------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/Documentation/admin-guide/perf/hisi-pcie-pmu.rst b/Documentati= on/admin-guide/perf/hisi-pcie-pmu.rst index 294ebbdb22af..bbe66480ff85 100644 --- a/Documentation/admin-guide/perf/hisi-pcie-pmu.rst +++ b/Documentation/admin-guide/perf/hisi-pcie-pmu.rst @@ -15,10 +15,10 @@ HiSilicon PCIe PMU driver The PCIe PMU driver registers a perf PMU with the name of its sicl-id and = PCIe Core id.:: =20 - /sys/bus/event_source/hisi_pcie_ + /sys/bus/event_source/hisi_pcie_core =20 PMU driver provides description of available events and filter options in = sysfs, -see /sys/bus/event_source/devices/hisi_pcie_. +see /sys/bus/event_source/devices/hisi_pcie_core. =20 The "format" directory describes all formats of the config (events) and co= nfig1 (filter options) fields of the perf_event_attr structure. The "events" dir= ectory @@ -33,13 +33,13 @@ monitored by PMU. Example usage of perf:: =20 $# perf list - hisi_pcie0_0/rx_mwr_latency/ [kernel PMU event] - hisi_pcie0_0/rx_mwr_cnt/ [kernel PMU event] + hisi_pcie0_core0/rx_mwr_latency/ [kernel PMU event] + hisi_pcie0_core0/rx_mwr_cnt/ [kernel PMU event] ------------------------------------------ =20 - $# perf stat -e hisi_pcie0_0/rx_mwr_latency/ - $# perf stat -e hisi_pcie0_0/rx_mwr_cnt/ - $# perf stat -g -e hisi_pcie0_0/rx_mwr_latency/ -e hisi_pcie0_0/rx_mwr_c= nt/ + $# perf stat -e hisi_pcie0_core0/rx_mwr_latency/ + $# perf stat -e hisi_pcie0_core0/rx_mwr_cnt/ + $# perf stat -g -e hisi_pcie0_core0/rx_mwr_latency/ -e hisi_pcie0_core0/= rx_mwr_cnt/ =20 The current driver does not support sampling. So "perf record" is unsuppor= ted. Also attach to a task is unsupported for PCIe PMU. @@ -64,7 +64,7 @@ bit8 is set, port=3D0x100; if these two Root Ports are bo= th monitored, port=3D0x101. =20 Example usage of perf:: =20 - $# perf stat -e hisi_pcie0_0/rx_mwr_latency,port=3D0x1/ sleep 5 + $# perf stat -e hisi_pcie0_core0/rx_mwr_latency,port=3D0x1/ sleep 5 =20 -bdf =20 @@ -76,7 +76,7 @@ For example, "bdf=3D0x3900" means BDF of target Endpoint = is 0000:39:00.0. =20 Example usage of perf:: =20 - $# perf stat -e hisi_pcie0_0/rx_mrd_flux,bdf=3D0x3900/ sleep 5 + $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,bdf=3D0x3900/ sleep 5 =20 2. Trigger filter Event statistics start when the first time TLP length is greater/smaller @@ -90,7 +90,7 @@ means start when TLP length < condition. =20 Example usage of perf:: =20 - $# perf stat -e hisi_pcie0_0/rx_mrd_flux,trig_len=3D0x4,trig_mode=3D1/ s= leep 5 + $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,trig_len=3D0x4,trig_mode=3D= 1/ sleep 5 =20 3. Threshold filter Counter counts when TLP length within the specified range. You can set the @@ -103,4 +103,4 @@ when TLP length < threshold. =20 Example usage of perf:: =20 - $# perf stat -e hisi_pcie0_0/rx_mrd_flux,thr_len=3D0x4,thr_mode=3D1/ sle= ep 5 + $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,thr_len=3D0x4,thr_mode=3D1/= sleep 5 --=20 2.24.0 From nobody Wed Apr 8 10:04:15 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB7C2C04A95 for ; Tue, 25 Oct 2022 11:33:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231947AbiJYLde (ORCPT ); Tue, 25 Oct 2022 07:33:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230305AbiJYLdW (ORCPT ); Tue, 25 Oct 2022 07:33:22 -0400 Received: from szxga03-in.huawei.com (szxga03-in.huawei.com [45.249.212.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26E57125006; Tue, 25 Oct 2022 04:33:21 -0700 (PDT) Received: from canpemm500009.china.huawei.com (unknown [172.30.72.57]) by szxga03-in.huawei.com (SkyGuard) with ESMTP id 4MxV9j6XJ9zJn9V; Tue, 25 Oct 2022 19:30:33 +0800 (CST) Received: from localhost.localdomain (10.67.164.66) by canpemm500009.china.huawei.com (7.192.105.203) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 25 Oct 2022 19:33:19 +0800 From: Yicong Yang To: Shaokun Zhang , , Jonathan Corbet , Will Deacon , Mark Rutland , John Garry , CC: , , , , , Subject: [PATCH 3/3] drivers/perf: hisi: Add TLP filter support Date: Tue, 25 Oct 2022 19:32:42 +0800 Message-ID: <20221025113242.58271-4-yangyicong@huawei.com> X-Mailer: git-send-email 2.31.0 In-Reply-To: <20221025113242.58271-1-yangyicong@huawei.com> References: <20221025113242.58271-1-yangyicong@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.67.164.66] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To canpemm500009.china.huawei.com (7.192.105.203) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yicong Yang The PMU support to filter the TLP when counting the bandwidth with below options: - only count the TLP headers - only count the TLP payloads - count both TLP headers and payloads In the current driver it's default to count the TLP payloads only, which will have an implicity side effects that on the traffic only have header only TLPs, we'll get no data. Make this user configuration through "len_mode" parameter and make it default to count both TLP headers and payloads when user not specified. Also update the documentation for it. Signed-off-by: Yicong Yang --- .../admin-guide/perf/hisi-pcie-pmu.rst | 20 +++++++++++++++++++ drivers/perf/hisilicon/hisi_pcie_pmu.c | 14 ++++++++++++- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/perf/hisi-pcie-pmu.rst b/Documentati= on/admin-guide/perf/hisi-pcie-pmu.rst index bbe66480ff85..83a2ef11b1a0 100644 --- a/Documentation/admin-guide/perf/hisi-pcie-pmu.rst +++ b/Documentation/admin-guide/perf/hisi-pcie-pmu.rst @@ -104,3 +104,23 @@ when TLP length < threshold. Example usage of perf:: =20 $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,thr_len=3D0x4,thr_mode=3D1/= sleep 5 + +4. TLP Length filter +When counting bandwidth, the data can be composed of certain parts of TLP +packets. You can specify it through "len_mode": + +- 2'b00: Reserved (Do not use this since the behaviour is undefined) +- 2'b01: Bandwidth of TLP payloads +- 2'b10: Bandwidth of TLP headers +- 2'b11: Bandwidth of both TLP payloads and headers + +For example, "len_mode=3D2" means only counting the bandwidth of TLP heade= rs +and "len_mode=3D3" means the final bandwidth data is composed of both TLP +headers and payloads. You need to carefully using this to avoid losing +data. For example you're likely to get no counts by "len_mode=3D1" if the = TLPs +on the traffic has no payload. This config is optional, by default it'll +be 2'b11. + +Example usage of perf:: + + $# perf stat -e hisi_pcie0_core0/rx_mrd_flux,len_mode=3D0x1/ sleep 5 diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilico= n/hisi_pcie_pmu.c index 071e63d9a9ac..6fee0b6e163b 100644 --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c @@ -47,10 +47,14 @@ #define HISI_PCIE_EVENT_M GENMASK_ULL(15, 0) #define HISI_PCIE_THR_MODE_M GENMASK_ULL(27, 27) #define HISI_PCIE_THR_M GENMASK_ULL(31, 28) +#define HISI_PCIE_LEN_M GENMASK_ULL(35, 34) #define HISI_PCIE_TARGET_M GENMASK_ULL(52, 36) #define HISI_PCIE_TRIG_MODE_M GENMASK_ULL(53, 53) #define HISI_PCIE_TRIG_M GENMASK_ULL(59, 56) =20 +/* Default config of TLP length mode, will count both TLP headers and payl= oads */ +#define HISI_PCIE_LEN_M_DEFAULT 3ULL + #define HISI_PCIE_MAX_COUNTERS 8 #define HISI_PCIE_REG_STEP 8 #define HISI_PCIE_THR_MAX_VAL 10 @@ -91,6 +95,7 @@ HISI_PCIE_PMU_FILTER_ATTR(thr_len, config1, 3, 0); HISI_PCIE_PMU_FILTER_ATTR(thr_mode, config1, 4, 4); HISI_PCIE_PMU_FILTER_ATTR(trig_len, config1, 8, 5); HISI_PCIE_PMU_FILTER_ATTR(trig_mode, config1, 9, 9); +HISI_PCIE_PMU_FILTER_ATTR(len_mode, config1, 11, 10); HISI_PCIE_PMU_FILTER_ATTR(port, config2, 15, 0); HISI_PCIE_PMU_FILTER_ATTR(bdf, config2, 31, 16); =20 @@ -215,8 +220,8 @@ static void hisi_pcie_pmu_config_filter(struct perf_eve= nt *event) { struct hisi_pcie_pmu *pcie_pmu =3D to_pcie_pmu(event->pmu); struct hw_perf_event *hwc =3D &event->hw; + u64 port, trig_len, thr_len, len_mode; u64 reg =3D HISI_PCIE_INIT_SET; - u64 port, trig_len, thr_len; =20 /* Config HISI_PCIE_EVENT_CTRL according to event. */ reg |=3D FIELD_PREP(HISI_PCIE_EVENT_M, hisi_pcie_get_real_event(event)); @@ -245,6 +250,12 @@ static void hisi_pcie_pmu_config_filter(struct perf_ev= ent *event) reg |=3D HISI_PCIE_THR_EN; } =20 + len_mode =3D hisi_pcie_get_len_mode(event); + if (len_mode) + reg |=3D FIELD_PREP(HISI_PCIE_LEN_M, len_mode); + else + reg |=3D FIELD_PREP(HISI_PCIE_LEN_M, HISI_PCIE_LEN_M_DEFAULT); + hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg); } =20 @@ -711,6 +722,7 @@ static struct attribute *hisi_pcie_pmu_format_attr[] = =3D { HISI_PCIE_PMU_FORMAT_ATTR(thr_mode, "config1:4"), HISI_PCIE_PMU_FORMAT_ATTR(trig_len, "config1:5-8"), HISI_PCIE_PMU_FORMAT_ATTR(trig_mode, "config1:9"), + HISI_PCIE_PMU_FORMAT_ATTR(len_mode, "config1:10-11"), HISI_PCIE_PMU_FORMAT_ATTR(port, "config2:0-15"), HISI_PCIE_PMU_FORMAT_ATTR(bdf, "config2:16-31"), NULL --=20 2.24.0