From nobody Wed Apr 8 10:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF6CAC04A95 for ; Tue, 25 Oct 2022 07:33:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231819AbiJYHdc (ORCPT ); Tue, 25 Oct 2022 03:33:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231829AbiJYHdU (ORCPT ); Tue, 25 Oct 2022 03:33:20 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 729E61552D0 for ; Tue, 25 Oct 2022 00:33:15 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id n7so10500257plp.1 for ; Tue, 25 Oct 2022 00:33:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jQnAjVM8KfWMqcwU3yG9m91ABhfRemXy71C0Mul10HU=; b=e8JJy63K9LlYNjNRkaJF+MGYeZJonUWQVJAkpo8xchWw4xqq+Fz/VfKE0WeZOnJcax W/+u2b+ROsGpGNPd/DE4I8cnfzjyQcemBjwVd6BD/A9kAfUwVQn85iW/9L0l5Zrv4zCM ef8TJpZAURk1+ZfOPgLTRLdnjX779naxVajmLClgWpVrgJ9hs8obvZPZTLuDWiGfgZcG uw9rUYAGDdZkDH6bkSgeaTruKw9jQF+/ZVJedGY5bkhH802qBSBQWn/TP+85PbXG5Aa6 dDTEMcpkWdMwnSN8Wz8WR0PU1o8fRBMTkgnFrW40RVh3yrb4XT+sk61BwQyZxDx3fzFD +7DQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jQnAjVM8KfWMqcwU3yG9m91ABhfRemXy71C0Mul10HU=; b=uIOKr7lBfle/3Ht0a/LiI/sFS/ptRP6zIf+coJzo0JgXhyDVZ3d6OmKtxe/QiQhqzd Al89m0wy6XvvHB8YDDzVpcDsDy4XPLU0ySY68yy7arz18HfXa14TedPaJku4JsETf5dx 36DDYxIkEts0S0UgPSmYTZhWB3f/iUMl8dXyaTwLdgKmfJQ8bbw8naN3dqZUGbA8y10J E3CGChRd4O+YA68gRVnmTzDKI87XM0J8eHFgJvyPDOMUZ3gZ35MBOJyXfXe7CJIqzrRr zyhRqWzCEnk5wci4MXF4GCnBcgUZYl+ZxljChbqi/lVY3JjQoVNdsR1HrlWzwih6x6So +QQw== X-Gm-Message-State: ACrzQf3RVYko1bBukYaUVMt52bfEsrJbqQ3vMTde5roXgg3LRVIPsRjg olIkOhREdZDd5feKqGxKRHuy X-Google-Smtp-Source: AMsMyM5Q6hyH/r3aMTe/oOPuJy8fJM9avInLR8qN1a8pB8WvQDd7f46uyeOJuTz7+IsPb8Uv/YtK6Q== X-Received: by 2002:a17:90a:e606:b0:212:f100:22e3 with SMTP id j6-20020a17090ae60600b00212f10022e3mr15802518pjy.83.1666683194461; Tue, 25 Oct 2022 00:33:14 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:12 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v2 1/7] dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider Date: Tue, 25 Oct 2022 13:02:48 +0530 Message-Id: <20221025073254.1564622-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index cbba8979fe0e..2e0336163ffb 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -57,6 +57,9 @@ properties: '#freq-domain-cells': const: 1 =20 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -84,6 +87,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_0>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -100,6 +104,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_100>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -113,6 +118,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_200>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -126,6 +132,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_300>; qcom,freq-domain =3D <&cpufreq_hw 0>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -139,6 +146,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_400>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -152,6 +160,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_500>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -165,6 +174,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_600>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -178,6 +188,7 @@ examples: enable-method =3D "psci"; next-level-cache =3D <&L2_700>; qcom,freq-domain =3D <&cpufreq_hw 1>; + clocks =3D <&cpufreq_hw 1>; L2_700: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -198,6 +209,7 @@ examples: clock-names =3D "xo", "alternate"; =20 #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; }; }; ... --=20 2.25.1 From nobody Wed Apr 8 10:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28523C38A2D for ; Tue, 25 Oct 2022 07:33:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231777AbiJYHdt (ORCPT ); Tue, 25 Oct 2022 03:33:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231624AbiJYHdW (ORCPT ); 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Tue, 25 Oct 2022 00:33:17 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 2/7] arm64: dts: qcom: sm8450: Supply clock from cpufreq node to CPUs Date: Tue, 25 Oct 2022 13:02:49 +0530 Message-Id: <20221025073254.1564622-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qco= m/sm8450.dtsi index 6c18cfca9a34..8f26cf9aad01 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -52,6 +52,7 @@ CPU0: cpu@0 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_0: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -71,6 +72,7 @@ CPU1: cpu@100 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_100: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -87,6 +89,7 @@ CPU2: cpu@200 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_200: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -103,6 +106,7 @@ CPU3: cpu@300 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 0>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 0>; L2_300: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -119,6 +123,7 @@ CPU4: cpu@400 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_400: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -135,6 +140,7 @@ CPU5: cpu@500 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_500: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -152,6 +158,7 @@ CPU6: cpu@600 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 1>; #cooling-cells =3D <2>; + clocks =3D <&cpufreq_hw 1>; L2_600: l2-cache { compatible =3D "cache"; next-level-cache =3D <&L3_0>; @@ -168,6 +175,7 @@ CPU7: cpu@700 { power-domain-names =3D "psci"; qcom,freq-domain =3D <&cpufreq_hw 2>; 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charset="utf-8" CPUFreq core will always set the "policy->cpus" bitmask with the bitfield of the CPU that goes first per domain/policy. So there is no way the "policy->cpus" bitmask will be empty during qcom_cpufreq_hw_cpu_init(). Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index d5ef3c66c762..a5b3b8d0e164 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -552,11 +552,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_pol= icy *policy) data->per_core_dcvs =3D true; =20 qcom_get_related_cpus(index, policy->cpus); - if (cpumask_empty(policy->cpus)) { - dev_err(dev, "Domain-%d failed to get related CPUs\n", index); - ret =3D -ENOENT; - goto error; - } =20 policy->driver_data =3D data; policy->dvfs_possible_from_any_cpu =3D true; --=20 2.25.1 From nobody Wed Apr 8 10:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9790DFA373E for ; Tue, 25 Oct 2022 07:34:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231778AbiJYHeW (ORCPT ); Tue, 25 Oct 2022 03:34:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231810AbiJYHda (ORCPT ); Tue, 25 Oct 2022 03:33:30 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D6571158D66 for ; Tue, 25 Oct 2022 00:33:29 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id f23so10482859plr.6 for ; Tue, 25 Oct 2022 00:33:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=q2nlS3XahONFZFIAHmPH/AavNAlCb2gKg69yTobdo08=; b=QCY1FpXs5WO6Zoq7B22DvZ1pZWwGCMuIxC+78tY69RBgPRC5LFHcu6q4WjcR4WPFlK t7kpFICtt4+YWJQwpBeWdZyX8VO73OnZMcX8VrQkKPkQe2JBNZuaaynnW6uMZ6IEV8WV E6kTvCg8jJreqbNhu5EXq92YSS0A8RBVWMvG9L2Q/k/+VE6M60+xRcEE6qYGT12oI7Sl GAwi0ZobnHBmv1QbZacs9IEUCTJY+sH0W50YGlg8okH9nQX2LxFMh2mve91qUDqIWXgg LLoaJTA0usHfCwDgaabp+9U4kjGhNhT27EtF3liLMnuyCab9tlaSN7mmam3XDqmRv8EU ZV6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q2nlS3XahONFZFIAHmPH/AavNAlCb2gKg69yTobdo08=; b=FL1/nrX8mCWYLuudXf3hC20PhjQRGcLsMd5iRMgCeygDO7/42lzEqfqb0JHIM1GmTQ m48lO+fSoN6gzJ3XtccUM6W/g/cDoppXZB0lQlJMaNATUB9jmLApVtef7C1PMBF0gc/k VZ7kuTKrjkVTQ/nfjplaHbdsPqLFttly0aHjoGfJxC+BA5p8XJK/WuXYZYXNce1jC87X 9+N6o2JU3yhQ04D0S27JNAomJjCjoX7PRN6Sb8Yz5l0KuOt6u6mnlcFdW9iNDFP5wxGW ZBh094hCoVQ2eIrZoQEQyZd5IlrtVEkqYxw4klujnmW5jIYuG2BC0P8R0Ng4aLyeBzfK 0qMg== X-Gm-Message-State: ACrzQf0vTHrKB8vi57iN2lrCmnMjGXaaiq9uPEGW/EVV4MdQltpsgkv4 R6BIMOBHsGtsNQxDFsge3fMG X-Google-Smtp-Source: AMsMyM6Lyxu4C8r07ItG9E0ag22O+BWY2awNjYOtomIMytiks/zHPyHKsDZcism4d8QEdth6YnFgdg== X-Received: by 2002:a17:902:7c97:b0:17f:5abf:9450 with SMTP id y23-20020a1709027c9700b0017f5abf9450mr36016087pll.19.1666683209309; Tue, 25 Oct 2022 00:33:29 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:27 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 4/7] cpufreq: qcom-hw: Allocate qcom_cpufreq_data during probe Date: Tue, 25 Oct 2022 13:02:51 +0530 Message-Id: <20221025073254.1564622-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" qcom_cpufreq_data is allocated based on the number of frequency domains defined in DT which is static and won't change during runtime. There is no real reason to allocate it during the CPU init() callback and deallocate it during exit(). Hence, move the allocation to probe() and use the allocated memory during init(). This also allows us to use devm_platform_get_and_ioremap_resource() helper for acquiring the freq-domain resources from DT. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 86 +++++++++++++------------------ 1 file changed, 37 insertions(+), 49 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index a5b3b8d0e164..1842e9facaa1 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -58,6 +58,10 @@ struct qcom_cpufreq_data { bool per_core_dcvs; }; =20 +static struct { + struct qcom_cpufreq_data *data; +} qcom_cpufreq; + static unsigned long cpu_hw_rate, xo_rate; static bool icc_scaling_enabled; =20 @@ -489,8 +493,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_poli= cy *policy) struct of_phandle_args args; struct device_node *cpu_np; struct device *cpu_dev; - struct resource *res; - void __iomem *base; struct qcom_cpufreq_data *data; int ret, index; =20 @@ -512,43 +514,16 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_po= licy *policy) return ret; =20 index =3D args.args[0]; - - res =3D platform_get_resource(pdev, IORESOURCE_MEM, index); - if (!res) { - dev_err(dev, "failed to get mem resource %d\n", index); - return -ENODEV; - } - - if (!request_mem_region(res->start, resource_size(res), res->name)) { - dev_err(dev, "failed to request resource %pR\n", res); - return -EBUSY; - } - - base =3D ioremap(res->start, resource_size(res)); - if (!base) { - dev_err(dev, "failed to map resource %pR\n", res); - ret =3D -ENOMEM; - goto release_region; - } - - data =3D kzalloc(sizeof(*data), GFP_KERNEL); - if (!data) { - ret =3D -ENOMEM; - goto unmap_base; - } - data->soc_data =3D of_device_get_match_data(&pdev->dev); - data->base =3D base; - data->res =3D res; + data =3D &qcom_cpufreq.data[index]; =20 /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(base + data->soc_data->reg_enable) & 0x1)) { + if (!(readl_relaxed(data->base + data->soc_data->reg_enable) & 0x1)) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); - ret =3D -ENODEV; - goto error; + return -ENODEV; } =20 - if (readl_relaxed(base + data->soc_data->reg_dcvs_ctrl) & 0x1) + if (readl_relaxed(data->base + data->soc_data->reg_dcvs_ctrl) & 0x1) data->per_core_dcvs =3D true; =20 qcom_get_related_cpus(index, policy->cpus); @@ -559,14 +534,13 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_po= licy *policy) ret =3D qcom_cpufreq_hw_read_lut(cpu_dev, policy); if (ret) { dev_err(dev, "Domain-%d failed to read LUT\n", index); - goto error; + return ret; } =20 ret =3D dev_pm_opp_get_opp_count(cpu_dev); if (ret <=3D 0) { dev_err(cpu_dev, "Failed to add OPPs\n"); - ret =3D -ENODEV; - goto error; + return -ENODEV; } =20 if (policy_has_boost_freq(policy)) { @@ -575,18 +549,7 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_pol= icy *policy) dev_warn(cpu_dev, "failed to enable boost: %d\n", ret); } =20 - ret =3D qcom_cpufreq_hw_lmh_init(policy, index); - if (ret) - goto error; - - return 0; -error: - kfree(data); -unmap_base: - iounmap(base); -release_region: - release_mem_region(res->start, resource_size(res)); - return ret; + return qcom_cpufreq_hw_lmh_init(policy, index); } =20 static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) @@ -643,7 +606,7 @@ static int qcom_cpufreq_hw_driver_probe(struct platform= _device *pdev) { struct device *cpu_dev; struct clk *clk; - int ret; + int ret, i, num_domains; =20 clk =3D clk_get(&pdev->dev, "xo"); if (IS_ERR(clk)) @@ -670,6 +633,31 @@ static int qcom_cpufreq_hw_driver_probe(struct platfor= m_device *pdev) if (ret) return ret; =20 + /* Allocate qcom_cpufreq_data based on the available frequency domains in= DT */ + num_domains =3D of_property_count_elems_of_size(pdev->dev.of_node, "reg",= sizeof(u32) * 4); + if (num_domains <=3D 0) + return num_domains; + + qcom_cpufreq.data =3D devm_kzalloc(&pdev->dev, sizeof(struct qcom_cpufreq= _data) * num_domains, + GFP_KERNEL); + if (!qcom_cpufreq.data) + return -ENOMEM; + + for (i =3D 0; i < num_domains; i++) { + struct qcom_cpufreq_data *data =3D &qcom_cpufreq.data[i]; + struct resource *res; + void __iomem *base; + + base =3D devm_platform_get_and_ioremap_resource(pdev, i, &res); + if (IS_ERR(base)) { + dev_err(&pdev->dev, "Failed to map resource %pR\n", res); + return PTR_ERR(base); + } + + data->base =3D base; + data->res =3D res; + } + ret =3D cpufreq_register_driver(&cpufreq_qcom_hw_driver); if (ret) dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); --=20 2.25.1 From nobody Wed Apr 8 10:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36CF0C04A95 for ; Tue, 25 Oct 2022 07:34:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231826AbiJYHe0 (ORCPT ); Tue, 25 Oct 2022 03:34:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231834AbiJYHdf (ORCPT ); Tue, 25 Oct 2022 03:33:35 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6F88159A11 for ; Tue, 25 Oct 2022 00:33:34 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id w189so9620174pfw.4 for ; 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Tue, 25 Oct 2022 00:33:34 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:32 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 5/7] cpufreq: qcom-hw: Use cached dev pointer in probe() Date: Tue, 25 Oct 2022 13:02:52 +0530 Message-Id: <20221025073254.1564622-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There are multiple instances of dev pointer used in the probe() function. Instead of referencing pdev->dev all the time, let's use a cached dev pointer to simplify the code. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index 1842e9facaa1..bc991ef10c05 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -604,18 +604,19 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = =3D { =20 static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct device *dev =3D &pdev->dev; struct device *cpu_dev; struct clk *clk; int ret, i, num_domains; =20 - clk =3D clk_get(&pdev->dev, "xo"); + clk =3D clk_get(dev, "xo"); if (IS_ERR(clk)) return PTR_ERR(clk); =20 xo_rate =3D clk_get_rate(clk); clk_put(clk); =20 - clk =3D clk_get(&pdev->dev, "alternate"); + clk =3D clk_get(dev, "alternate"); if (IS_ERR(clk)) return PTR_ERR(clk); =20 @@ -634,11 +635,11 @@ static int qcom_cpufreq_hw_driver_probe(struct platfo= rm_device *pdev) return ret; =20 /* Allocate qcom_cpufreq_data based on the available frequency domains in= DT */ - num_domains =3D of_property_count_elems_of_size(pdev->dev.of_node, "reg",= sizeof(u32) * 4); + num_domains =3D of_property_count_elems_of_size(dev->of_node, "reg", size= of(u32) * 4); if (num_domains <=3D 0) return num_domains; =20 - qcom_cpufreq.data =3D devm_kzalloc(&pdev->dev, sizeof(struct qcom_cpufreq= _data) * num_domains, + qcom_cpufreq.data =3D devm_kzalloc(dev, sizeof(struct qcom_cpufreq_data) = * num_domains, GFP_KERNEL); if (!qcom_cpufreq.data) return -ENOMEM; @@ -650,7 +651,7 @@ static int qcom_cpufreq_hw_driver_probe(struct platform= _device *pdev) =20 base =3D devm_platform_get_and_ioremap_resource(pdev, i, &res); if (IS_ERR(base)) { - dev_err(&pdev->dev, "Failed to map resource %pR\n", res); + dev_err(dev, "Failed to map resource %pR\n", res); return PTR_ERR(base); } =20 @@ -660,9 +661,9 @@ static int qcom_cpufreq_hw_driver_probe(struct platform= _device *pdev) =20 ret =3D cpufreq_register_driver(&cpufreq_qcom_hw_driver); if (ret) - dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n"); + dev_err(dev, "CPUFreq HW driver failed to register\n"); else - dev_dbg(&pdev->dev, "QCOM CPUFreq HW driver initialized\n"); + dev_dbg(dev, "QCOM CPUFreq HW driver initialized\n"); =20 return ret; } --=20 2.25.1 From nobody Wed Apr 8 10:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ABFEC38A2D for ; Tue, 25 Oct 2022 07:34:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231172AbiJYHec (ORCPT ); Tue, 25 Oct 2022 03:34:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231863AbiJYHdn (ORCPT ); Tue, 25 Oct 2022 03:33:43 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EBAB159963 for ; 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charset="utf-8" soc_data is a static info of the driver and thus no need to cache it inside the qcom_cpufreq_data struct which is allocated per frequency domain. So, move it inside qcom_cpufreq struct. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index bc991ef10c05..76f840636828 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -42,7 +42,6 @@ struct qcom_cpufreq_soc_data { struct qcom_cpufreq_data { void __iomem *base; struct resource *res; - const struct qcom_cpufreq_soc_data *soc_data; =20 /* * Mutex to synchronize between de-init sequence and re-starting LMh @@ -60,6 +59,7 @@ struct qcom_cpufreq_data { =20 static struct { struct qcom_cpufreq_data *data; + const struct qcom_cpufreq_soc_data *soc_data; } qcom_cpufreq; =20 static unsigned long cpu_hw_rate, xo_rate; @@ -110,7 +110,7 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_= policy *policy, unsigned int index) { struct qcom_cpufreq_data *data =3D policy->driver_data; - const struct qcom_cpufreq_soc_data *soc_data =3D data->soc_data; + const struct qcom_cpufreq_soc_data *soc_data =3D qcom_cpufreq.soc_data; unsigned long freq =3D policy->freq_table[index].frequency; unsigned int i; =20 @@ -138,7 +138,7 @@ static unsigned int qcom_cpufreq_hw_get(unsigned int cp= u) return 0; =20 data =3D policy->driver_data; - soc_data =3D data->soc_data; + soc_data =3D qcom_cpufreq.soc_data; =20 index =3D readl_relaxed(data->base + soc_data->reg_perf_state); index =3D min(index, LUT_MAX_ENTRIES - 1); @@ -150,7 +150,7 @@ static unsigned int qcom_cpufreq_hw_fast_switch(struct = cpufreq_policy *policy, unsigned int target_freq) { struct qcom_cpufreq_data *data =3D policy->driver_data; - const struct qcom_cpufreq_soc_data *soc_data =3D data->soc_data; + const struct qcom_cpufreq_soc_data *soc_data =3D qcom_cpufreq.soc_data; unsigned int index; unsigned int i; =20 @@ -174,7 +174,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_= dev, unsigned long rate; int ret; struct qcom_cpufreq_data *drv_data =3D policy->driver_data; - const struct qcom_cpufreq_soc_data *soc_data =3D drv_data->soc_data; + const struct qcom_cpufreq_soc_data *soc_data =3D qcom_cpufreq.soc_data; =20 table =3D kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL); if (!table) @@ -291,10 +291,10 @@ static unsigned long qcom_lmh_get_throttle_freq(struc= t qcom_cpufreq_data *data) { unsigned int lval; =20 - if (data->soc_data->reg_current_vote) - lval =3D readl_relaxed(data->base + data->soc_data->reg_current_vote) & = 0x3ff; + if (qcom_cpufreq.soc_data->reg_current_vote) + lval =3D readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_current_v= ote) & 0x3ff; else - lval =3D readl_relaxed(data->base + data->soc_data->reg_domain_state) & = 0xff; + lval =3D readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_domain_st= ate) & 0xff; =20 return lval * xo_rate; } @@ -366,9 +366,9 @@ static irqreturn_t qcom_lmh_dcvs_handle_irq(int irq, vo= id *data) disable_irq_nosync(c_data->throttle_irq); schedule_delayed_work(&c_data->throttle_work, 0); =20 - if (c_data->soc_data->reg_intr_clr) + if (qcom_cpufreq.soc_data->reg_intr_clr) writel_relaxed(GT_IRQ_STATUS, - c_data->base + c_data->soc_data->reg_intr_clr); + c_data->base + qcom_cpufreq.soc_data->reg_intr_clr); =20 return IRQ_HANDLED; } @@ -514,16 +514,15 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_po= licy *policy) return ret; =20 index =3D args.args[0]; - data->soc_data =3D of_device_get_match_data(&pdev->dev); data =3D &qcom_cpufreq.data[index]; =20 /* HW should be in enabled state to proceed */ - if (!(readl_relaxed(data->base + data->soc_data->reg_enable) & 0x1)) { + if (!(readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_enable) & 0x1= )) { dev_err(dev, "Domain-%d cpufreq hardware not enabled\n", index); return -ENODEV; } =20 - if (readl_relaxed(data->base + data->soc_data->reg_dcvs_ctrl) & 0x1) + if (readl_relaxed(data->base + qcom_cpufreq.soc_data->reg_dcvs_ctrl) & 0x= 1) data->per_core_dcvs =3D true; =20 qcom_get_related_cpus(index, policy->cpus); @@ -644,6 +643,8 @@ static int qcom_cpufreq_hw_driver_probe(struct platform= _device *pdev) if (!qcom_cpufreq.data) return -ENOMEM; =20 + qcom_cpufreq.soc_data =3D of_device_get_match_data(dev); + for (i =3D 0; i < num_domains; i++) { struct qcom_cpufreq_data *data =3D &qcom_cpufreq.data[i]; struct resource *res; --=20 2.25.1 From nobody Wed Apr 8 10:18:54 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA10AC04A95 for ; Tue, 25 Oct 2022 07:34:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231849AbiJYHek (ORCPT ); Tue, 25 Oct 2022 03:34:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231908AbiJYHeF (ORCPT ); Tue, 25 Oct 2022 03:34:05 -0400 Received: from mail-pl1-x642.google.com (mail-pl1-x642.google.com [IPv6:2607:f8b0:4864:20::642]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7734153E17 for ; Tue, 25 Oct 2022 00:33:44 -0700 (PDT) Received: by mail-pl1-x642.google.com with SMTP id 4so4584961pli.0 for ; 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Tue, 25 Oct 2022 00:33:43 -0700 (PDT) Received: from localhost.localdomain ([117.193.211.146]) by smtp.gmail.com with ESMTPSA id c1-20020a17090a4d0100b0020dda7efe61sm5048369pjg.5.2022.10.25.00.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Oct 2022 00:33:42 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 7/7] cpufreq: qcom-hw: Add CPU clock provider support Date: Tue, 25 Oct 2022 13:02:54 +0530 Message-Id: <20221025073254.1564622-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> References: <20221025073254.1564622-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Qcom CPUFreq hardware (EPSS/OSM) controls clock and voltage to the CPU cores. But this relationship is not represented with the clk framework so far. So, let's make the qcom-cpufreq-hw driver a clock provider. This makes the clock producer/consumer relationship cleaner and is also useful for CPU related frameworks like OPP to know the frequency at which the CPUs are running. The clock frequency provided by the driver is for each frequency domain. We cannot get the frequency of each CPU core because, not all platforms support per-core DCVS feature. Also the frequency supplied by the driver is the actual frequency that comes out of the EPSS/OSM block after the DCVS operation. This frequency is not same as what the CPUFreq framework has set but it is the one that gets supplied to the CPUs after throttling by LMh. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufr= eq-hw.c index 76f840636828..66677db3e267 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -53,6 +54,7 @@ struct qcom_cpufreq_data { bool cancel_throttle; struct delayed_work throttle_work; struct cpufreq_policy *policy; + struct clk_hw cpu_clk; =20 bool per_core_dcvs; }; @@ -601,8 +603,20 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = =3D { .ready =3D qcom_cpufreq_ready, }; =20 +static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsign= ed long parent_rate) +{ + struct qcom_cpufreq_data *data =3D container_of(hw, struct qcom_cpufreq_d= ata, cpu_clk); + + return qcom_lmh_get_throttle_freq(data) / HZ_PER_KHZ; +} + +static const struct clk_ops qcom_cpufreq_hw_clk_ops =3D { + .recalc_rate =3D qcom_cpufreq_hw_recalc_rate, +}; + static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct clk_hw_onecell_data *clk_data; struct device *dev =3D &pdev->dev; struct device *cpu_dev; struct clk *clk; @@ -645,8 +659,16 @@ static int qcom_cpufreq_hw_driver_probe(struct platfor= m_device *pdev) =20 qcom_cpufreq.soc_data =3D of_device_get_match_data(dev); =20 + clk_data =3D devm_kzalloc(dev, struct_size(clk_data, hws, num_domains), G= FP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num =3D num_domains; + for (i =3D 0; i < num_domains; i++) { struct qcom_cpufreq_data *data =3D &qcom_cpufreq.data[i]; + static struct clk_init_data init =3D {}; + const char *clk_name; struct resource *res; void __iomem *base; =20 @@ -658,6 +680,27 @@ static int qcom_cpufreq_hw_driver_probe(struct platfor= m_device *pdev) =20 data->base =3D base; data->res =3D res; + + /* Register CPU clock for each frequency domain */ + clk_name =3D devm_kasprintf(dev, GFP_KERNEL, "qcom_cpufreq%d", i); + init.name =3D clk_name; + init.flags =3D CLK_GET_RATE_NOCACHE; + init.ops =3D &qcom_cpufreq_hw_clk_ops; + data->cpu_clk.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &data->cpu_clk); + if (ret < 0) { + dev_err(dev, "Failed to register Qcom CPUFreq clock\n"); + return ret; + } + + clk_data->hws[i] =3D &data->cpu_clk; + } + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret < 0) { + dev_err(dev, "Failed to add Qcom CPUFreq clock provider\n"); + return ret; } =20 ret =3D cpufreq_register_driver(&cpufreq_qcom_hw_driver); --=20 2.25.1