From nobody Sat Sep 21 11:39:37 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DDC19C67871 for ; Tue, 25 Oct 2022 01:50:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231742AbiJYBu6 (ORCPT ); Mon, 24 Oct 2022 21:50:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231640AbiJYBud (ORCPT ); Mon, 24 Oct 2022 21:50:33 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87E9C32AAE; Mon, 24 Oct 2022 18:47:08 -0700 (PDT) X-UUID: 0c3706d845d44169b38af17017c713f0-20221025 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=ieQS2Mw52Pi8udyGNEflIMqPTtMIjzLnr/hwmBb+3cw=; b=S9cyxmxQQQqWWF3clzmqkWQywedKVrUIqyVQOgmsUGNClV40NpExftamVpmx7Phiej18Oo65G1YZNmdm7Kk9i1lAZPhYlZt+WJaMEKFbLSnN/bSIg7ejCdtjWyWTWJzWPREhN0ozkz+VNX/hfVX8ypfVdz1zZBg27ptCCkBQP20=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:4ae20d06-25a9-4b1e-a19a-2248aff8c791,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.12,REQID:4ae20d06-25a9-4b1e-a19a-2248aff8c791,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:62cd327,CLOUDID:1f47f86c-89d3-4bfa-baad-dc632a24bca3,B ulkID:221025094704UJJN74HI,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 0c3706d845d44169b38af17017c713f0-20221025 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 616003830; Tue, 25 Oct 2022 09:47:04 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.186) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 25 Oct 2022 09:47:02 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 25 Oct 2022 09:47:01 +0800 From: Mingjia Zhang To: Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , "Hans Verkuil" , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa CC: George Sun , Xiaoyong Lu , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , "Steve Cho" , , , , , , Subject: [PATCH v5] media: mediatek: vcodec: Add to support VP9 inner racing mode Date: Tue, 25 Oct 2022 09:46:59 +0800 Message-ID: <20221025014659.7158-1-mingjia.zhang@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable VP9 inner racing mode We send lat trans buffer to the core when trigger lat to work, instead of w= aiting for the lat decode done. It can be reduce decoder latency. Signed-off-by: Mingjia Zhang --- Changes from v3: - CTS/GTS test pass - Fluster result: Ran 275/303 tests successfully Changes from v2: - CTS/GTS test pass - Fluster result: Ran 240/303 tests successfully Changes from v1: - CTS/GTS test pass --- .../vcodec/vdec/vdec_vp9_req_lat_if.c | 85 ++++++++++--------- 1 file changed, 47 insertions(+), 38 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_i= f.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c index 81de876d51267..1b39119c89951 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp9_req_lat_if.c @@ -436,6 +436,7 @@ struct vdec_vp9_slice_ref { * @frame_ctx: 4 frame context according to VP9 Spec * @frame_ctx_helper: 4 frame context according to newest kernel spec * @dirty: state of each frame context + * @local_vsi: local instance vsi information * @init_vsi: vsi used for initialized VP9 instance * @vsi: vsi used for decoding/flush ... * @core_vsi: vsi used for Core stage @@ -482,6 +483,8 @@ struct vdec_vp9_slice_instance { struct v4l2_vp9_frame_context frame_ctx_helper; unsigned char dirty[4]; =20 + struct vdec_vp9_slice_vsi local_vsi; + /* MicroP vsi */ union { struct vdec_vp9_slice_init_vsi *init_vsi; @@ -1616,16 +1619,10 @@ static int vdec_vp9_slice_update_single(struct vdec= _vp9_slice_instance *instance } =20 static int vdec_vp9_slice_update_lat(struct vdec_vp9_slice_instance *insta= nce, - struct vdec_lat_buf *lat_buf, - struct vdec_vp9_slice_pfc *pfc) + struct vdec_vp9_slice_vsi *vsi) { - struct vdec_vp9_slice_vsi *vsi; - - vsi =3D &pfc->vsi; - memcpy(&pfc->state[0], &vsi->state, sizeof(vsi->state)); - mtk_vcodec_debug(instance, "Frame %u LAT CRC 0x%08x %lx %lx\n", - pfc->seq, vsi->state.crc[0], + (instance->seq - 1), vsi->state.crc[0], (unsigned long)vsi->trans.dma_addr, (unsigned long)vsi->trans.dma_addr_end); =20 @@ -2090,6 +2087,13 @@ static int vdec_vp9_slice_lat_decode(void *h_vdec, s= truct mtk_vcodec_mem *bs, return ret; } =20 + if (IS_VDEC_INNER_RACING(ctx->dev->dec_capability)) { + vdec_vp9_slice_vsi_from_remote(vsi, instance->vsi, 0); + memcpy(&instance->local_vsi, vsi, sizeof(*vsi)); + vdec_msg_queue_qbuf(&ctx->dev->msg_queue_core_ctx, lat_buf); + vsi =3D &instance->local_vsi; + } + if (instance->irq) { ret =3D mtk_vcodec_wait_for_done_ctx(ctx, MTK_INST_IRQ_RECEIVED, WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0); @@ -2102,22 +2106,25 @@ static int vdec_vp9_slice_lat_decode(void *h_vdec, = struct mtk_vcodec_mem *bs, } =20 vdec_vp9_slice_vsi_from_remote(vsi, instance->vsi, 0); - ret =3D vdec_vp9_slice_update_lat(instance, lat_buf, pfc); + ret =3D vdec_vp9_slice_update_lat(instance, vsi); =20 - /* LAT trans full, no more UBE or decode timeout */ - if (ret) { - mtk_vcodec_err(instance, "VP9 decode error: %d\n", ret); - return ret; - } + if (!IS_VDEC_INNER_RACING(ctx->dev->dec_capability)) + /* LAT trans full, no more UBE or decode timeout */ + if (ret) { + mtk_vcodec_err(instance, "frame[%d] decode error: %d\n", + ret, (instance->seq - 1)); + return ret; + } =20 - mtk_vcodec_debug(instance, "lat dma addr: 0x%lx 0x%lx\n", - (unsigned long)pfc->vsi.trans.dma_addr, - (unsigned long)pfc->vsi.trans.dma_addr_end); =20 - vdec_msg_queue_update_ube_wptr(&ctx->msg_queue, - vsi->trans.dma_addr_end + - ctx->msg_queue.wdma_addr.dma_addr); - vdec_msg_queue_qbuf(&ctx->dev->msg_queue_core_ctx, lat_buf); + vsi->trans.dma_addr_end +=3D ctx->msg_queue.wdma_addr.dma_addr; + vdec_msg_queue_update_ube_wptr(&ctx->msg_queue, vsi->trans.dma_addr_end); + if (!IS_VDEC_INNER_RACING(ctx->dev->dec_capability)) + vdec_msg_queue_qbuf(&ctx->dev->msg_queue_core_ctx, lat_buf); + + mtk_vcodec_debug(instance, "lat trans end addr(0x%lx), ube start addr(0x%= lx)\n", + (unsigned long)vsi->trans.dma_addr_end, + (unsigned long)ctx->msg_queue.wdma_addr.dma_addr); =20 return 0; } @@ -2139,40 +2146,40 @@ static int vdec_vp9_slice_decode(void *h_vdec, stru= ct mtk_vcodec_mem *bs, static int vdec_vp9_slice_core_decode(struct vdec_lat_buf *lat_buf) { struct vdec_vp9_slice_instance *instance; - struct vdec_vp9_slice_pfc *pfc; + struct vdec_vp9_slice_pfc *pfc =3D NULL; struct mtk_vcodec_ctx *ctx =3D NULL; struct vdec_fb *fb =3D NULL; int ret =3D -EINVAL; =20 if (!lat_buf) - goto err; + return -EINVAL; =20 pfc =3D lat_buf->private_data; ctx =3D lat_buf->ctx; if (!pfc || !ctx) - goto err; + return -EINVAL; =20 instance =3D ctx->drv_handle; if (!instance) - goto err; + return -EINVAL; =20 fb =3D ctx->dev->vdec_pdata->get_cap_buffer(ctx); if (!fb) { ret =3D -EBUSY; - goto err; + goto vdec_dec_end; } =20 ret =3D vdec_vp9_slice_setup_core(instance, fb, lat_buf, pfc); if (ret) { mtk_vcodec_err(instance, "vdec_vp9_slice_setup_core\n"); - goto err; + goto vdec_dec_end; } vdec_vp9_slice_vsi_to_remote(&pfc->vsi, instance->core_vsi); =20 ret =3D vpu_dec_core(&instance->vpu); if (ret) { mtk_vcodec_err(instance, "vpu_dec_core\n"); - goto err; + goto vdec_dec_end; } =20 if (instance->irq) { @@ -2190,24 +2197,26 @@ static int vdec_vp9_slice_core_decode(struct vdec_l= at_buf *lat_buf) ret =3D vdec_vp9_slice_update_core(instance, lat_buf, pfc); if (ret) { mtk_vcodec_err(instance, "vdec_vp9_slice_update_core\n"); - goto err; + goto vdec_dec_end; } =20 - pfc->vsi.trans.dma_addr_end +=3D ctx->msg_queue.wdma_addr.dma_addr; mtk_vcodec_debug(instance, "core dma_addr_end 0x%lx\n", (unsigned long)pfc->vsi.trans.dma_addr_end); - vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, pfc->vsi.trans.dma_addr_e= nd); - ctx->dev->vdec_pdata->cap_to_disp(ctx, 0, lat_buf->src_buf_req); - - return 0; =20 -err: - if (ctx && pfc) { - /* always update read pointer */ - vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, pfc->vsi.trans.dma_addr_= end); +vdec_dec_end: + /* always update read pointer */ + if (IS_VDEC_INNER_RACING(ctx->dev->dec_capability)) + vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, + pfc->vsi.trans.dma_addr); + else + vdec_msg_queue_update_ube_rptr(&ctx->msg_queue, + pfc->vsi.trans.dma_addr_end); =20 + if (ret) { if (fb) ctx->dev->vdec_pdata->cap_to_disp(ctx, 1, lat_buf->src_buf_req); + } else { + ctx->dev->vdec_pdata->cap_to_disp(ctx, 0, lat_buf->src_buf_req); } return ret; } --=20 2.18.0