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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id l24-20020a056000023800b00236627c078esm6322307wrz.110.2022.10.24.06.16.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Oct 2022 06:16:32 -0700 (PDT) From: Fadwa CHIBY X-Google-Original-From: Fadwa CHIBY To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Johnson Wang , "Zhiyong . Tao" Cc: Fabien Parent , Fadwa CHIBY , Sen Chu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 3/3] soc: mediatek: pwrap: add mt8365 SoC support Date: Mon, 24 Oct 2022 15:15:43 +0200 Message-Id: <20221024131544.31219-4-fchiby@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024131544.31219-1-fchiby@baylibre.com> References: <20221024131544.31219-1-fchiby@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add PMIC Wrap support for MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Fadwa CHIBY Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 78 ++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index d56b00023ccd..15789a03e6c6 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -983,6 +983,68 @@ static int mt8195_regs[] =3D { [PWRAP_WACS2_RDATA] =3D 0x8A8, }; =20 +static int mt8365_regs[] =3D { + [PWRAP_MUX_SEL] =3D 0x0, + [PWRAP_WRAP_EN] =3D 0x4, + [PWRAP_DIO_EN] =3D 0x8, + [PWRAP_CSHEXT_WRITE] =3D 0x24, + [PWRAP_CSHEXT_READ] =3D 0x28, + [PWRAP_STAUPD_PRD] =3D 0x3c, + [PWRAP_STAUPD_GRPEN] =3D 0x40, + [PWRAP_STAUPD_MAN_TRIG] =3D 0x58, + [PWRAP_STAUPD_STA] =3D 0x5c, + [PWRAP_WRAP_STA] =3D 0x60, + [PWRAP_HARB_INIT] =3D 0x64, + [PWRAP_HARB_HPRIO] =3D 0x68, + [PWRAP_HIPRIO_ARB_EN] =3D 0x6c, + [PWRAP_HARB_STA0] =3D 0x70, + [PWRAP_HARB_STA1] =3D 0x74, + [PWRAP_MAN_EN] =3D 0x7c, + [PWRAP_MAN_CMD] =3D 0x80, + [PWRAP_MAN_RDATA] =3D 0x84, + [PWRAP_MAN_VLDCLR] =3D 0x88, + [PWRAP_WACS0_EN] =3D 0x8c, + [PWRAP_INIT_DONE0] =3D 0x90, + [PWRAP_WACS0_CMD] =3D 0xc00, + [PWRAP_WACS0_RDATA] =3D 0xc04, + [PWRAP_WACS0_VLDCLR] =3D 0xc08, + [PWRAP_WACS1_EN] =3D 0x94, + [PWRAP_INIT_DONE1] =3D 0x98, + [PWRAP_WACS2_EN] =3D 0x9c, + [PWRAP_INIT_DONE2] =3D 0xa0, + [PWRAP_WACS2_CMD] =3D 0xc20, + [PWRAP_WACS2_RDATA] =3D 0xc24, + [PWRAP_WACS2_VLDCLR] =3D 0xc28, + [PWRAP_INT_EN] =3D 0xb4, + [PWRAP_INT_FLG_RAW] =3D 0xb8, + [PWRAP_INT_FLG] =3D 0xbc, + [PWRAP_INT_CLR] =3D 0xc0, + [PWRAP_SIG_ADR] =3D 0xd4, + [PWRAP_SIG_MODE] =3D 0xd8, + [PWRAP_SIG_VALUE] =3D 0xdc, + [PWRAP_SIG_ERRVAL] =3D 0xe0, + [PWRAP_CRC_EN] =3D 0xe4, + [PWRAP_TIMER_EN] =3D 0xe8, + [PWRAP_TIMER_STA] =3D 0xec, + [PWRAP_WDT_UNIT] =3D 0xf0, + [PWRAP_WDT_SRC_EN] =3D 0xf4, + [PWRAP_WDT_FLG] =3D 0xfc, + [PWRAP_DEBUG_INT_SEL] =3D 0x104, + [PWRAP_CIPHER_KEY_SEL] =3D 0x1c4, + [PWRAP_CIPHER_IV_SEL] =3D 0x1c8, + [PWRAP_CIPHER_RDY] =3D 0x1d0, + [PWRAP_CIPHER_MODE] =3D 0x1d4, + [PWRAP_CIPHER_SWRST] =3D 0x1d8, + [PWRAP_DCM_EN] =3D 0x1dc, + [PWRAP_DCM_DBC_PRD] =3D 0x1e0, + [PWRAP_EINT_STA0_ADR] =3D 0x44, + [PWRAP_EINT_STA1_ADR] =3D 0x48, + [PWRAP_INT1_EN] =3D 0xc4, + [PWRAP_INT1_FLG] =3D 0xcc, + [PWRAP_INT1_CLR] =3D 0xd0, + [PWRAP_WDT_SRC_EN_1] =3D 0xf8, +}; + static int mt8516_regs[] =3D { [PWRAP_MUX_SEL] =3D 0x0, [PWRAP_WRAP_EN] =3D 0x4, @@ -1139,6 +1201,7 @@ enum pwrap_type { PWRAP_MT8183, PWRAP_MT8186, PWRAP_MT8195, + PWRAP_MT8365, PWRAP_MT8516, }; =20 @@ -1598,6 +1661,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8186: + case PWRAP_MT8365: case PWRAP_MT8516: pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); break; @@ -2106,6 +2170,19 @@ static struct pmic_wrapper_type pwrap_mt8195 =3D { .init_soc_specific =3D NULL, }; =20 +static const struct pmic_wrapper_type pwrap_mt8365 =3D { + .regs =3D mt8365_regs, + .type =3D PWRAP_MT8365, + .arb_en_all =3D 0x3ffff, + .int_en_all =3D 0x7f1fffff, + .int1_en_all =3D 0x0, + .spi_w =3D PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src =3D PWRAP_WDT_SRC_MASK_ALL, + .caps =3D PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, + .init_reg_clock =3D pwrap_common_init_reg_clock, + .init_soc_specific =3D NULL, +}; + static struct pmic_wrapper_type pwrap_mt8516 =3D { .regs =3D mt8516_regs, .type =3D PWRAP_MT8516, @@ -2143,6 +2220,7 @@ static const struct of_device_id of_pwrap_match_tbl[]= =3D { { .compatible =3D "mediatek,mt8183-pwrap", .data =3D &pwrap_mt8183 }, { .compatible =3D "mediatek,mt8186-pwrap", .data =3D &pwrap_mt8186 }, { .compatible =3D "mediatek,mt8195-pwrap", .data =3D &pwrap_mt8195 }, + { .compatible =3D "mediatek,mt8365-pwrap", .data =3D &pwrap_mt8365 }, { .compatible =3D "mediatek,mt8516-pwrap", .data =3D &pwrap_mt8516 }, { /* sentinel */ } }; --=20 2.25.1