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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id l24-20020a056000023800b00236627c078esm6322307wrz.110.2022.10.24.06.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Oct 2022 06:16:16 -0700 (PDT) From: Fadwa CHIBY X-Google-Original-From: Fadwa CHIBY To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Johnson Wang , "Zhiyong . Tao" Cc: Fabien Parent , Fadwa CHIBY , Rob Herring , Tinghan Shen , Sen Chu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 1/3] dt-bindings: soc: mediatek: pwrap: add MT8365 SoC bindings Date: Mon, 24 Oct 2022 15:15:41 +0200 Message-Id: <20221024131544.31219-2-fchiby@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024131544.31219-1-fchiby@baylibre.com> References: <20221024131544.31219-1-fchiby@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add pwrap binding documentation for Signed-off-by: Fabien Parent Signed-off-by: Fadwa CHIBY Acked-by: Rob Herring --- Documentation/devicetree/bindings/soc/mediatek/pwrap.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Doc= umentation/devicetree/bindings/soc/mediatek/pwrap.txt index d24e2bc444be..8424b93c432e 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -30,6 +30,7 @@ Required properties in pwrap device node. "mediatek,mt8186-pwrap" for MT8186 SoCs "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs "mediatek,mt8195-pwrap" for MT8195 SoCs + "mediatek,mt8365-pwrap" for MT8365 SoCs "mediatek,mt8516-pwrap" for MT8516 SoCs - interrupts: IRQ for pwrap in SOC - reg-names: "pwrap" is required; "pwrap-bridge" is optional. @@ -39,6 +40,8 @@ Required properties in pwrap device node. - clock-names: Must include the following entries: "spi": SPI bus clock "wrap": Main module clock + "sys": System module clock (for MT8365 SoC) + "tmr": Timer module clock (for MT8365 SoC) - clocks: Must contain an entry for each entry in clock-names. =20 Optional properities: --=20 2.25.1 From nobody Sat Sep 21 12:50:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31277C38A2D for ; Mon, 24 Oct 2022 16:56:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230307AbiJXQ4G (ORCPT ); Mon, 24 Oct 2022 12:56:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236073AbiJXQzi (ORCPT ); Mon, 24 Oct 2022 12:55:38 -0400 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35FBC1C9040 for ; Mon, 24 Oct 2022 08:36:35 -0700 (PDT) Received: by mail-wm1-f50.google.com with SMTP id v130-20020a1cac88000000b003bcde03bd44so10213743wme.5 for ; Mon, 24 Oct 2022 08:36:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Wg8m4GG4QjexJtQ30uCclpZbT7iCGr4ggTfboiYgY7w=; b=W0aOZLMhucJGkDWFZ4eLo90W7KJSaOP4g5shimjmGiPnHWVRLfBBjrRLoSODsg8dq0 xrLJ3Z755FPKU1WQxarAGiMXvi8RX+0JoM5em8BbtYKHKLPAXM9dFDbVbFcQHhvbThut VbZ7y5XQ6aJlXy3cb7DJu8iGvR7L3v2aeVIW/sSJ7jfeRdsa3LlfVjRlOkpr/6UU6EK3 e7ru/CixxS1601VgYzo3glYEZrxDkJ/HbIGGG0doobG8avEEHQYhvkjm0kB18NozqrWi OKVhFW9wYfP0Rz5jaipJJUTB6Xff9U8U3pBrhTmXd7kjKebaAIEI/QC3Sio+ha1RT8by xZkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wg8m4GG4QjexJtQ30uCclpZbT7iCGr4ggTfboiYgY7w=; b=4iaPomot1TpsHX1bxa59j58O8zXNaxF4ep0gsvnu9EK6dL4HDlnIhfpUQXdH844PyZ Mn2n0gtJLcgXXrBAxd44XD5wFMlLCLZE8xbN9yvMFsRHipIuvxs9P9FecUJhHd+grenC WM75QWj9FJVPVmcLx596tnCjnvVzK8SHIDaqJLjE759tHbquiqsdbua5jJPLtbxdNTLZ N2EkHzJoKhfDYMKQO9iGCc4bOVLPU6x3MyqC6XajrtXWeUJdA8hZ3VGcjMI9B4rXSFbw 4MFZeHlMcKFvR+T3/zEPF07GiAzC5htNm6WCQRhNqxNhL6kTU8t3EZRhOVX4BLqzXCeC bcXg== X-Gm-Message-State: ACrzQf0aVPCsMD6NJcnMTU9Kz75Mc8tOQ1ynbKZVpd4Hanw8baHar4ES Y/HaycYz7Teh3DCGLHsfuAZyCe+OnAoEA5oN X-Google-Smtp-Source: AMsMyM540QyJygyyI1aVFU3oRNSF3FU9t13sfAoCzM4zbaT4cykElqhdjbjaVQODkTz+W8n50nxENw== X-Received: by 2002:a05:600c:5252:b0:3c6:f478:96e6 with SMTP id fc18-20020a05600c525200b003c6f47896e6mr29614762wmb.75.1666617383603; Mon, 24 Oct 2022 06:16:23 -0700 (PDT) Received: from fadwachiby.baylibre (laubervilliers-658-1-213-31.w90-63.abo.wanadoo.fr. [90.63.244.31]) by smtp.gmail.com with ESMTPSA id l24-20020a056000023800b00236627c078esm6322307wrz.110.2022.10.24.06.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Oct 2022 06:16:22 -0700 (PDT) From: Fadwa CHIBY X-Google-Original-From: Fadwa CHIBY To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Johnson Wang , "Zhiyong . Tao" Cc: Fabien Parent , Fadwa CHIBY , Sen Chu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 2/3] soc: mediatek: pwrap: add support for sys & tmr clocks Date: Mon, 24 Oct 2022 15:15:42 +0200 Message-Id: <20221024131544.31219-3-fchiby@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024131544.31219-1-fchiby@baylibre.com> References: <20221024131544.31219-1-fchiby@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent MT8365 requires an extra 2 clocks to be enabled to behave correctly. Add support these 2 clocks, they are made optional since they seem to be present only on MT8365. Signed-off-by: Fabien Parent Signed-off-by: Fadwa CHIBY Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 36 ++++++++++++++++++++++++---- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index eb82ae06697f..d56b00023ccd 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -1171,6 +1171,8 @@ struct pmic_wrapper { const struct pwrap_slv_type *slave; struct clk *clk_spi; struct clk *clk_wrap; + struct clk *clk_sys; + struct clk *clk_tmr; struct reset_control *rstc; =20 struct reset_control *rstc_bridge; @@ -2214,6 +2216,20 @@ static int pwrap_probe(struct platform_device *pdev) return PTR_ERR(wrp->clk_wrap); } =20 + wrp->clk_sys =3D devm_clk_get_optional(wrp->dev, "sys"); + if (IS_ERR(wrp->clk_sys)) { + return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_sys), + "failed to get clock: %pe\n", + wrp->clk_sys); + } + + wrp->clk_tmr =3D devm_clk_get_optional(wrp->dev, "tmr"); + if (IS_ERR(wrp->clk_tmr)) { + return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_tmr), + "failed to get clock: %pe\n", + wrp->clk_tmr); + } + ret =3D clk_prepare_enable(wrp->clk_spi); if (ret) return ret; @@ -2222,6 +2238,14 @@ static int pwrap_probe(struct platform_device *pdev) if (ret) goto err_out1; =20 + ret =3D clk_prepare_enable(wrp->clk_sys); + if (ret) + goto err_out2; + + ret =3D clk_prepare_enable(wrp->clk_tmr); + if (ret) + goto err_out3; + /* Enable internal dynamic clock */ if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) { pwrap_writel(wrp, 1, PWRAP_DCM_EN); @@ -2236,7 +2260,7 @@ static int pwrap_probe(struct platform_device *pdev) ret =3D pwrap_init(wrp); if (ret) { dev_dbg(wrp->dev, "init failed with %d\n", ret); - goto err_out2; + goto err_out4; } } =20 @@ -2250,7 +2274,7 @@ static int pwrap_probe(struct platform_device *pdev) if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) { dev_dbg(wrp->dev, "initialization isn't finished\n"); ret =3D -ENODEV; - goto err_out2; + goto err_out4; } =20 /* Initialize watchdog, may not be done by the bootloader */ @@ -2288,7 +2312,7 @@ static int pwrap_probe(struct platform_device *pdev) IRQF_TRIGGER_HIGH, "mt-pmic-pwrap", wrp); if (ret) - goto err_out2; + goto err_out4; =20 wrp->regmap =3D devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops-= >regmap); if (IS_ERR(wrp->regmap)) { @@ -2300,11 +2324,15 @@ static int pwrap_probe(struct platform_device *pdev) if (ret) { dev_dbg(wrp->dev, "failed to create child devices at %pOF\n", np); - goto err_out2; + goto err_out4; } =20 return 0; =20 +err_out4: + clk_disable_unprepare(wrp->clk_tmr); +err_out3: + clk_disable_unprepare(wrp->clk_sys); err_out2: clk_disable_unprepare(wrp->clk_wrap); err_out1: --=20 2.25.1 From nobody Sat Sep 21 12:50:30 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3344C67871 for ; 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[90.63.244.31]) by smtp.gmail.com with ESMTPSA id l24-20020a056000023800b00236627c078esm6322307wrz.110.2022.10.24.06.16.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Oct 2022 06:16:32 -0700 (PDT) From: Fadwa CHIBY X-Google-Original-From: Fadwa CHIBY To: Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Johnson Wang , "Zhiyong . Tao" Cc: Fabien Parent , Fadwa CHIBY , Sen Chu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 3/3] soc: mediatek: pwrap: add mt8365 SoC support Date: Mon, 24 Oct 2022 15:15:43 +0200 Message-Id: <20221024131544.31219-4-fchiby@baylibre.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024131544.31219-1-fchiby@baylibre.com> References: <20221024131544.31219-1-fchiby@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabien Parent Add PMIC Wrap support for MT8365 SoC. Signed-off-by: Fabien Parent Signed-off-by: Fadwa CHIBY Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-pmic-wrap.c | 78 ++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index d56b00023ccd..15789a03e6c6 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -983,6 +983,68 @@ static int mt8195_regs[] =3D { [PWRAP_WACS2_RDATA] =3D 0x8A8, }; =20 +static int mt8365_regs[] =3D { + [PWRAP_MUX_SEL] =3D 0x0, + [PWRAP_WRAP_EN] =3D 0x4, + [PWRAP_DIO_EN] =3D 0x8, + [PWRAP_CSHEXT_WRITE] =3D 0x24, + [PWRAP_CSHEXT_READ] =3D 0x28, + [PWRAP_STAUPD_PRD] =3D 0x3c, + [PWRAP_STAUPD_GRPEN] =3D 0x40, + [PWRAP_STAUPD_MAN_TRIG] =3D 0x58, + [PWRAP_STAUPD_STA] =3D 0x5c, + [PWRAP_WRAP_STA] =3D 0x60, + [PWRAP_HARB_INIT] =3D 0x64, + [PWRAP_HARB_HPRIO] =3D 0x68, + [PWRAP_HIPRIO_ARB_EN] =3D 0x6c, + [PWRAP_HARB_STA0] =3D 0x70, + [PWRAP_HARB_STA1] =3D 0x74, + [PWRAP_MAN_EN] =3D 0x7c, + [PWRAP_MAN_CMD] =3D 0x80, + [PWRAP_MAN_RDATA] =3D 0x84, + [PWRAP_MAN_VLDCLR] =3D 0x88, + [PWRAP_WACS0_EN] =3D 0x8c, + [PWRAP_INIT_DONE0] =3D 0x90, + [PWRAP_WACS0_CMD] =3D 0xc00, + [PWRAP_WACS0_RDATA] =3D 0xc04, + [PWRAP_WACS0_VLDCLR] =3D 0xc08, + [PWRAP_WACS1_EN] =3D 0x94, + [PWRAP_INIT_DONE1] =3D 0x98, + [PWRAP_WACS2_EN] =3D 0x9c, + [PWRAP_INIT_DONE2] =3D 0xa0, + [PWRAP_WACS2_CMD] =3D 0xc20, + [PWRAP_WACS2_RDATA] =3D 0xc24, + [PWRAP_WACS2_VLDCLR] =3D 0xc28, + [PWRAP_INT_EN] =3D 0xb4, + [PWRAP_INT_FLG_RAW] =3D 0xb8, + [PWRAP_INT_FLG] =3D 0xbc, + [PWRAP_INT_CLR] =3D 0xc0, + [PWRAP_SIG_ADR] =3D 0xd4, + [PWRAP_SIG_MODE] =3D 0xd8, + [PWRAP_SIG_VALUE] =3D 0xdc, + [PWRAP_SIG_ERRVAL] =3D 0xe0, + [PWRAP_CRC_EN] =3D 0xe4, + [PWRAP_TIMER_EN] =3D 0xe8, + [PWRAP_TIMER_STA] =3D 0xec, + [PWRAP_WDT_UNIT] =3D 0xf0, + [PWRAP_WDT_SRC_EN] =3D 0xf4, + [PWRAP_WDT_FLG] =3D 0xfc, + [PWRAP_DEBUG_INT_SEL] =3D 0x104, + [PWRAP_CIPHER_KEY_SEL] =3D 0x1c4, + [PWRAP_CIPHER_IV_SEL] =3D 0x1c8, + [PWRAP_CIPHER_RDY] =3D 0x1d0, + [PWRAP_CIPHER_MODE] =3D 0x1d4, + [PWRAP_CIPHER_SWRST] =3D 0x1d8, + [PWRAP_DCM_EN] =3D 0x1dc, + [PWRAP_DCM_DBC_PRD] =3D 0x1e0, + [PWRAP_EINT_STA0_ADR] =3D 0x44, + [PWRAP_EINT_STA1_ADR] =3D 0x48, + [PWRAP_INT1_EN] =3D 0xc4, + [PWRAP_INT1_FLG] =3D 0xcc, + [PWRAP_INT1_CLR] =3D 0xd0, + [PWRAP_WDT_SRC_EN_1] =3D 0xf8, +}; + static int mt8516_regs[] =3D { [PWRAP_MUX_SEL] =3D 0x0, [PWRAP_WRAP_EN] =3D 0x4, @@ -1139,6 +1201,7 @@ enum pwrap_type { PWRAP_MT8183, PWRAP_MT8186, PWRAP_MT8195, + PWRAP_MT8365, PWRAP_MT8516, }; =20 @@ -1598,6 +1661,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) case PWRAP_MT6797: case PWRAP_MT8173: case PWRAP_MT8186: + case PWRAP_MT8365: case PWRAP_MT8516: pwrap_writel(wrp, 1, PWRAP_CIPHER_EN); break; @@ -2106,6 +2170,19 @@ static struct pmic_wrapper_type pwrap_mt8195 =3D { .init_soc_specific =3D NULL, }; =20 +static const struct pmic_wrapper_type pwrap_mt8365 =3D { + .regs =3D mt8365_regs, + .type =3D PWRAP_MT8365, + .arb_en_all =3D 0x3ffff, + .int_en_all =3D 0x7f1fffff, + .int1_en_all =3D 0x0, + .spi_w =3D PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src =3D PWRAP_WDT_SRC_MASK_ALL, + .caps =3D PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1, + .init_reg_clock =3D pwrap_common_init_reg_clock, + .init_soc_specific =3D NULL, +}; + static struct pmic_wrapper_type pwrap_mt8516 =3D { .regs =3D mt8516_regs, .type =3D PWRAP_MT8516, @@ -2143,6 +2220,7 @@ static const struct of_device_id of_pwrap_match_tbl[]= =3D { { .compatible =3D "mediatek,mt8183-pwrap", .data =3D &pwrap_mt8183 }, { .compatible =3D "mediatek,mt8186-pwrap", .data =3D &pwrap_mt8186 }, { .compatible =3D "mediatek,mt8195-pwrap", .data =3D &pwrap_mt8195 }, + { .compatible =3D "mediatek,mt8365-pwrap", .data =3D &pwrap_mt8365 }, { .compatible =3D "mediatek,mt8516-pwrap", .data =3D &pwrap_mt8516 }, { /* sentinel */ } }; --=20 2.25.1