From nobody Fri Dec 19 18:53:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3749FA373E for ; Mon, 24 Oct 2022 13:35:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232524AbiJXNdW (ORCPT ); Mon, 24 Oct 2022 09:33:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236079AbiJXN3e (ORCPT ); Mon, 24 Oct 2022 09:29:34 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBACCABF25; Mon, 24 Oct 2022 05:32:42 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A196E612DB; Mon, 24 Oct 2022 12:32:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B4812C433D6; Mon, 24 Oct 2022 12:32:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1666614762; bh=4yEgmnwTZHctMTUP9k2Sgbjd3eyxLywPyXolyPXXje0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=09OYMQTpnOEcjF+WXQBYzzeh4Ip1xTDVK4q3fODg4uYDsl/Sr3P+gOR/1RyDPfkbm NDjCwrmR+PGFplfkrHE1epakbLI0P5rfcI0mSWoslZnKMpBiV12wBN2EX7TgMy714o EV6yLLU9eGKiZWHaix51gyWIPK8lBWBq56CWLaac= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Quanyang Wang , Shubhrajyoti Datta , Stephen Boyd , Sasha Levin Subject: [PATCH 5.10 354/390] clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate Date: Mon, 24 Oct 2022 13:32:31 +0200 Message-Id: <20221024113038.073824230@linuxfoundation.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221024113022.510008560@linuxfoundation.org> References: <20221024113022.510008560@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Quanyang Wang [ Upstream commit 30eaf02149ecc3c5815e45d27187bf09e925071d ] The function zynqmp_pll_round_rate is used to find a most appropriate PLL frequency which the hardware can generate according to the desired frequency. For example, if the desired frequency is 297MHz, considering the limited range from PS_PLL_VCO_MIN (1.5GHz) to PS_PLL_VCO_MAX (3.0GHz) of PLL, zynqmp_pll_round_rate should return 1.872GHz (297MHz * 5). There are two problems with the current code of zynqmp_pll_round_rate: 1) When the rate is below PS_PLL_VCO_MIN, it can't find a correct rate when the parameter "rate" is an integer multiple of *prate, in other words, if "f" is zero, zynqmp_pll_round_rate won't return a valid frequency which is from PS_PLL_VCO_MIN to PS_PLL_VCO_MAX. For example, *prate is 33MHz and the rate is 660MHz, zynqmp_pll_round_rate will not boost up rate and just return 660MHz, and this will cause clk_calc_new_rates failure since zynqmp_pll_round_rate returns an invalid rate out of its boundaries. 2) Even if the rate is higher than PS_PLL_VCO_MIN, there is still a risk that zynqmp_pll_round_rate returns an invalid rate because the function DIV_ROUND_CLOSEST makes some loss in the fractional part. If the parent clock *prate is 33333333Hz and we want to set the PLL rate to 1.5GHz, this function will return 1499999985Hz by using the formula below: value =3D *prate * DIV_ROUND_CLOSEST(rate, *prate)). This value is also invalid since it's slightly smaller than PS_PLL_VCO_MIN. because DIV_ROUND_CLOSEST makes some loss in the fractional part. Signed-off-by: Quanyang Wang Link: https://lore.kernel.org/r/20220826142030.213805-1-quanyang.wang@windr= iver.com Reviewed-by: Shubhrajyoti Datta Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/zynqmp/pll.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c index abe6afbf3407..2ae7f9129b07 100644 --- a/drivers/clk/zynqmp/pll.c +++ b/drivers/clk/zynqmp/pll.c @@ -99,26 +99,25 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, un= signed long rate, unsigned long *prate) { u32 fbdiv; - long rate_div, f; + u32 mult, div; =20 - /* Enable the fractional mode if needed */ - rate_div =3D (rate * FRAC_DIV) / *prate; - f =3D rate_div % FRAC_DIV; - if (f) { - if (rate > PS_PLL_VCO_MAX) { - fbdiv =3D rate / PS_PLL_VCO_MAX; - rate =3D rate / (fbdiv + 1); - } - if (rate < PS_PLL_VCO_MIN) { - fbdiv =3D DIV_ROUND_UP(PS_PLL_VCO_MIN, rate); - rate =3D rate * fbdiv; - } - return rate; + /* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */ + if (rate > PS_PLL_VCO_MAX) { + div =3D DIV_ROUND_UP(rate, PS_PLL_VCO_MAX); + rate =3D rate / div; + } + if (rate < PS_PLL_VCO_MIN) { + mult =3D DIV_ROUND_UP(PS_PLL_VCO_MIN, rate); + rate =3D rate * mult; } =20 fbdiv =3D DIV_ROUND_CLOSEST(rate, *prate); - fbdiv =3D clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); - return *prate * fbdiv; + if (fbdiv < PLL_FBDIV_MIN || fbdiv > PLL_FBDIV_MAX) { + fbdiv =3D clamp_t(u32, fbdiv, PLL_FBDIV_MIN, PLL_FBDIV_MAX); + rate =3D *prate * fbdiv; + } + + return rate; } =20 /** --=20 2.35.1