From nobody Wed Sep 3 06:41:48 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FA11FA373E for ; Mon, 24 Oct 2022 12:24:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233481AbiJXMYw (ORCPT ); Mon, 24 Oct 2022 08:24:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233559AbiJXMXL (ORCPT ); Mon, 24 Oct 2022 08:23:11 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F42D1C119; Mon, 24 Oct 2022 04:59:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 58C0F61252; Mon, 24 Oct 2022 11:59:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6AE14C433C1; Mon, 24 Oct 2022 11:59:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1666612769; bh=cHT/tctzQJbGiXiQn4s+uUUWvv1Z72ev5clpduBCXxw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GPMJrVkwjJB/Tto61ezoEEuMcyRorrGSKq3t+SmwdENP6pjN/nLfLNVC4Am22kg5/ 4y7RKc83HWpn8qyqVivu7J76UgCdFwBkwNBumj3r/iygAr26z0xroODp3kQ/HkotAS 1BhDqcMclNt46zX6U+f7YPw6vkpSb5NGmahTnXFA= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= , Gregory CLEMENT , Sasha Levin Subject: [PATCH 4.19 111/229] ARM: dts: turris-omnia: Fix mpp26 pin name and comment Date: Mon, 24 Oct 2022 13:30:30 +0200 Message-Id: <20221024113002.595984668@linuxfoundation.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221024112959.085534368@linuxfoundation.org> References: <20221024112959.085534368@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marek Beh=C3=BAn [ Upstream commit 49e93898f0dc177e645c22d0664813567fd9ec00 ] There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin, which is routed to CN11 pin header, is documented as SPI CS1, but MPP[26] pin does not support this function. Instead it controls chip select 2 if in "spi0" mode. Fix the name of the pin node in pinctrl node and fix the comment in SPI node. Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Signed-off-by: Marek Beh=C3=BAn Signed-off-by: Gregory CLEMENT Signed-off-by: Sasha Levin --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/= dts/armada-385-turris-omnia.dts index fde4c302f08e..92e08486ec81 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -307,7 +307,7 @@ marvell,function =3D "spi0"; }; =20 - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins =3D "mpp26"; marvell,function =3D "spi0"; }; @@ -342,7 +342,7 @@ }; }; =20 - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; =20 &uart0 { --=20 2.35.1