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Mon, 24 Oct 2022 01:25:28 -0700 From: Raju Lakkaraju To: CC: , , , , , , , , , , Subject: [PATCH net-next V1 2/2] net: phy: micrel: Add PHY Auto/MDI/MDI-X set driver for KSZ9131 Date: Mon, 24 Oct 2022 13:55:16 +0530 Message-ID: <20221024082516.661199-3-Raju.Lakkaraju@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221024082516.661199-1-Raju.Lakkaraju@microchip.com> References: <20221024082516.661199-1-Raju.Lakkaraju@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for MDI-X status and configuration for KSZ9131 chips Signed-off-by: Raju Lakkaraju Reviewed-by: Andrew Lunn Reviewed-by: Horatiu Vultur --- Change List: =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V0 -> V1: - Drop the "_" from the end of the macros - Add KSZ9131 MDI-X specific register contain 9131 in macro names=20 drivers/net/phy/micrel.c | 77 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 54a17b576eac..26ce0c5defcd 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -1295,6 +1295,81 @@ static int ksz9131_config_init(struct phy_device *ph= ydev) return 0; } =20 +#define MII_KSZ9131_AUTO_MDIX 0x1C +#define MII_KSZ9131_AUTO_MDI_SET BIT(7) +#define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6) + +static int ksz9131_mdix_update(struct phy_device *phydev) +{ + int ret; + + ret =3D phy_read(phydev, MII_KSZ9131_AUTO_MDIX); + if (ret < 0) + return ret; + + if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) { + if (ret & MII_KSZ9131_AUTO_MDI_SET) + phydev->mdix_ctrl =3D ETH_TP_MDI; + else + phydev->mdix_ctrl =3D ETH_TP_MDI_X; + } else { + phydev->mdix_ctrl =3D ETH_TP_MDI_AUTO; + } + + if (ret & MII_KSZ9131_AUTO_MDI_SET) + phydev->mdix =3D ETH_TP_MDI; + else + phydev->mdix =3D ETH_TP_MDI_X; + + return 0; +} + +static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl) +{ + u16 val; + + switch (ctrl) { + case ETH_TP_MDI: + val =3D MII_KSZ9131_AUTO_MDIX_SWAP_OFF | + MII_KSZ9131_AUTO_MDI_SET; + break; + case ETH_TP_MDI_X: + val =3D MII_KSZ9131_AUTO_MDIX_SWAP_OFF; + break; + case ETH_TP_MDI_AUTO: + val =3D 0; + break; + default: + return 0; + } + + return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX, + MII_KSZ9131_AUTO_MDIX_SWAP_OFF | + MII_KSZ9131_AUTO_MDI_SET, val); +} + +static int ksz9131_read_status(struct phy_device *phydev) +{ + int ret; + + ret =3D ksz9131_mdix_update(phydev); + if (ret < 0) + return ret; + + return genphy_read_status(phydev); +} + +static int ksz9131_config_aneg(struct phy_device *phydev) +{ + int ret; + + ret =3D ksz9131_config_mdix(phydev, phydev->mdix_ctrl); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) @@ -3304,6 +3379,8 @@ static struct phy_driver ksphy_driver[] =3D { .probe =3D kszphy_probe, .config_init =3D ksz9131_config_init, .config_intr =3D kszphy_config_intr, + .config_aneg =3D ksz9131_config_aneg, + .read_status =3D ksz9131_read_status, .handle_interrupt =3D kszphy_handle_interrupt, .get_sset_count =3D kszphy_get_sset_count, .get_strings =3D kszphy_get_strings, --=20 2.25.1