From nobody Fri Dec 19 18:43:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2306C04A95 for ; Sat, 22 Oct 2022 08:18:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233591AbiJVISq (ORCPT ); Sat, 22 Oct 2022 04:18:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234083AbiJVIQJ (ORCPT ); Sat, 22 Oct 2022 04:16:09 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 885C486F9D; Sat, 22 Oct 2022 00:57:03 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 8CDFA60B45; Sat, 22 Oct 2022 07:56:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 92BAFC433C1; Sat, 22 Oct 2022 07:56:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1666425414; bh=ugBjsepRYvYP6ewZJtg3S2+9ioUPke2+iMbvqyO+qVE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gif+MmWnRT7y9o2TolKo727PcTka27O5Ar/J7LFyjYtahEZ7BD0/AdW+xPqDfAUjD 6LXK5J4eZWMUcRqpYHHLo8qV0wS81noSxsPaVDKibW4s6TLt6Fin7+dsFY6GjJe47f /xWcUj8VMGv6OV1Cdg8LqGcfTsrZQYp8S86oc4RE= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Adam Skladowski , Iskren Chernev , Bjorn Andersson , Sasha Levin Subject: [PATCH 5.19 463/717] clk: qcom: gcc-sm6115: Override default Alpha PLL regs Date: Sat, 22 Oct 2022 09:25:42 +0200 Message-Id: <20221022072518.779391675@linuxfoundation.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221022072415.034382448@linuxfoundation.org> References: <20221022072415.034382448@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Adam Skladowski [ Upstream commit 068a0605ef5a6b430e7278c169bfcd25b680b28f ] The DEFAULT and BRAMMO PLL offsets are non-standard in downstream, but currently only BRAMMO ones are overridden. Override DEFAULT ones too. A very similar thing is happening in gcc-qcm2290 driver. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver f= or SM6115") Signed-off-by: Adam Skladowski Signed-off-by: Iskren Chernev Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220830075620.974009-2-iskren.chernev@gmai= l.com Signed-off-by: Sasha Levin --- drivers/clk/qcom/gcc-sm6115.c | 46 +++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 68fe9f6f0d2f..e24a977c2580 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -53,11 +53,25 @@ static struct pll_vco gpll10_vco[] =3D { { 750000000, 1500000000, 1 }, }; =20 +static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] =3D { + [CLK_ALPHA_PLL_TYPE_DEFAULT] =3D { + [PLL_OFF_L_VAL] =3D 0x04, + [PLL_OFF_ALPHA_VAL] =3D 0x08, + [PLL_OFF_ALPHA_VAL_U] =3D 0x0c, + [PLL_OFF_TEST_CTL] =3D 0x10, + [PLL_OFF_TEST_CTL_U] =3D 0x14, + [PLL_OFF_USER_CTL] =3D 0x18, + [PLL_OFF_USER_CTL_U] =3D 0x1c, + [PLL_OFF_CONFIG_CTL] =3D 0x20, + [PLL_OFF_STATUS] =3D 0x24, + }, +}; + static struct clk_alpha_pll gpll0 =3D { .offset =3D 0x0, .vco_table =3D default_vco, .num_vco =3D ARRAY_SIZE(default_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr =3D { .enable_reg =3D 0x79000, .enable_mask =3D BIT(0), @@ -83,7 +97,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_aux2 =3D { .post_div_table =3D post_div_table_gpll0_out_aux2, .num_post_div =3D ARRAY_SIZE(post_div_table_gpll0_out_aux2), .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "gpll0_out_aux2", .parent_hws =3D (const struct clk_hw *[]){ &gpll0.clkr.hw }, @@ -115,7 +129,7 @@ static struct clk_alpha_pll_postdiv gpll0_out_main =3D { .post_div_table =3D post_div_table_gpll0_out_main, .num_post_div =3D ARRAY_SIZE(post_div_table_gpll0_out_main), .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "gpll0_out_main", .parent_hws =3D (const struct clk_hw *[]){ &gpll0.clkr.hw }, @@ -137,7 +151,7 @@ static struct clk_alpha_pll gpll10 =3D { .offset =3D 0xa000, .vco_table =3D gpll10_vco, .num_vco =3D ARRAY_SIZE(gpll10_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr =3D { .enable_reg =3D 0x79000, .enable_mask =3D BIT(10), @@ -163,7 +177,7 @@ static struct clk_alpha_pll_postdiv gpll10_out_main =3D= { .post_div_table =3D post_div_table_gpll10_out_main, .num_post_div =3D ARRAY_SIZE(post_div_table_gpll10_out_main), .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "gpll10_out_main", .parent_hws =3D (const struct clk_hw *[]){ &gpll10.clkr.hw }, @@ -189,7 +203,7 @@ static struct clk_alpha_pll gpll11 =3D { .vco_table =3D default_vco, .num_vco =3D ARRAY_SIZE(default_vco), .flags =3D SUPPORTS_DYNAMIC_UPDATE, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr =3D { .enable_reg =3D 0x79000, .enable_mask =3D BIT(11), @@ -215,7 +229,7 @@ static struct clk_alpha_pll_postdiv gpll11_out_main =3D= { .post_div_table =3D post_div_table_gpll11_out_main, .num_post_div =3D ARRAY_SIZE(post_div_table_gpll11_out_main), .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "gpll11_out_main", .parent_hws =3D (const struct clk_hw *[]){ &gpll11.clkr.hw }, @@ -229,7 +243,7 @@ static struct clk_alpha_pll gpll3 =3D { .offset =3D 0x3000, .vco_table =3D default_vco, .num_vco =3D ARRAY_SIZE(default_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr =3D { .enable_reg =3D 0x79000, .enable_mask =3D BIT(3), @@ -248,7 +262,7 @@ static struct clk_alpha_pll gpll4 =3D { .offset =3D 0x4000, .vco_table =3D default_vco, .num_vco =3D ARRAY_SIZE(default_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr =3D { .enable_reg =3D 0x79000, .enable_mask =3D BIT(4), @@ -274,7 +288,7 @@ static struct clk_alpha_pll_postdiv gpll4_out_main =3D { .post_div_table =3D post_div_table_gpll4_out_main, .num_post_div =3D ARRAY_SIZE(post_div_table_gpll4_out_main), .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "gpll4_out_main", .parent_hws =3D (const struct clk_hw *[]){ &gpll4.clkr.hw }, @@ -287,7 +301,7 @@ static struct clk_alpha_pll gpll6 =3D { .offset =3D 0x6000, .vco_table =3D default_vco, .num_vco =3D ARRAY_SIZE(default_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr =3D { .enable_reg =3D 0x79000, .enable_mask =3D BIT(6), @@ -313,7 +327,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_main =3D { .post_div_table =3D post_div_table_gpll6_out_main, .num_post_div =3D ARRAY_SIZE(post_div_table_gpll6_out_main), .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "gpll6_out_main", .parent_hws =3D (const struct clk_hw *[]){ &gpll6.clkr.hw }, @@ -326,7 +340,7 @@ static struct clk_alpha_pll gpll7 =3D { .offset =3D 0x7000, .vco_table =3D default_vco, .num_vco =3D ARRAY_SIZE(default_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr =3D { .enable_reg =3D 0x79000, .enable_mask =3D BIT(7), @@ -352,7 +366,7 @@ static struct clk_alpha_pll_postdiv gpll7_out_main =3D { .post_div_table =3D post_div_table_gpll7_out_main, .num_post_div =3D ARRAY_SIZE(post_div_table_gpll7_out_main), .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "gpll7_out_main", .parent_hws =3D (const struct clk_hw *[]){ &gpll7.clkr.hw }, @@ -380,7 +394,7 @@ static struct clk_alpha_pll gpll8 =3D { .offset =3D 0x8000, .vco_table =3D default_vco, .num_vco =3D ARRAY_SIZE(default_vco), - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .flags =3D SUPPORTS_DYNAMIC_UPDATE, .clkr =3D { .enable_reg =3D 0x79000, @@ -407,7 +421,7 @@ static struct clk_alpha_pll_postdiv gpll8_out_main =3D { .post_div_table =3D post_div_table_gpll8_out_main, .num_post_div =3D ARRAY_SIZE(post_div_table_gpll8_out_main), .width =3D 4, - .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .regs =3D clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_DEFAULT], .clkr.hw.init =3D &(struct clk_init_data){ .name =3D "gpll8_out_main", .parent_hws =3D (const struct clk_hw *[]){ &gpll8.clkr.hw }, --=20 2.35.1