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[90.24.137.155]) by smtp.gmail.com with ESMTPSA id k5-20020a05600c0b4500b003c41144b3cfsm2040233wmr.20.2022.10.21.01.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 01:47:56 -0700 (PDT) From: bchihi@baylibre.com To: sean.wang@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com Cc: linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [v2, 1/2] pinctrl: mediatek: common: add mt8365_set_clr_mode() callback for broken SET/CLR modes Date: Fri, 21 Oct 2022 10:47:07 +0200 Message-Id: <20221021084708.1109986-2-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021084708.1109986-1-bchihi@baylibre.com> References: <20221021084708.1109986-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Add mt8365_set_clr_mode() callback for such SoCs, so that instead of using the SET/CLR register, use the main R/W register to read/update/write the modes. Co-developed-by: Fabien Parent Signed-off-by: Fabien Parent Signed-off-by: Balsam CHIHI --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 15 +++++++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 8 +++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctr= l/mediatek/pinctrl-mtk-common.c index f25b3e09386b..076ae0b38e3d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -330,6 +330,21 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctr= l *pctl, return -EINVAL; } =20 + if (pctl->devdata->mt8365_set_clr_mode) { + bit =3D pin & pctl->devdata->mode_mask; + reg_pullen =3D mtk_get_port(pctl, pin) + + pctl->devdata->pullen_offset; + reg_pullsel =3D mtk_get_port(pctl, pin) + + pctl->devdata->pullsel_offset; + ret =3D pctl->devdata->mt8365_set_clr_mode(mtk_get_regmap(pctl, pin), + bit, reg_pullen, reg_pullsel, + enable, isup); + if (ret) + return -EINVAL; + + return 0; + } + bit =3D BIT(pin & pctl->devdata->mode_mask); if (enable) reg_pullen =3D SET_ADDR(mtk_get_port(pctl, pin) + diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctr= l/mediatek/pinctrl-mtk-common.h index 6fe8564334c9..11afa12a96cb 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -216,7 +216,10 @@ struct mtk_eint_offsets { * @spec_dir_set: In very few SoCs, direction control registers are not * arranged continuously, they may be cut to parts. So they need special * dir setting. - + * @mt8365_set_clr_mode: In mt8365, some pins won't set correcty because t= hey + * need to use the main R/W register to read/update/write the modes instea= d of + * the SET/CLR register. + * * @dir_offset: The direction register offset. * @pullen_offset: The pull-up/pull-down enable register offset. * @pinmux_offset: The pinmux register offset. @@ -252,6 +255,9 @@ struct mtk_pinctrl_devdata { void (*spec_pinmux_set)(struct regmap *reg, unsigned int pin, unsigned int mode); void (*spec_dir_set)(unsigned int *reg_addr, unsigned int pin); + int (*mt8365_set_clr_mode)(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup); unsigned int dir_offset; unsigned int ies_offset; unsigned int smt_offset; --=20 2.34.1 From nobody Sat Sep 21 12:40:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0F4DC433FE for ; Fri, 21 Oct 2022 08:48:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230347AbiJUIsV (ORCPT ); Fri, 21 Oct 2022 04:48:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230250AbiJUIsG (ORCPT ); Fri, 21 Oct 2022 04:48:06 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F15EF11CB59 for ; Fri, 21 Oct 2022 01:47:59 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id w18so3738771wro.7 for ; Fri, 21 Oct 2022 01:47:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IbWZD88Csa/gnzCp+HMy/jlXVSOibosOwLIHUydjLSM=; b=SsKIYrb7OvBJOeb8oL4usYLyXghenrQID5yZvH3pX0XKPhJN1CG7V6x/U0nKj8osd7 d808EvZBNDx/cY56qI+NXMpb+DZzaLrmrtRmbQ7SpR8d54YEQ5RgTmE4ra4VDJib2jam vwiVe8T34UXKId38I0e2iHZddayU5VEz8LCYizNDMlp6tnl/0+bNIdU7H0z0I6BUpV+B /ucURVgVWqJQXc+l9wJO1fW/vtVg3qM4neP415ndQIgao5xb30HpKN4zkISS9cUNDHFK cCOliYL9hfvCH0QOuEltYQVMAU4liP5W10nmN5U/k1E2c37GVmxup5pG0eXlYky1YvTU Yaqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IbWZD88Csa/gnzCp+HMy/jlXVSOibosOwLIHUydjLSM=; b=5AIPBHWfrXKS4ycNjP2kknyoljwAET+zgzeIWDPHmCShB+lwe8coO8M116IBadhPQB ScL24IPFheSjmaHwMskbvQnWA6jTRb5hllsoLynjyjHT6l2sSyKvgBukhdSDkulJrSyj 0nlgWbunmhGlWxBIZyFN/9iWHXOywV+su2zsLuaFTLldQsWMyej9r7svAHCmABHJtQ3F nCla7TyMlBoMGR6Mdvr4ZpAbEFGTuNkfxvRuprWl5DO84GXuuaNUnxlg4AVaq6+cHlcU XAwcOgNm0F7zVO46r3MHtDxxp1/rze05N0TQubnqyxIg+mXUZcpfa5wU2NFdZLQBGLpV pLCg== X-Gm-Message-State: ACrzQf1FRIVkTR7Jz0j7MxE+bLXGJK0jZ+tecNmyfykPnkFR2K9++WiT sqq6itg4rniTkATK/GqXspVsaw== X-Google-Smtp-Source: AMsMyM7uFs9IFzNVInzdSUYlLwCAHeX5bF4kkYp9ut4AlH8VXFPaQellUjaw5YdFzfU/trLsLMNTig== X-Received: by 2002:a5d:4cc2:0:b0:22e:372d:9c9 with SMTP id c2-20020a5d4cc2000000b0022e372d09c9mr11435346wrt.576.1666342077651; Fri, 21 Oct 2022 01:47:57 -0700 (PDT) Received: from localhost.localdomain (laubervilliers-657-1-248-155.w90-24.abo.wanadoo.fr. [90.24.137.155]) by smtp.gmail.com with ESMTPSA id k5-20020a05600c0b4500b003c41144b3cfsm2040233wmr.20.2022.10.21.01.47.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Oct 2022 01:47:57 -0700 (PDT) From: bchihi@baylibre.com To: sean.wang@kernel.org, linus.walleij@linaro.org, matthias.bgg@gmail.com Cc: linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [v2, 2/2] pinctrl: mediatek: mt8365: use mt8365_set_clr_mode() callback Date: Fri, 21 Oct 2022 10:47:08 +0200 Message-Id: <20221021084708.1109986-3-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021084708.1109986-1-bchihi@baylibre.com> References: <20221021084708.1109986-1-bchihi@baylibre.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Balsam CHIHI On MT8365, the SET/CLR of the mode is broken and some pin modes won't be set correctly. Use the mt8365_set_clr_mode() callback to fix the issue. Co-developed-by: Fabien Parent Signed-off-by: Fabien Parent Signed-off-by: Balsam CHIHI --- drivers/pinctrl/mediatek/pinctrl-mt8365.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/me= diatek/pinctrl-mt8365.c index 57f37a294063..42b48136ab77 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8365.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -416,6 +416,23 @@ static const struct mtk_pin_ies_smt_set mt8365_smt_set= [] =3D { MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), }; =20 +static int mt8365_set_clr_mode(struct regmap *regmap, + unsigned int bit, unsigned int reg_pullen, unsigned int reg_pullsel, + bool enable, bool isup) +{ + int ret; + + ret =3D regmap_update_bits(regmap, reg_pullen, BIT(bit), enable << bit); + if (ret) + return -EINVAL; + + ret =3D regmap_update_bits(regmap, reg_pullsel, BIT(bit), isup << bit); + if (ret) + return -EINVAL; + + return 0; +} + static const struct mtk_pinctrl_devdata mt8365_pinctrl_data =3D { .pins =3D mtk_pins_mt8365, .npins =3D ARRAY_SIZE(mtk_pins_mt8365), @@ -431,6 +448,7 @@ static const struct mtk_pinctrl_devdata mt8365_pinctrl_= data =3D { .n_spec_pupd =3D ARRAY_SIZE(mt8365_spec_pupd), .spec_pull_set =3D mtk_pctrl_spec_pull_set_samereg, .spec_ies_smt_set =3D mtk_pconf_spec_set_ies_smt_range, + .mt8365_set_clr_mode =3D mt8365_set_clr_mode, .dir_offset =3D 0x0140, .dout_offset =3D 0x00A0, .din_offset =3D 0x0000, --=20 2.34.1