From nobody Wed Apr 8 00:00:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEB05C43217 for ; Thu, 20 Oct 2022 15:16:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230027AbiJTPQ0 (ORCPT ); Thu, 20 Oct 2022 11:16:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229850AbiJTPQS (ORCPT ); Thu, 20 Oct 2022 11:16:18 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5514E138BAA for ; Thu, 20 Oct 2022 08:16:16 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id v1so5797852wrt.11 for ; Thu, 20 Oct 2022 08:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sQtmC5CT1BYx1wr4cDsdhyqbJnf1PNOi9nZ8obHDjYY=; b=VTFyI5VGtitN13E0qI7ebcaThIJga5Br0H4ijGb0xvRwlE43XkXzmyOFzR6AeRDpr5 tgsjsHN0yanBjF+ekH+AuvtBxMJiNt5lIqdBNmHf1jVRQhz0xwsf7dkB6/FkTKbpJkO1 ZIh5x3HGaitiP7NdmOfx1bd/xZR3NAn1zEEGjFFHU8YxTWOQFdLJmsmdhGyDgJY8ldpr 6faAhg5m4VYdSMRWgc82RtgQw49wsBzkuPy6o6H5Gh8IawzXqtMUhbthPyie97NbM7qF WU9sLEu3GJQo6c9KNrc7tHwy1fo7kkP2YBmoP3H/6/5rYKwob/ImkOElN39qdz6PWDaT xyNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sQtmC5CT1BYx1wr4cDsdhyqbJnf1PNOi9nZ8obHDjYY=; b=KLeP7WbSPugfBqx++q0YYHfPYNzEW0DftIQPS0Ww/8GVRyTjhtFKwE2+oM0TIrPK0v ykH6UmCNrHm2fctr4NaZF4GCMdAhsPRgGV8ivX/3EfgRTf+7N/lx61b6vQpcXPzRrXZ0 ILz0fzWJNJUBrfTRwAA4rUtW4jTSHbS9xaLa7yqmJfzzxW/QkZ5dtq6v4YOLw6I/7R4K Wk+4NBQRIqJODqUIDTFCRwN2cGwf0VeVU8Qc4DbOPTgB/pAvNzD56FPwCJHE9QRaQGuv eMyS3MDCUpiVbdG4oVxbDPtJ5SIlF3Q7Cyq3vRBRrBTNY7YKyNdapv6G5H6JetlPWTrD TaJg== X-Gm-Message-State: ACrzQf17Jm8iWCp/JcHXNsVmCHSrJphflpkTT+h7aXI7b1ox7N5b2Y+C 4ePPEKCwNACGhV9Sw6lZK5o4fA== X-Google-Smtp-Source: AMsMyM4b4mug2ufxEEqjlM/508NrROih3W/qYIT3N70EY7VYNDFhgOZHjQnriqgWLqeJoDcQvR60cA== X-Received: by 2002:adf:f00b:0:b0:22e:3439:cff2 with SMTP id j11-20020adff00b000000b0022e3439cff2mr9443422wro.719.1666278974810; Thu, 20 Oct 2022 08:16:14 -0700 (PDT) Received: from rainbowdash.guest.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id bg6-20020a05600c3c8600b003c6f3e5ba42sm41362wmb.46.2022.10.20.08.16.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 08:16:13 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 01/10] dt-bindings: pwm: Document Synopsys DesignWare snps,pwm-dw-apb-timers-pwm2 Date: Thu, 20 Oct 2022 16:16:01 +0100 Message-Id: <20221020151610.59443-2-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation for the bindings for Synopsys' DesignWare PWM block as we will be adding DT/platform support to the Linux driver soon. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-K=C3=B6nig Reviewed-by: Krzysztof Kozlowski Tested-by: Jarkko Nikula --- v5: - fixed order of properties - corrected clock to two items v4: - fixed typos, added reg v3: - add description and example - merge the snps,pwm-number into this patch - rename snps,pwm to snps,dw-apb-timers-pwm2 v2: - fix #pwm-cells to be 3 - fix indentation and ordering issues --- .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/snps,dw-apb-timer= s-pwm2.yaml diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.= yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml new file mode 100644 index 000000000000..9aabdb373afa --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DW-APB timers PWM controller + +maintainers: + - Ben Dooks + +description: + This describes the DesignWare APB timers module when used in the PWM + mode. The IP core can be generated with various options which can + control the functionality, the number of PWMs available and other + internal controls the designer requires. + + The IP block has a version register so this can be used for detection + instead of having to encode the IP version number in the device tree + comaptible. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: snps,dw-apb-timers-pwm2 + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Interface bus clock + - description: PWM reference clock + + clock-names: + items: + - const: bus + - const: timer + + snps,pwm-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [1, 2, 3, 4, 5, 6, 7, 8] + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + pwm: pwm@180000 { + compatible =3D "snps,dw-apb-timers-pwm2"; + reg =3D <0x180000 0x200>; + #pwm-cells =3D <3>; + clocks =3D <&bus>, <&timer>; + clock-names =3D "bus", "timer"; + }; --=20 2.35.1 From nobody Wed Apr 8 00:00:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 019C9C4321E for ; Thu, 20 Oct 2022 15:16:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229850AbiJTPQ3 (ORCPT ); Thu, 20 Oct 2022 11:16:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229986AbiJTPQT (ORCPT ); Thu, 20 Oct 2022 11:16:19 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0ED32147053 for ; Thu, 20 Oct 2022 08:16:18 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id a3so34989691wrt.0 for ; Thu, 20 Oct 2022 08:16:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=kJeYraV+chjx4w/MZhjgD8d2xGVua4ZGuZHWlb758KSGO9ChppIikvGNbRU5JuDcMT 5q4sTiPl4qmad1XKgrkucu5HEcOejc4GFcu5wgdG9SqJ+q8uPkF7hPhQAOrjX7S6SMQq tMzzBzDxpSbVvqT3yGk4CY5K6Q4lfhQx/5JB6gQsuCpzeiXERrCjLmyreJDqzO599NZw 9DzW4wTv5O3ttQZunV8Dh3TUQta4hnsv+4LwJj96Hy9dULjjR+puxvkxBClUPcltAQhV m0sjJHT4Vqaf0GUfjhy8hFaxm4Qh3/YDjo1HIlFdeEq1YLeGuCi2ZiwFsnaGDyPsHham pjYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=UFce9ih7UVOGlSr/qjUL47edfvl03ym/1Uv3Eodc2jxe3jnH4x6sQNI3bQ2TJaO1ke BOGv1s/as+vAg4pqruPa/FSjj+LbUrwzdepjWBnwgeEBNbuourRVGlFJINWYl8OzuEEx XzBNCWulASvgJdF8TJcD93wBVvKp52LIdIgMT1Xv0fsoSTbcQdumhpgSa0mLpwFCEwlB T7ltNk/LmFO0ynZDjjAloOXicxDBPaSZ57gCu+LRLxZa9Ag1QOObG73wI9nVLuuzgoZT pixMpG2+2hA9OW2n6Krxjv4lHv6oz137dolpVYMJYudgPQdfUhjKoGe9ClaGIIydyxXn j1FA== X-Gm-Message-State: ACrzQf2C3dEKrYZyrj27hIPTnpM4c7dKm2BN5+8+QUyngVzb0U5YSWJY Yc6zWCA/aUEibFiZHJyQQ2W2Sw== X-Google-Smtp-Source: AMsMyM5qyB4bwOpUIYl9vi1zgJNgu2I+7YGLZ5w0AMEMM42WxAUOza4QELi8lmWd2SJCPtFdIwIfmg== X-Received: by 2002:a5d:494a:0:b0:235:4b14:4c7e with SMTP id r10-20020a5d494a000000b002354b144c7emr3453423wrs.174.1666278976603; Thu, 20 Oct 2022 08:16:16 -0700 (PDT) Received: from rainbowdash.guest.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id bg6-20020a05600c3c8600b003c6f3e5ba42sm41362wmb.46.2022.10.20.08.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 08:16:15 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 02/10] pwm: dwc: allow driver to be built with COMPILE_TEST Date: Thu, 20 Oct 2022 16:16:02 +0100 Message-Id: <20221020151610.59443-3-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allow dwc driver to be built with COMPILE_TEST should allow better coverage when build testing. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-K=C3=B6nig Tested-by: Jarkko Nikula --- v4: - moved to earlier in the series v3: - add HAS_IOMEM depdency for compile testing --- drivers/pwm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..3f3c53af4a56 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -176,7 +176,8 @@ config PWM_CROS_EC =20 config PWM_DWC tristate "DesignWare PWM Controller" - depends on PCI + depends on PCI || COMPILE_TEST + depends on HAS_IOMEM help PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. =20 --=20 2.35.1 From nobody Wed Apr 8 00:00:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14E3CC43219 for ; Thu, 20 Oct 2022 15:16:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229552AbiJTPQi (ORCPT ); Thu, 20 Oct 2022 11:16:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230030AbiJTPQU (ORCPT ); Thu, 20 Oct 2022 11:16:20 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 45801136409 for ; Thu, 20 Oct 2022 08:16:19 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id f11so35064786wrm.6 for ; Thu, 20 Oct 2022 08:16:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=lTDMDCDikO894I2FgciNbIL2IAOM8w7a+kTIfkIAPMwv51/V0acIRNTjlCEZ36RRDf PrsjV5wL1wTdai5/OpGT0qbDSu7AVPrwsfBps+tv4PY6lziaO0t9PiDxLdlddWVQFfAX yEKWIO62oUZjNtUyDXWXKAbByzuUkDx4XaskF4U0qYozpx4r0glx4Qcu/NraN2nyHfCG dby0HW4oZUkeQjS/500DpVkziMRCU2uN9HFWfuwGluZiGsC/Cdd5RtNvecKSqUqYLbow t0UBemQ2wgh3cziVOGtmBUNXJDyAI14+NmHv+py383JAfYGMWFNqJxLqrTNuw7N4Odi5 1Utw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=X39fQx6pyzD4Xw6EVWqhLRm8KtZUxDR1Qan5TpFfsz1nrYnYmniD/Ma6iC4PAPPBrv 0AtqJj8RNVza0sVBdTOmLeTgVnJdT/+/rEJu+tB6wosO/ZCiA++EwCgkrD9XjqFSCfXU NT+L+7Wij3aNjLS7g6q1HdTbsjfrLcyPF5+1NKn1fKPdE4zG8mqeHlbdzJvE4NCwtf7Z P1UEbykMeKSgQf1VPdPgBE3cp++M8nNrzZ9Y84yPRxN2PI5U7smPPVE4KwujAJAdnepQ kiJuENo/cV5W1ybDExpk53sshEtDhjORb57vpJaNmsPyZT3qgVis4mic02mSHLZWoEwW /5hw== X-Gm-Message-State: ACrzQf3Tl2RtS17JxQwVEzQZOwV4qGyXqAtGgwu+a0jEdUf0Y7zvwCZB NzH+hoaKTmaLOqKw7WsC9ytwDw== X-Google-Smtp-Source: AMsMyM5BRAOxV+stH3UEOXaLk809vn4lxaZpN1GqorG7LeUTaIxAv4QERtw4FMEAanYlhzJgrnf9LA== X-Received: by 2002:a5d:4f12:0:b0:22e:3920:a09c with SMTP id c18-20020a5d4f12000000b0022e3920a09cmr8693613wru.95.1666278977636; Thu, 20 Oct 2022 08:16:17 -0700 (PDT) Received: from rainbowdash.guest.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id bg6-20020a05600c3c8600b003c6f3e5ba42sm41362wmb.46.2022.10.20.08.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 08:16:17 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 03/10] pwm: dwc: change &pci->dev to dev in probe Date: Thu, 20 Oct 2022 16:16:03 +0100 Message-Id: <20221020151610.59443-4-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The dwc_pwm_probe() assignes dev to be &pci->dev but then uses &pci->dev throughout the function. Change these all to the be 'dev' variable to make lines shorter. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-K=C3=B6nig Tested-by: Jarkko Nikula --- drivers/pwm/pwm-dwc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 7568300bb11e..c706ef9a7ba1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -202,14 +202,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const s= truct pci_device_id *id) struct dwc_pwm *dwc; int ret; =20 - dwc =3D devm_kzalloc(&pci->dev, sizeof(*dwc), GFP_KERNEL); + dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) return -ENOMEM; =20 ret =3D pcim_enable_device(pci); if (ret) { - dev_err(&pci->dev, - "Failed to enable device (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); return ret; } =20 @@ -217,14 +216,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const s= truct pci_device_id *id) =20 ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); if (ret) { - dev_err(&pci->dev, - "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); 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Thu, 20 Oct 2022 08:16:18 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 04/10] pwm: dwc: move memory alloc to own function Date: Thu, 20 Oct 2022 16:16:04 +0100 Message-Id: <20221020151610.59443-5-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding other bus support, move the allocation of the pwm struct out of the main driver code. Signed-off-by: Ben Dooks Tested-by: Jarkko Nikula --- drivers/pwm/pwm-dwc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index c706ef9a7ba1..61f11e0a9319 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -196,13 +196,29 @@ static const struct pwm_ops dwc_pwm_ops =3D { .owner =3D THIS_MODULE, }; =20 +static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +{ + struct dwc_pwm *dwc; + + dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return NULL; + + dwc->chip.dev =3D dev; + dwc->chip.ops =3D &dwc_pwm_ops; + dwc->chip.npwm =3D DWC_TIMERS_TOTAL; + + dev_set_drvdata(dev, dwc); + return dwc; +} + static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) { struct device *dev =3D &pci->dev; struct dwc_pwm *dwc; int ret; =20 - dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + dwc =3D dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; =20 @@ -226,12 +242,6 @@ static int dwc_pwm_probe(struct pci_dev *pci, const st= ruct pci_device_id *id) return -ENOMEM; } =20 - pci_set_drvdata(pci, dwc); - - dwc->chip.dev =3D dev; - dwc->chip.ops =3D &dwc_pwm_ops; - dwc->chip.npwm =3D DWC_TIMERS_TOTAL; - ret =3D pwmchip_add(&dwc->chip); if (ret) return ret; --=20 2.35.1 From nobody Wed Apr 8 00:00:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98161C43217 for ; Thu, 20 Oct 2022 15:16:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230221AbiJTPQm (ORCPT ); Thu, 20 Oct 2022 11:16:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230081AbiJTPQX (ORCPT ); Thu, 20 Oct 2022 11:16:23 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A088B14C52D for ; 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Thu, 20 Oct 2022 08:16:19 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 05/10] pwm: dwc: use devm_pwmchip_add Date: Thu, 20 Oct 2022 16:16:05 +0100 Message-Id: <20221020151610.59443-6-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use devm_pwmchip_add() to add the pwm chip to avoid having to manually remove it (useful for the next patch which adds the platform-device support). Signed-off-by: Ben Dooks Reviewed-by: Uwe Kleine-K=C3=B6nig Tested-by: Jarkko Nikula --- drivers/pwm/pwm-dwc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 61f11e0a9319..56cde9da2c0e 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -242,7 +242,7 @@ static int dwc_pwm_probe(struct pci_dev *pci, const str= uct pci_device_id *id) return -ENOMEM; } =20 - ret =3D pwmchip_add(&dwc->chip); + ret =3D devm_pwmchip_add(dev, &dwc->chip); if (ret) return ret; =20 @@ -254,12 +254,8 @@ static int dwc_pwm_probe(struct pci_dev *pci, const st= ruct pci_device_id *id) =20 static void dwc_pwm_remove(struct pci_dev *pci) { - struct dwc_pwm *dwc =3D pci_get_drvdata(pci); - pm_runtime_forbid(&pci->dev); pm_runtime_get_noresume(&pci->dev); - - pwmchip_remove(&dwc->chip); } =20 #ifdef CONFIG_PM_SLEEP --=20 2.35.1 From nobody Wed Apr 8 00:00:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1DA1C433FE for ; Thu, 20 Oct 2022 15:16:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230307AbiJTPQ5 (ORCPT ); Thu, 20 Oct 2022 11:16:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230129AbiJTPQ2 (ORCPT ); Thu, 20 Oct 2022 11:16:28 -0400 Received: from mail-wm1-x336.google.com (mail-wm1-x336.google.com [IPv6:2a00:1450:4864:20::336]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E8D414DF2E for ; Thu, 20 Oct 2022 08:16:23 -0700 (PDT) Received: by mail-wm1-x336.google.com with SMTP id v130-20020a1cac88000000b003bcde03bd44so2596710wme.5 for ; Thu, 20 Oct 2022 08:16:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CrCSKyIIPnCSoamHugpD/e3j+U8pl8ZSDgiJjEnZ55k=; b=RbDNo5ksbkygSpWcQXS6uZnU/GOxeXWVXdduJiwHEnbxUeyqshKObty0D66/c1nDub PAah6LIiUmQFJ9bqXakX5cP4lorcHyA+NCjLYMOFHoEsnSmvOBWFFPlYGxVM9grvW+9A NYMtjG1l3DV3leVtTRJGzvr8lphUpdqLCqfO1oAaUJ/Z8YJ34ZOVSNS/38sKYprXNHqr QZVWpMoqQNX2+O4GDjubVcwjeWBg0L644r6v3mICS2BuE81hkPih6Pt5KzOYdqBj/8GB aeGO/8IRRsvtKTj3g3E9dGHtROAhPzzWKPsoGeFdc730aCkwC2Qwbmtoh3R0vtrQwhJV 8Bxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CrCSKyIIPnCSoamHugpD/e3j+U8pl8ZSDgiJjEnZ55k=; b=C/O2WXwVrTWXqTkIz2h0/qDQh6f/PW6Y19YbiL+ow6ZmUYjE9+zneCyKj+S680htKB SWA+Fjo6Ag8ivwy6tK6gXFM9rwYhRCRw+jPX1pHH7TXVuxQhkrI6qAnnFXS/sMrt2VDn xAK16LjhTg0/smDYTkI4+X+b2WFHLoqKfIPJdYTo0hZ4eGVum37t7xKYRGyv7Mym2RJj ErCObKOWyY4sMldrlWg1+qqsd2d2ztBnZvPD30xRYaH4l2GNVrhfi9TFOdwGOGjOcTVL a15N9TtWzDP34mIapMhCxZxZnWFu//cxmGy+9iwIiiqeDWpzXlbGB+dynU4CwDpsHcjk ddOw== X-Gm-Message-State: ACrzQf1eXJEXZmc4apGr66+hZX/gf8k3C2UVdXDxEj0hxfGj0jLjDgZn WllB+UeWgysGu/I1rKoFcn/GoIDTaMRMAg== X-Google-Smtp-Source: AMsMyM5xccuoThOCHQuKXWiGZw4lu08/1jHLSLUi3vBtvXAiveltYyoelobiKcRp8pvtgBw6MIZysA== X-Received: by 2002:a05:600c:4910:b0:3c7:1428:f17 with SMTP id f16-20020a05600c491000b003c714280f17mr913068wmp.155.1666278981293; Thu, 20 Oct 2022 08:16:21 -0700 (PDT) Received: from rainbowdash.guest.codethink.co.uk ([167.98.27.226]) by smtp.gmail.com with ESMTPSA id bg6-20020a05600c3c8600b003c6f3e5ba42sm41362wmb.46.2022.10.20.08.16.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 08:16:20 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 06/10] pwm: dwc: split pci out of core driver Date: Thu, 20 Oct 2022 16:16:06 +0100 Message-Id: <20221020151610.59443-7-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Moving towards adding non-pci support for the driver, move the pci parts out of the core into their own module. This is partly due to the module_driver() code only being allowed once in a module and also to avoid a number of #ifdef if we build a single file in a system without pci support. Signed-off-by: Ben Dooks Tested-by: Jarkko Nikula --- v6: - put DWC_PERIOD_NS back to avoid bisect issues v4: - removed DWC_PERIOD_NS as not needed --- drivers/pwm/Kconfig | 14 +++- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-pci.c | 133 ++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.c | 158 +------------------------------------- drivers/pwm/pwm-dwc.h | 58 ++++++++++++++ 5 files changed, 207 insertions(+), 157 deletions(-) create mode 100644 drivers/pwm/pwm-dwc-pci.c create mode 100644 drivers/pwm/pwm-dwc.h diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 3f3c53af4a56..a9f1c554db2b 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -175,15 +175,23 @@ config PWM_CROS_EC Controller. =20 config PWM_DWC - tristate "DesignWare PWM Controller" - depends on PCI || COMPILE_TEST + tristate "DesignWare PWM Controller core" depends on HAS_IOMEM help - PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + PWM driver for Synopsys DWC PWM Controller. =20 To compile this driver as a module, choose M here: the module will be called pwm-dwc. =20 +config PWM_DWC_PCI + tristate "DesignWare PWM Controller core" + depends on PWM_DWC && HAS_IOMEM && PCI + help + PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-pci. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..a70d36623129 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o +obj-$(CONFIG_PWM_DWC_PCI) +=3D pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) +=3D pwm-fsl-ftm.o obj-$(CONFIG_PWM_HIBVT) +=3D pwm-hibvt.o diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c new file mode 100644 index 000000000000..2213d0e7f3c8 --- /dev/null +++ b/drivers/pwm/pwm-dwc-pci.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver (PCI part) + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + * + * Limitations: + * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and= low + * periods are one or more input clock periods long. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) +{ + struct device *dev =3D &pci->dev; + struct dwc_pwm *dwc; + int ret; + + dwc =3D dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + ret =3D pcim_enable_device(pci); + if (ret) { + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); + return ret; + } + + pci_set_master(pci); + + ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); + if (ret) { + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + return ret; + } + + dwc->base =3D pcim_iomap_table(pci)[0]; + if (!dwc->base) { + dev_err(dev, "Base address missing\n"); + return -ENOMEM; + } + + ret =3D devm_pwmchip_add(dev, &dwc->chip); + if (ret) + return ret; + + pm_runtime_put(dev); + pm_runtime_allow(dev); + + return 0; +} + +static void dwc_pwm_remove(struct pci_dev *pci) +{ + pm_runtime_forbid(&pci->dev); + pm_runtime_get_noresume(&pci->dev); +} + +#ifdef CONFIG_PM_SLEEP +static int dwc_pwm_suspend(struct device *dev) +{ + struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); + int i; + + for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { + if (dwc->chip.pwms[i].state.enabled) { + dev_err(dev, "PWM %u in use by consumer (%s)\n", + i, dwc->chip.pwms[i].label); + return -EBUSY; + } + dwc->ctx[i].cnt =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); + dwc->ctx[i].cnt2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); + dwc->ctx[i].ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); + } + + return 0; +} + +static int dwc_pwm_resume(struct device *dev) +{ + struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); + int i; + + for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { + dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); + } + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); + +static const struct pci_device_id dwc_pwm_id_table[] =3D { + { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ + { } /* Terminating Entry */ +}; +MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); + +static struct pci_driver dwc_pwm_driver =3D { + .name =3D "pwm-dwc", + .probe =3D dwc_pwm_probe, + .remove =3D dwc_pwm_remove, + .id_table =3D dwc_pwm_id_table, + .driver =3D { + .pm =3D &dwc_pwm_pm_ops, + }, +}; + +module_pci_driver(dwc_pwm_driver); + +MODULE_AUTHOR("Felipe Balbi (Intel)"); +MODULE_AUTHOR("Jarkko Nikula "); +MODULE_AUTHOR("Raymond Tan "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 56cde9da2c0e..90a8ae1252a1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -1,16 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * DesignWare PWM Controller driver + * DesignWare PWM Controller driver core * * Copyright (C) 2018-2020 Intel Corporation * * Author: Felipe Balbi (Intel) * Author: Jarkko Nikula * Author: Raymond Tan - * - * Limitations: - * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and= low - * periods are one or more input clock periods long. */ =20 #include @@ -21,51 +17,7 @@ #include #include =20 -#define DWC_TIM_LD_CNT(n) ((n) * 0x14) -#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) -#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) -#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) -#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) -#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) - -#define DWC_TIMERS_INT_STS 0xa0 -#define DWC_TIMERS_EOI 0xa4 -#define DWC_TIMERS_RAW_INT_STS 0xa8 -#define DWC_TIMERS_COMP_VERSION 0xac - -#define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 - -/* Timer Control Register */ -#define DWC_TIM_CTRL_EN BIT(0) -#define DWC_TIM_CTRL_MODE BIT(1) -#define DWC_TIM_CTRL_MODE_FREE (0 << 1) -#define DWC_TIM_CTRL_MODE_USER (1 << 1) -#define DWC_TIM_CTRL_INT_MASK BIT(2) -#define DWC_TIM_CTRL_PWM BIT(3) - -struct dwc_pwm_ctx { - u32 cnt; - u32 cnt2; - u32 ctrl; -}; - -struct dwc_pwm { - struct pwm_chip chip; - void __iomem *base; - struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; -}; -#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) - -static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) -{ - return readl(dwc->base + offset); -} - -static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offs= et) -{ - writel(value, dwc->base + offset); -} +#include "pwm-dwc.h" =20 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) { @@ -196,7 +148,7 @@ static const struct pwm_ops dwc_pwm_ops =3D { .owner =3D THIS_MODULE, }; =20 -static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +struct dwc_pwm *dwc_pwm_alloc(struct device *dev) { struct dwc_pwm *dwc; =20 @@ -211,109 +163,7 @@ static struct dwc_pwm *dwc_pwm_alloc(struct device *d= ev) dev_set_drvdata(dev, dwc); return dwc; } - -static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) -{ - struct device *dev =3D &pci->dev; - struct dwc_pwm *dwc; - int ret; - - dwc =3D dwc_pwm_alloc(dev); - if (!dwc) - return -ENOMEM; - - ret =3D pcim_enable_device(pci); - if (ret) { - dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); - return ret; - } - - pci_set_master(pci); - - ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); - if (ret) { - dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); - return ret; - } - - dwc->base =3D pcim_iomap_table(pci)[0]; - if (!dwc->base) { - dev_err(dev, "Base address missing\n"); - return -ENOMEM; - } - - ret =3D devm_pwmchip_add(dev, &dwc->chip); - if (ret) - return ret; - - pm_runtime_put(dev); - pm_runtime_allow(dev); - - return 0; -} - -static void dwc_pwm_remove(struct pci_dev *pci) -{ - pm_runtime_forbid(&pci->dev); - pm_runtime_get_noresume(&pci->dev); -} - -#ifdef CONFIG_PM_SLEEP -static int dwc_pwm_suspend(struct device *dev) -{ - struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); - int i; - - for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { - if (dwc->chip.pwms[i].state.enabled) { - dev_err(dev, "PWM %u in use by consumer (%s)\n", - i, dwc->chip.pwms[i].label); - return -EBUSY; - } - dwc->ctx[i].cnt =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); - dwc->ctx[i].cnt2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); - dwc->ctx[i].ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); - } - - return 0; -} - -static int dwc_pwm_resume(struct device *dev) -{ - struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); - int i; - - for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { - dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); - } - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); - -static const struct pci_device_id dwc_pwm_id_table[] =3D { - { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ - { } /* Terminating Entry */ -}; -MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); - -static struct pci_driver dwc_pwm_driver =3D { - .name =3D "pwm-dwc", - .probe =3D dwc_pwm_probe, - .remove =3D dwc_pwm_remove, - .id_table =3D dwc_pwm_id_table, - .driver =3D { - .pm =3D &dwc_pwm_pm_ops, - }, -}; - -module_pci_driver(dwc_pwm_driver); +EXPORT_SYMBOL_GPL(dwc_pwm_alloc); =20 MODULE_AUTHOR("Felipe Balbi (Intel)"); MODULE_AUTHOR("Jarkko Nikula "); diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h new file mode 100644 index 000000000000..68f98eb76152 --- /dev/null +++ b/drivers/pwm/pwm-dwc.h @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + */ + +#define DWC_TIM_LD_CNT(n) ((n) * 0x14) +#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) +#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) +#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) +#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) +#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) + +#define DWC_TIMERS_INT_STS 0xa0 +#define DWC_TIMERS_EOI 0xa4 +#define DWC_TIMERS_RAW_INT_STS 0xa8 +#define DWC_TIMERS_COMP_VERSION 0xac + +#define DWC_TIMERS_TOTAL 8 +#define DWC_CLK_PERIOD_NS 10 + +/* Timer Control Register */ +#define DWC_TIM_CTRL_EN BIT(0) +#define DWC_TIM_CTRL_MODE BIT(1) +#define DWC_TIM_CTRL_MODE_FREE (0 << 1) +#define DWC_TIM_CTRL_MODE_USER (1 << 1) +#define DWC_TIM_CTRL_INT_MASK BIT(2) +#define DWC_TIM_CTRL_PWM BIT(3) + +struct dwc_pwm_ctx { + u32 cnt; + u32 cnt2; + u32 ctrl; +}; + +struct dwc_pwm { + struct pwm_chip chip; + void __iomem *base; + struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; +}; +#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) + +static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) +{ + return readl(dwc->base + offset); +} + +static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offs= et) +{ + writel(value, dwc->base + offset); +} + +extern struct dwc_pwm *dwc_pwm_alloc(struct device *dev); --=20 2.35.1 From nobody Wed Apr 8 00:00:01 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A7A7C433FE for ; Thu, 20 Oct 2022 15:16:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230228AbiJTPQu (ORCPT ); Thu, 20 Oct 2022 11:16:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230137AbiJTPQ2 (ORCPT ); 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Thu, 20 Oct 2022 08:16:21 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 07/10] pwm: dwc: make timer clock configurable Date: Thu, 20 Oct 2022 16:16:07 +0100 Message-Id: <20221020151610.59443-8-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks Tested-by: Jarkko Nikula --- v6: - removed DWC_CLK_PERIOD_NS as it is now not needed v4: - moved earlier before the of changes to make the of changes one patch v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc-pci.c | 1 + drivers/pwm/pwm-dwc.c | 10 ++++++---- drivers/pwm/pwm-dwc.h | 3 ++- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c index 2213d0e7f3c8..949423e368f9 100644 --- a/drivers/pwm/pwm-dwc-pci.c +++ b/drivers/pwm/pwm-dwc-pci.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #include "pwm-dwc.h" =20 diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 90a8ae1252a1..1251620ab771 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include =20 @@ -47,13 +48,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; @@ -128,12 +129,12 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, =20 duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty +=3D 1; - duty *=3D DWC_CLK_PERIOD_NS; + duty *=3D dwc->clk_ns; state->duty_cycle =3D duty; =20 period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period +=3D 1; - period *=3D DWC_CLK_PERIOD_NS; + period *=3D dwc->clk_ns; period +=3D duty; state->period =3D period; =20 @@ -156,6 +157,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; =20 + dwc->clk_ns =3D 10; dwc->chip.dev =3D dev; dwc->chip.ops =3D &dwc_pwm_ops; dwc->chip.npwm =3D DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index 68f98eb76152..dc451cb2eff5 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -22,7 +22,6 @@ #define DWC_TIMERS_COMP_VERSION 0xac =20 #define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 =20 /* Timer Control Register */ #define DWC_TIM_CTRL_EN BIT(0) @@ -41,6 +40,8 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; 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Thu, 20 Oct 2022 08:16:22 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 08/10] pwm: dwc: add of/platform support Date: Thu, 20 Oct 2022 16:16:08 +0100 Message-Id: <20221020151610.59443-9-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The dwc pwm controller can be used in non-PCI systems, so allow either platform or OF based probing. Signed-off-by: Ben Dooks Tested-by: Jarkko Nikula --- v5: - fix missing " in kconfig - remove .remove method, devm already sorts this. - merge pwm-number code - split the of code out of the core - get bus clock v4: - moved the compile test code earlier - fixed review comments - used NS_PER_SEC - use devm_clk_get_enabled - ensure we get the bus clock v3: - changed compatible name fixup add pwm/Kconfig --- drivers/pwm/Kconfig | 9 +++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-of.c | 76 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) create mode 100644 drivers/pwm/pwm-dwc-of.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a9f1c554db2b..c734f58a8bfc 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -192,6 +192,15 @@ config PWM_DWC_PCI To compile this driver as a module, choose M here: the module will be called pwm-dwc-pci. =20 +config PWM_DWC_OF + tristate "DesignWare PWM Controller (OF bus)" + depends on PWM_DWC && OF + help + PWM driver for Synopsys DWC PWM Controller on an OF bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-of. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index a70d36623129..d1fd1641f077 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o +obj-$(CONFIG_PWM_DWC_OF) +=3D pwm-dwc-of.o obj-$(CONFIG_PWM_DWC_PCI) +=3D pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) +=3D pwm-fsl-ftm.o diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c new file mode 100644 index 000000000000..c5b4351cc7b0 --- /dev/null +++ b/drivers/pwm/pwm-dwc-of.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver OF + * + * Copyright (C) 2022 SiFive, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_plat_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct dwc_pwm *dwc; + struct clk *bus; + u32 nr_pwm; + + dwc =3D dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) { + if (nr_pwm > DWC_TIMERS_TOTAL) + dev_err(dev, "too many PWMs (%d) specified, capping at %d\n", + nr_pwm, dwc->chip.npwm); + else + dwc->chip.npwm =3D nr_pwm; + } + + dwc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc->base)) + return PTR_ERR(dwc->base); + + bus =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(bus)) + return dev_err_probe(dev, PTR_ERR(bus), + "failed to get clock\n"); + + dwc->clk =3D devm_clk_get_enabled(dev, "timer"); + if (IS_ERR(dwc->clk)) + return dev_err_probe(dev, PTR_ERR(dwc->clk), + "failed to get timer clock\n"); + + dwc->clk_ns =3D NSEC_PER_SEC / clk_get_rate(dwc->clk); + return devm_pwmchip_add(dev, &dwc->chip); +} + +static const struct of_device_id dwc_pwm_dt_ids[] =3D { + { .compatible =3D "snps,dw-apb-timers-pwm2" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids); + +static struct platform_driver dwc_pwm_plat_driver =3D { + .driver =3D { + .name =3D "dwc-pwm", + .of_match_table =3D dwc_pwm_dt_ids, + }, + .probe =3D dwc_pwm_plat_probe, +}; + +module_platform_driver(dwc_pwm_plat_driver); + +MODULE_ALIAS("platform:dwc-pwm-of"); +MODULE_AUTHOR("Ben Dooks "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); --=20 2.35.1 From nobody Wed Apr 8 00:00:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AC1DC4332F for ; Thu, 20 Oct 2022 15:17:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230286AbiJTPRJ (ORCPT ); Thu, 20 Oct 2022 11:17:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230041AbiJTPQ3 (ORCPT ); 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Thu, 20 Oct 2022 08:16:23 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 09/10] pwm: dwc: add PWM bit unset in get_state call Date: Thu, 20 Oct 2022 16:16:09 +0100 Message-Id: <20221020151610.59443-10-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks Tested-by: Jarkko Nikula --- v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 1251620ab771..5ef0fe7ea3e9 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -121,23 +121,30 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; =20 pm_runtime_get_sync(chip->dev); =20 - state->enabled =3D !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); =20 - duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty +=3D 1; - duty *=3D dwc->clk_ns; - state->duty_cycle =3D duty; + state->enabled =3D !!(ctrl & DWC_TIM_CTRL_EN); =20 - period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period +=3D 1; - period *=3D dwc->clk_ns; - period +=3D duty; - state->period =3D period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D (ld2 + 1) * dwc->clk_ns; + period +=3D duty; + } else { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D duty * 2; + } =20 + state->period =3D period; + state->duty_cycle =3D duty; state->polarity =3D PWM_POLARITY_INVERSED; =20 pm_runtime_put_sync(chip->dev); --=20 2.35.1 From nobody Wed Apr 8 00:00:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E50EC4332F for ; Thu, 20 Oct 2022 15:17:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230176AbiJTPRQ (ORCPT ); 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Thu, 20 Oct 2022 08:16:24 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v6 10/10] pwm: dwc: use clock rate in hz to avoid rounding issues Date: Thu, 20 Oct 2022 16:16:10 +0100 Message-Id: <20221020151610.59443-11-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020151610.59443-1-ben.dooks@sifive.com> References: <20221020151610.59443-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As noted, the clock-rate when not a nice multiple of ns is probably going to end up with inacurate caculations, as well as on a non pci system the rate may change (although we've not put a clock rate change notifier in this code yet) so we also add some quick checks of the rate when we do any calculations with it. Signed-off-by; Ben Dooks Reported-by: Uwe Kleine-K=C3=B6nig Tested-by: Jarkko Nikula --- drivers/pwm/pwm-dwc-of.c | 2 +- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++++--------- drivers/pwm/pwm-dwc.h | 2 +- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c index c5b4351cc7b0..5f7f066859d4 100644 --- a/drivers/pwm/pwm-dwc-of.c +++ b/drivers/pwm/pwm-dwc-of.c @@ -50,7 +50,7 @@ static int dwc_pwm_plat_probe(struct platform_device *pde= v) return dev_err_probe(dev, PTR_ERR(dwc->clk), "failed to get timer clock\n"); =20 - dwc->clk_ns =3D NSEC_PER_SEC / clk_get_rate(dwc->clk); + dwc->clk_rate =3D clk_get_rate(dwc->clk); return devm_pwmchip_add(dev, &dwc->chip); } =20 diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 5ef0fe7ea3e9..f48a6245a3b5 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -43,18 +43,22 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, u32 high; u32 low; =20 + if (dwc->clk) + dwc->clk_rate =3D clk_get_rate(dwc->clk); + /* * Calculate width of low and high period in terms of input clock * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); + tmp =3D state->duty_cycle * dwc->clk_rate; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 - tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - dwc->clk_ns); + tmp =3D (state->period - state->duty_cycle) * dwc->clk_rate; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; @@ -120,6 +124,7 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, st= ruct pwm_device *pwm, struct pwm_state *state) { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); + unsigned long clk_rate; u64 duty, period; u32 ctrl, ld, ld2; =20 @@ -129,22 +134,28 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); =20 + if (dwc->clk) + dwc->clk_rate =3D clk_get_rate(dwc->clk); + + clk_rate =3D dwc->clk_rate; state->enabled =3D !!(ctrl & DWC_TIM_CTRL_EN); =20 /* If we're not in PWM, technically the output is a 50-50 * based on the timer load-count only. */ if (ctrl & DWC_TIM_CTRL_PWM) { - duty =3D (ld + 1) * dwc->clk_ns; - period =3D (ld2 + 1) * dwc->clk_ns; + duty =3D ld + 1; + period =3D ld2 + 1; period +=3D duty; } else { - duty =3D (ld + 1) * dwc->clk_ns; + duty =3D ld + 1; period =3D duty * 2; } =20 - state->period =3D period; - state->duty_cycle =3D duty; + duty *=3D NSEC_PER_SEC; + period *=3D NSEC_PER_SEC; + state->period =3D DIV_ROUND_CLOSEST_ULL(period, clk_rate); + state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL(duty, clk_rate); state->polarity =3D PWM_POLARITY_INVERSED; =20 pm_runtime_put_sync(chip->dev); @@ -164,7 +175,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; =20 - dwc->clk_ns =3D 10; + dwc->clk_rate =3D NSEC_PER_SEC / 10; dwc->chip.dev =3D dev; dwc->chip.ops =3D &dwc_pwm_ops; dwc->chip.npwm =3D DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index dc451cb2eff5..19bdc2224690 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -41,7 +41,7 @@ struct dwc_pwm { struct pwm_chip chip; void __iomem *base; struct clk *clk; - unsigned int clk_ns; + unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) --=20 2.35.1