From nobody Thu Oct 2 22:01:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA3F9C433FE for ; Thu, 20 Oct 2022 13:11:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230489AbiJTNLS (ORCPT ); Thu, 20 Oct 2022 09:11:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230410AbiJTNKG (ORCPT ); Thu, 20 Oct 2022 09:10:06 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3382616592; Thu, 20 Oct 2022 06:09:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666271385; x=1697807385; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=39GjVRLDPS/1QDYVIMky4FSkEo1Jdj3lBXRSLGyOUSU=; b=sYynPwrJjePvTmAltSONoU1EiLrwiXt+VrFq4T5eabw8oK4D87RIk2DM YKNbfoW/Rdasqy0c0lwcfx2ZbW4QA3hfm6+N/kYNH4IEzJdgdIKou5+/1 13bT2TaJ+WqX9Yi34+zlljFqXLxbkgPcDKrrepg/1YC0LL03RIfMrHQV3 yvdzK16bh24MUTN8P9ISZU2r6dD7pMpejg7le7cjeOtDEIZyUT5Qc4UXn mhBEwS1uLpFVIQ/hbeEE87uY+gjgwfon1N1EAHJmF7MP7ooX8SU7VR/KG 6nD4kIVFfqlLaIs0NIQJpvGNu6BdDacGQec7E4kASp7r+zYpEKdSeLgfx A==; X-IronPort-AV: E=Sophos;i="5.95,198,1661842800"; d="scan'208";a="119582009" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Oct 2022 06:09:36 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 20 Oct 2022 06:09:36 -0700 Received: from den-dk-m31857.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 20 Oct 2022 06:09:33 -0700 From: Steen Hegelund To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni CC: Steen Hegelund , , Randy Dunlap , "Casper Andersson" , Russell King , Wan Jiabing , "Nathan Huckleberry" , , , Subject: [PATCH net-next v3 8/9] net: microchip: sparx5: Adding KUNIT test VCAP model Date: Thu, 20 Oct 2022 15:09:03 +0200 Message-ID: <20221020130904.1215072-9-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221020130904.1215072-1-steen.hegelund@microchip.com> References: <20221020130904.1215072-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This provides a test VCAP model for use in a KUNIT test. The model provides 3 different VCAP types for better test coverage. Signed-off-by: Steen Hegelund --- drivers/net/ethernet/microchip/vcap/Makefile | 1 + .../microchip/vcap/vcap_model_kunit.c | 5570 +++++++++++++++++ .../microchip/vcap/vcap_model_kunit.h | 10 + 3 files changed, 5581 insertions(+) create mode 100644 drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c create mode 100644 drivers/net/ethernet/microchip/vcap/vcap_model_kunit.h diff --git a/drivers/net/ethernet/microchip/vcap/Makefile b/drivers/net/eth= ernet/microchip/vcap/Makefile index 598d1c296f38..b377569f92d8 100644 --- a/drivers/net/ethernet/microchip/vcap/Makefile +++ b/drivers/net/ethernet/microchip/vcap/Makefile @@ -4,5 +4,6 @@ # =20 obj-$(CONFIG_VCAP) +=3D vcap.o +obj-$(CONFIG_VCAP_KUNIT_TEST) +=3D vcap_model_kunit.o =20 vcap-y +=3D vcap_api.o diff --git a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c b/drive= rs/net/ethernet/microchip/vcap/vcap_model_kunit.c new file mode 100644 index 000000000000..5d681d2697cd --- /dev/null +++ b/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c @@ -0,0 +1,5570 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. + * Microchip VCAP API Test VCAP Model Data + */ + +#include +#include + +#include "vcap_api.h" +#include "vcap_model_kunit.h" + +/* keyfields */ +static const struct vcap_field is0_mll_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 7, + }, + [VCAP_KF_8021Q_VLAN_TAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 3, + }, + [VCAP_KF_8021Q_VID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 28, + .width =3D 3, + }, + [VCAP_KF_8021Q_VID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 31, + .width =3D 12, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 43, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 91, + .width =3D 48, + }, + [VCAP_KF_ETYPE_MPLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 139, + .width =3D 2, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 141, + .width =3D 8, + }, +}; + +static const struct vcap_field is0_tri_vid_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 7, + }, + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_GEN_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 24, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 30, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 33, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 34, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 46, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 49, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI1] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 53, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 65, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI2] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 71, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 72, + .width =3D 12, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 8, + }, + [VCAP_KF_OAM_Y1731_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_OAM_MEL_FLAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 93, + .width =3D 7, + }, +}; + +static const struct vcap_field is0_ll_full_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 7, + }, + [VCAP_KF_8021Q_VLAN_TAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 19, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 32, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 35, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI1] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 38, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 39, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 51, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 54, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI2] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 57, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 58, + .width =3D 12, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 70, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 118, + .width =3D 48, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 166, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 167, + .width =3D 16, + }, + [VCAP_KF_IP_SNAP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 183, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 184, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 185, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 187, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 188, + .width =3D 1, + }, + [VCAP_KF_L3_DSCP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 189, + .width =3D 6, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 195, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 227, + .width =3D 32, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 259, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 260, + .width =3D 1, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 261, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 277, + .width =3D 8, + }, +}; + +static const struct vcap_field is0_normal_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_GEN_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 12, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 19, + .width =3D 65, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 86, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 89, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 92, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 96, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 108, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 111, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI1] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 114, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 115, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 127, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 130, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI2] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 133, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 134, + .width =3D 12, + }, + [VCAP_KF_DST_ENTRY] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 146, + .width =3D 1, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 147, + .width =3D 48, + }, + [VCAP_KF_IP_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 195, + .width =3D 1, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 196, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 197, + .width =3D 16, + }, + [VCAP_KF_IP_SNAP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 213, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 214, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 215, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 217, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, + [VCAP_KF_L3_DSCP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 219, + .width =3D 6, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 225, + .width =3D 32, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 257, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 258, + .width =3D 1, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 259, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 275, + .width =3D 8, + }, +}; + +static const struct vcap_field is0_normal_7tuple_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_GEN_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 12, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 18, + .width =3D 65, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 83, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 85, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 95, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 107, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 110, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI1] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 113, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 114, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 126, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 129, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI2] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 132, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 133, + .width =3D 12, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 145, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 193, + .width =3D 48, + }, + [VCAP_KF_IP_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 241, + .width =3D 1, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 242, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 243, + .width =3D 16, + }, + [VCAP_KF_IP_SNAP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 259, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 260, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 261, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 263, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 264, + .width =3D 1, + }, + [VCAP_KF_L3_DSCP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 265, + .width =3D 6, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 271, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 399, + .width =3D 128, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 527, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 528, + .width =3D 1, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 529, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 545, + .width =3D 8, + }, +}; + +static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_GEN_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 12, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 19, + .width =3D 65, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 86, + .width =3D 3, + }, + [VCAP_KF_8021Q_TPID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 89, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 92, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID0] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 96, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 108, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 111, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI1] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 114, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID1] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 115, + .width =3D 12, + }, + [VCAP_KF_8021Q_TPID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 127, + .width =3D 3, + }, + [VCAP_KF_8021Q_PCP2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 130, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI2] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 133, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID2] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 134, + .width =3D 12, + }, + [VCAP_KF_IP_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 146, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 147, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 148, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 150, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 151, + .width =3D 1, + }, + [VCAP_KF_L3_DSCP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 152, + .width =3D 6, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 158, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 190, + .width =3D 32, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 222, + .width =3D 8, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 230, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 231, + .width =3D 1, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 232, + .width =3D 8, + }, + [VCAP_KF_IP_PAYLOAD_5TUPLE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 240, + .width =3D 32, + }, +}; + +static const struct vcap_field is0_pure_5tuple_ip4_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_GEN_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 12, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 19, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 20, + .width =3D 1, + }, + [VCAP_KF_L3_DSCP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 21, + .width =3D 6, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 59, + .width =3D 32, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 99, + .width =3D 8, + }, + [VCAP_KF_IP_PAYLOAD_5TUPLE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 107, + .width =3D 32, + }, +}; + +static const struct vcap_field is0_etag_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 7, + }, + [VCAP_KF_8021BR_E_TAGGED] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 10, + .width =3D 1, + }, + [VCAP_KF_8021BR_GRP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 11, + .width =3D 2, + }, + [VCAP_KF_8021BR_ECID_EXT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 8, + }, + [VCAP_KF_8021BR_ECID_BASE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 21, + .width =3D 12, + }, + [VCAP_KF_8021BR_IGR_ECID_EXT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 33, + .width =3D 8, + }, + [VCAP_KF_8021BR_IGR_ECID_BASE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 12, + }, +}; + +static const struct vcap_field is2_mac_etype_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L3_SMAC_SIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 86, + .width =3D 1, + }, + [VCAP_KF_L3_DMAC_DIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 90, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 138, + .width =3D 48, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 186, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 187, + .width =3D 16, + }, + [VCAP_KF_L2_PAYLOAD_ETYPE] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 203, + .width =3D 64, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 267, + .width =3D 16, + }, + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 283, + .width =3D 1, + }, + [VCAP_KF_OAM_Y1731_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 284, + .width =3D 1, + }, +}; + +static const struct vcap_field is2_arp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 86, + .width =3D 48, + }, + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 134, + .width =3D 1, + }, + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 135, + .width =3D 1, + }, + [VCAP_KF_ARP_LEN_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 136, + .width =3D 1, + }, + [VCAP_KF_ARP_TGT_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 137, + .width =3D 1, + }, + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 138, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 139, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 140, + .width =3D 2, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 142, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 174, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 206, + .width =3D 1, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 207, + .width =3D 16, + }, +}; + +static const struct vcap_field is2_ip4_tcp_udp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L3_SMAC_SIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 86, + .width =3D 1, + }, + [VCAP_KF_L3_DMAC_DIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 96, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 104, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 136, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 168, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 169, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 170, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 186, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 202, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 219, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 220, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 221, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 222, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 223, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 224, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 225, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 226, + .width =3D 64, + }, +}; + +static const struct vcap_field is2_ip4_other_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L3_SMAC_SIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 86, + .width =3D 1, + }, + [VCAP_KF_L3_DMAC_DIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 96, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 104, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 136, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 168, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 169, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 177, + .width =3D 16, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U112, + .offset =3D 193, + .width =3D 96, + }, +}; + +static const struct vcap_field is2_ip6_std_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L3_SMAC_SIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 86, + .width =3D 1, + }, + [VCAP_KF_L3_DMAC_DIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 91, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 219, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 220, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 228, + .width =3D 16, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 244, + .width =3D 40, + }, +}; + +static const struct vcap_field is2_ip_7tuple_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 11, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 18, + .width =3D 65, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 83, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 86, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 99, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 112, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 113, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 116, + .width =3D 1, + }, + [VCAP_KF_L3_SMAC_SIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 117, + .width =3D 1, + }, + [VCAP_KF_L3_DMAC_DIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 118, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 119, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 120, + .width =3D 1, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 121, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 169, + .width =3D 48, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 217, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 219, + .width =3D 8, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 227, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 355, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 483, + .width =3D 1, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 484, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 485, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 486, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 502, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 518, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 534, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 535, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 536, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 537, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 538, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 539, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 540, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 541, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 542, + .width =3D 64, + }, +}; + +static const struct vcap_field is2_ip6_vid_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 26, + .width =3D 13, + }, + [VCAP_KF_L3_SMAC_SIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_KF_L3_DMAC_DIP_MATCH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 40, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 41, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 42, + .width =3D 1, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 43, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 171, + .width =3D 128, + }, +}; + +static const struct vcap_field es2_mac_etype_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_ACL_GRP_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 8, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 45, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 77, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 78, + .width =3D 9, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 96, + .width =3D 1, + }, + [VCAP_KF_MIRROR_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 97, + .width =3D 2, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 99, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 147, + .width =3D 48, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 195, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 196, + .width =3D 16, + }, + [VCAP_KF_L2_PAYLOAD_ETYPE] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 212, + .width =3D 64, + }, + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 276, + .width =3D 1, + }, + [VCAP_KF_OAM_Y1731_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 277, + .width =3D 1, + }, +}; + +static const struct vcap_field es2_arp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_ACL_GRP_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 8, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 45, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 77, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 78, + .width =3D 9, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_MIRROR_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 96, + .width =3D 2, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 98, + .width =3D 48, + }, + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 146, + .width =3D 1, + }, + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 147, + .width =3D 1, + }, + [VCAP_KF_ARP_LEN_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 148, + .width =3D 1, + }, + [VCAP_KF_ARP_TGT_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 149, + .width =3D 1, + }, + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 150, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 151, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 152, + .width =3D 2, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 154, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 186, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, +}; + +static const struct vcap_field es2_ip4_tcp_udp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_ACL_GRP_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 8, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 45, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 77, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 78, + .width =3D 9, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 96, + .width =3D 1, + }, + [VCAP_KF_MIRROR_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 97, + .width =3D 2, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 99, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 100, + .width =3D 2, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 102, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 103, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 104, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 112, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 144, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 176, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 177, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 178, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 194, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 210, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 226, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 227, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 228, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 229, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 230, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 231, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 232, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 233, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 234, + .width =3D 64, + }, +}; + +static const struct vcap_field es2_ip4_other_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_ACL_GRP_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 8, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 45, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 77, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 78, + .width =3D 9, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 96, + .width =3D 1, + }, + [VCAP_KF_MIRROR_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 97, + .width =3D 2, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 99, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 100, + .width =3D 2, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 102, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 103, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 104, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 112, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 144, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 176, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 177, + .width =3D 8, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U112, + .offset =3D 185, + .width =3D 96, + }, +}; + +static const struct vcap_field es2_ip_7tuple_keyfield[] =3D { + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_KF_ACL_GRP_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 1, + .width =3D 8, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 10, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 11, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 26, + .width =3D 13, + }, + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 39, + .width =3D 3, + }, + [VCAP_KF_IF_EGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 32, + }, + [VCAP_KF_IF_IGR_PORT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 74, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 75, + .width =3D 9, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 87, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 88, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 91, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 92, + .width =3D 1, + }, + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_MIRROR_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 94, + .width =3D 2, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 96, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 144, + .width =3D 48, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 192, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 193, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 194, + .width =3D 8, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 202, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 330, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 458, + .width =3D 1, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 459, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 460, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 461, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 477, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 493, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 509, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 510, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 511, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 512, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 513, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 514, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 515, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 516, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 517, + .width =3D 64, + }, +}; + +static const struct vcap_field es2_ip4_vid_keyfield[] =3D { + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_KF_ACL_GRP_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 1, + .width =3D 8, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 10, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 11, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 25, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 26, + .width =3D 13, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 39, + .width =3D 3, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 42, + .width =3D 1, + }, + [VCAP_KF_COSID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 43, + .width =3D 3, + }, + [VCAP_KF_L3_DPL_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 46, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 47, + .width =3D 1, + }, + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 48, + .width =3D 1, + }, + [VCAP_KF_MIRROR_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 49, + .width =3D 2, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 51, + .width =3D 1, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 52, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 32, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 116, + .width =3D 16, + }, +}; + +static const struct vcap_field es2_ip6_vid_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 3, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 3, + .width =3D 1, + }, + [VCAP_KF_ACL_GRP_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 8, + }, + [VCAP_KF_PROT_ACTIVE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 12, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 13, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 42, + .width =3D 1, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 43, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 171, + .width =3D 128, + }, +}; + +/* keyfield_set */ +static const struct vcap_set is0_keyfield_set[] =3D { + [VCAP_KFS_MLL] =3D { + .type_id =3D 0, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, + [VCAP_KFS_TRI_VID] =3D { + .type_id =3D 0, + .sw_per_item =3D 2, + .sw_cnt =3D 6, + }, + [VCAP_KFS_LL_FULL] =3D { + .type_id =3D 0, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_NORMAL] =3D { + .type_id =3D 1, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_NORMAL_7TUPLE] =3D { + .type_id =3D 0, + .sw_per_item =3D 12, + .sw_cnt =3D 1, + }, + [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D { + .type_id =3D 2, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_PURE_5TUPLE_IP4] =3D { + .type_id =3D 2, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, + [VCAP_KFS_ETAG] =3D { + .type_id =3D 3, + .sw_per_item =3D 2, + .sw_cnt =3D 6, + }, +}; + +static const struct vcap_set is2_keyfield_set[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D { + .type_id =3D 0, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_ARP] =3D { + .type_id =3D 3, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_TCP_UDP] =3D { + .type_id =3D 4, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_OTHER] =3D { + .type_id =3D 5, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP6_STD] =3D { + .type_id =3D 6, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP_7TUPLE] =3D { + .type_id =3D 1, + .sw_per_item =3D 12, + .sw_cnt =3D 1, + }, + [VCAP_KFS_IP6_VID] =3D { + .type_id =3D 9, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, +}; + +static const struct vcap_set es2_keyfield_set[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D { + .type_id =3D 0, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_ARP] =3D { + .type_id =3D 1, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_TCP_UDP] =3D { + .type_id =3D 2, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_OTHER] =3D { + .type_id =3D 3, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP_7TUPLE] =3D { + .type_id =3D -1, + .sw_per_item =3D 12, + .sw_cnt =3D 1, + }, + [VCAP_KFS_IP4_VID] =3D { + .type_id =3D -1, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, + [VCAP_KFS_IP6_VID] =3D { + .type_id =3D 5, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, +}; + +/* keyfield_set map */ +static const struct vcap_field *is0_keyfield_set_map[] =3D { + [VCAP_KFS_MLL] =3D is0_mll_keyfield, + [VCAP_KFS_TRI_VID] =3D is0_tri_vid_keyfield, + [VCAP_KFS_LL_FULL] =3D is0_ll_full_keyfield, + [VCAP_KFS_NORMAL] =3D is0_normal_keyfield, + [VCAP_KFS_NORMAL_7TUPLE] =3D is0_normal_7tuple_keyfield, + [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D is0_normal_5tuple_ip4_keyfield, + [VCAP_KFS_PURE_5TUPLE_IP4] =3D is0_pure_5tuple_ip4_keyfield, + [VCAP_KFS_ETAG] =3D is0_etag_keyfield, +}; + +static const struct vcap_field *is2_keyfield_set_map[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D is2_mac_etype_keyfield, + [VCAP_KFS_ARP] =3D is2_arp_keyfield, + [VCAP_KFS_IP4_TCP_UDP] =3D is2_ip4_tcp_udp_keyfield, + [VCAP_KFS_IP4_OTHER] =3D is2_ip4_other_keyfield, + [VCAP_KFS_IP6_STD] =3D is2_ip6_std_keyfield, + [VCAP_KFS_IP_7TUPLE] =3D is2_ip_7tuple_keyfield, + [VCAP_KFS_IP6_VID] =3D is2_ip6_vid_keyfield, +}; + +static const struct vcap_field *es2_keyfield_set_map[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D es2_mac_etype_keyfield, + [VCAP_KFS_ARP] =3D es2_arp_keyfield, + [VCAP_KFS_IP4_TCP_UDP] =3D es2_ip4_tcp_udp_keyfield, + [VCAP_KFS_IP4_OTHER] =3D es2_ip4_other_keyfield, + [VCAP_KFS_IP_7TUPLE] =3D es2_ip_7tuple_keyfield, + [VCAP_KFS_IP4_VID] =3D es2_ip4_vid_keyfield, + [VCAP_KFS_IP6_VID] =3D es2_ip6_vid_keyfield, +}; + +/* keyfield_set map sizes */ +static int is0_keyfield_set_map_size[] =3D { + [VCAP_KFS_MLL] =3D ARRAY_SIZE(is0_mll_keyfield), + [VCAP_KFS_TRI_VID] =3D ARRAY_SIZE(is0_tri_vid_keyfield), + [VCAP_KFS_LL_FULL] =3D ARRAY_SIZE(is0_ll_full_keyfield), + [VCAP_KFS_NORMAL] =3D ARRAY_SIZE(is0_normal_keyfield), + [VCAP_KFS_NORMAL_7TUPLE] =3D ARRAY_SIZE(is0_normal_7tuple_keyfield), + [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D ARRAY_SIZE(is0_normal_5tuple_ip4_keyfiel= d), + [VCAP_KFS_PURE_5TUPLE_IP4] =3D ARRAY_SIZE(is0_pure_5tuple_ip4_keyfield), + [VCAP_KFS_ETAG] =3D ARRAY_SIZE(is0_etag_keyfield), +}; + +static int is2_keyfield_set_map_size[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D ARRAY_SIZE(is2_mac_etype_keyfield), + [VCAP_KFS_ARP] =3D ARRAY_SIZE(is2_arp_keyfield), + [VCAP_KFS_IP4_TCP_UDP] =3D ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), + [VCAP_KFS_IP4_OTHER] =3D ARRAY_SIZE(is2_ip4_other_keyfield), + [VCAP_KFS_IP6_STD] =3D ARRAY_SIZE(is2_ip6_std_keyfield), + [VCAP_KFS_IP_7TUPLE] =3D ARRAY_SIZE(is2_ip_7tuple_keyfield), + [VCAP_KFS_IP6_VID] =3D ARRAY_SIZE(is2_ip6_vid_keyfield), +}; + +static int es2_keyfield_set_map_size[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D ARRAY_SIZE(es2_mac_etype_keyfield), + [VCAP_KFS_ARP] =3D ARRAY_SIZE(es2_arp_keyfield), + [VCAP_KFS_IP4_TCP_UDP] =3D ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), + [VCAP_KFS_IP4_OTHER] =3D ARRAY_SIZE(es2_ip4_other_keyfield), + [VCAP_KFS_IP_7TUPLE] =3D ARRAY_SIZE(es2_ip_7tuple_keyfield), + [VCAP_KFS_IP4_VID] =3D ARRAY_SIZE(es2_ip4_vid_keyfield), + [VCAP_KFS_IP6_VID] =3D ARRAY_SIZE(es2_ip6_vid_keyfield), +}; + +/* actionfields */ +static const struct vcap_field is0_mlbs_actionfield[] =3D { + [VCAP_AF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_COSID_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_COSID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 3, + }, + [VCAP_AF_QOS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 5, + .width =3D 1, + }, + [VCAP_AF_QOS_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 6, + .width =3D 3, + }, + [VCAP_AF_DP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_AF_DP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 2, + }, + [VCAP_AF_MAP_LOOKUP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 2, + }, + [VCAP_AF_MAP_KEY] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 3, + }, + [VCAP_AF_MAP_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 9, + }, + [VCAP_AF_CLS_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 26, + .width =3D 3, + }, + [VCAP_AF_GVID_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 3, + }, + [VCAP_AF_VID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 32, + .width =3D 13, + }, + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 45, + .width =3D 1, + }, + [VCAP_AF_ISDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 46, + .width =3D 12, + }, + [VCAP_AF_FWD_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 58, + .width =3D 1, + }, + [VCAP_AF_CPU_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 59, + .width =3D 1, + }, + [VCAP_AF_CPU_Q] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 60, + .width =3D 3, + }, + [VCAP_AF_OAM_Y1731_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 63, + .width =3D 3, + }, + [VCAP_AF_OAM_TWAMP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 66, + .width =3D 1, + }, + [VCAP_AF_OAM_IP_BFD_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 67, + .width =3D 1, + }, + [VCAP_AF_TC_LABEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 3, + }, + [VCAP_AF_TTL_LABEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 71, + .width =3D 3, + }, + [VCAP_AF_NUM_VLD_LABELS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 74, + .width =3D 2, + }, + [VCAP_AF_FWD_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 76, + .width =3D 3, + }, + [VCAP_AF_MPLS_OAM_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 79, + .width =3D 3, + }, + [VCAP_AF_MPLS_MEP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 82, + .width =3D 1, + }, + [VCAP_AF_MPLS_MIP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 83, + .width =3D 1, + }, + [VCAP_AF_MPLS_OAM_FLAVOR] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_AF_MPLS_IP_CTRL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_AF_PAG_OVERRIDE_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 86, + .width =3D 8, + }, + [VCAP_AF_PAG_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 94, + .width =3D 8, + }, + [VCAP_AF_S2_KEY_SEL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 102, + .width =3D 1, + }, + [VCAP_AF_S2_KEY_SEL_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 103, + .width =3D 6, + }, + [VCAP_AF_PIPELINE_FORCE_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 109, + .width =3D 2, + }, + [VCAP_AF_PIPELINE_ACT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 111, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 112, + .width =3D 5, + }, + [VCAP_AF_NXT_KEY_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 117, + .width =3D 5, + }, + [VCAP_AF_NXT_NORM_W16_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 122, + .width =3D 5, + }, + [VCAP_AF_NXT_OFFSET_FROM_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 127, + .width =3D 2, + }, + [VCAP_AF_NXT_TYPE_AFTER_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 129, + .width =3D 2, + }, + [VCAP_AF_NXT_NORMALIZE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 131, + .width =3D 1, + }, + [VCAP_AF_NXT_IDX_CTRL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 132, + .width =3D 3, + }, + [VCAP_AF_NXT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 135, + .width =3D 12, + }, +}; + +static const struct vcap_field is0_mlbs_reduced_actionfield[] =3D { + [VCAP_AF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_COSID_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_COSID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 3, + }, + [VCAP_AF_QOS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 5, + .width =3D 1, + }, + [VCAP_AF_QOS_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 6, + .width =3D 3, + }, + [VCAP_AF_DP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_AF_DP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 2, + }, + [VCAP_AF_MAP_LOOKUP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 2, + }, + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_AF_ISDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 15, + .width =3D 12, + }, + [VCAP_AF_FWD_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 27, + .width =3D 1, + }, + [VCAP_AF_CPU_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 28, + .width =3D 1, + }, + [VCAP_AF_CPU_Q] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 3, + }, + [VCAP_AF_TC_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 32, + .width =3D 1, + }, + [VCAP_AF_TTL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 33, + .width =3D 1, + }, + [VCAP_AF_FWD_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 34, + .width =3D 3, + }, + [VCAP_AF_MPLS_OAM_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 37, + .width =3D 3, + }, + [VCAP_AF_MPLS_MEP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 40, + .width =3D 1, + }, + [VCAP_AF_MPLS_MIP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 41, + .width =3D 1, + }, + [VCAP_AF_MPLS_OAM_FLAVOR] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 42, + .width =3D 1, + }, + [VCAP_AF_MPLS_IP_CTRL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 43, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_FORCE_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 2, + }, + [VCAP_AF_PIPELINE_ACT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 46, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_PT_REDUCED] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 47, + .width =3D 3, + }, + [VCAP_AF_NXT_KEY_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 50, + .width =3D 5, + }, + [VCAP_AF_NXT_NORM_W32_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 55, + .width =3D 2, + }, + [VCAP_AF_NXT_TYPE_AFTER_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 57, + .width =3D 2, + }, + [VCAP_AF_NXT_NORMALIZE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 59, + .width =3D 1, + }, + [VCAP_AF_NXT_IDX_CTRL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 60, + .width =3D 3, + }, + [VCAP_AF_NXT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 63, + .width =3D 12, + }, +}; + +static const struct vcap_field is0_classification_actionfield[] =3D { + [VCAP_AF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_DSCP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_DSCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 6, + }, + [VCAP_AF_COSID_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 8, + .width =3D 1, + }, + [VCAP_AF_COSID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 9, + .width =3D 3, + }, + [VCAP_AF_QOS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 12, + .width =3D 1, + }, + [VCAP_AF_QOS_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 13, + .width =3D 3, + }, + [VCAP_AF_DP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 16, + .width =3D 1, + }, + [VCAP_AF_DP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 2, + }, + [VCAP_AF_DEI_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 19, + .width =3D 1, + }, + [VCAP_AF_DEI_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 20, + .width =3D 1, + }, + [VCAP_AF_PCP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 21, + .width =3D 1, + }, + [VCAP_AF_PCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 22, + .width =3D 3, + }, + [VCAP_AF_MAP_LOOKUP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 25, + .width =3D 2, + }, + [VCAP_AF_MAP_KEY] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 3, + }, + [VCAP_AF_MAP_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 30, + .width =3D 9, + }, + [VCAP_AF_CLS_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 39, + .width =3D 3, + }, + [VCAP_AF_GVID_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 3, + }, + [VCAP_AF_VID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 45, + .width =3D 13, + }, + [VCAP_AF_VLAN_POP_CNT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 58, + .width =3D 1, + }, + [VCAP_AF_VLAN_POP_CNT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 59, + .width =3D 2, + }, + [VCAP_AF_VLAN_PUSH_CNT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 61, + .width =3D 1, + }, + [VCAP_AF_VLAN_PUSH_CNT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 62, + .width =3D 2, + }, + [VCAP_AF_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 64, + .width =3D 2, + }, + [VCAP_AF_VLAN_WAS_TAGGED] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 66, + .width =3D 2, + }, + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 68, + .width =3D 1, + }, + [VCAP_AF_ISDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 69, + .width =3D 12, + }, + [VCAP_AF_RT_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 81, + .width =3D 2, + }, + [VCAP_AF_LPM_AFFIX_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 83, + .width =3D 1, + }, + [VCAP_AF_LPM_AFFIX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 84, + .width =3D 10, + }, + [VCAP_AF_RLEG_DMAC_CHK_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_AF_TTL_DECR_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_AF_L3_MAC_UPDATE_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 96, + .width =3D 1, + }, + [VCAP_AF_FWD_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 97, + .width =3D 1, + }, + [VCAP_AF_CPU_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 98, + .width =3D 1, + }, + [VCAP_AF_CPU_Q] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 99, + .width =3D 3, + }, + [VCAP_AF_MIP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 102, + .width =3D 2, + }, + [VCAP_AF_OAM_Y1731_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 104, + .width =3D 3, + }, + [VCAP_AF_OAM_TWAMP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 107, + .width =3D 1, + }, + [VCAP_AF_OAM_IP_BFD_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 108, + .width =3D 1, + }, + [VCAP_AF_PAG_OVERRIDE_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 109, + .width =3D 8, + }, + [VCAP_AF_PAG_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 117, + .width =3D 8, + }, + [VCAP_AF_S2_KEY_SEL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 125, + .width =3D 1, + }, + [VCAP_AF_S2_KEY_SEL_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 126, + .width =3D 6, + }, + [VCAP_AF_INJ_MASQ_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 132, + .width =3D 1, + }, + [VCAP_AF_INJ_MASQ_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 133, + .width =3D 7, + }, + [VCAP_AF_LPORT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 140, + .width =3D 1, + }, + [VCAP_AF_INJ_MASQ_LPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 141, + .width =3D 7, + }, + [VCAP_AF_PIPELINE_FORCE_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 148, + .width =3D 2, + }, + [VCAP_AF_PIPELINE_ACT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 150, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 151, + .width =3D 5, + }, + [VCAP_AF_NXT_KEY_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 156, + .width =3D 5, + }, + [VCAP_AF_NXT_NORM_W16_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 161, + .width =3D 5, + }, + [VCAP_AF_NXT_OFFSET_FROM_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 166, + .width =3D 2, + }, + [VCAP_AF_NXT_TYPE_AFTER_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 168, + .width =3D 2, + }, + [VCAP_AF_NXT_NORMALIZE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 170, + .width =3D 1, + }, + [VCAP_AF_NXT_IDX_CTRL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 171, + .width =3D 3, + }, + [VCAP_AF_NXT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 174, + .width =3D 12, + }, +}; + +static const struct vcap_field is0_full_actionfield[] =3D { + [VCAP_AF_DSCP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_DSCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 1, + .width =3D 6, + }, + [VCAP_AF_COSID_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 7, + .width =3D 1, + }, + [VCAP_AF_COSID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 8, + .width =3D 3, + }, + [VCAP_AF_QOS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 11, + .width =3D 1, + }, + [VCAP_AF_QOS_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 3, + }, + [VCAP_AF_DP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_AF_DP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 2, + }, + [VCAP_AF_DEI_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 18, + .width =3D 1, + }, + [VCAP_AF_DEI_VAL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 19, + .width =3D 1, + }, + [VCAP_AF_PCP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 20, + .width =3D 1, + }, + [VCAP_AF_PCP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 21, + .width =3D 3, + }, + [VCAP_AF_MAP_LOOKUP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 24, + .width =3D 2, + }, + [VCAP_AF_MAP_KEY] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 26, + .width =3D 3, + }, + [VCAP_AF_MAP_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 29, + .width =3D 9, + }, + [VCAP_AF_CLS_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 38, + .width =3D 3, + }, + [VCAP_AF_GVID_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 3, + }, + [VCAP_AF_VID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 13, + }, + [VCAP_AF_VLAN_POP_CNT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 57, + .width =3D 1, + }, + [VCAP_AF_VLAN_POP_CNT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 58, + .width =3D 2, + }, + [VCAP_AF_VLAN_PUSH_CNT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 60, + .width =3D 1, + }, + [VCAP_AF_VLAN_PUSH_CNT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 61, + .width =3D 2, + }, + [VCAP_AF_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 63, + .width =3D 2, + }, + [VCAP_AF_VLAN_WAS_TAGGED] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 65, + .width =3D 2, + }, + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 67, + .width =3D 1, + }, + [VCAP_AF_ISDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 12, + }, + [VCAP_AF_MASK_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 80, + .width =3D 3, + }, + [VCAP_AF_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 83, + .width =3D 65, + }, + [VCAP_AF_RT_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 148, + .width =3D 2, + }, + [VCAP_AF_LPM_AFFIX_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 150, + .width =3D 1, + }, + [VCAP_AF_LPM_AFFIX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 151, + .width =3D 10, + }, + [VCAP_AF_RLEG_DMAC_CHK_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 161, + .width =3D 1, + }, + [VCAP_AF_TTL_DECR_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 162, + .width =3D 1, + }, + [VCAP_AF_L3_MAC_UPDATE_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 163, + .width =3D 1, + }, + [VCAP_AF_CPU_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 164, + .width =3D 1, + }, + [VCAP_AF_CPU_Q] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 165, + .width =3D 3, + }, + [VCAP_AF_MIP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 168, + .width =3D 2, + }, + [VCAP_AF_OAM_Y1731_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 170, + .width =3D 3, + }, + [VCAP_AF_OAM_TWAMP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 173, + .width =3D 1, + }, + [VCAP_AF_OAM_IP_BFD_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 174, + .width =3D 1, + }, + [VCAP_AF_RSVD_LBL_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 175, + .width =3D 4, + }, + [VCAP_AF_TC_LABEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 179, + .width =3D 3, + }, + [VCAP_AF_TTL_LABEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 182, + .width =3D 3, + }, + [VCAP_AF_NUM_VLD_LABELS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 185, + .width =3D 2, + }, + [VCAP_AF_FWD_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 187, + .width =3D 3, + }, + [VCAP_AF_MPLS_OAM_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 190, + .width =3D 3, + }, + [VCAP_AF_MPLS_MEP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 193, + .width =3D 1, + }, + [VCAP_AF_MPLS_MIP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 194, + .width =3D 1, + }, + [VCAP_AF_MPLS_OAM_FLAVOR] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 195, + .width =3D 1, + }, + [VCAP_AF_MPLS_IP_CTRL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 196, + .width =3D 1, + }, + [VCAP_AF_CUSTOM_ACE_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 197, + .width =3D 5, + }, + [VCAP_AF_CUSTOM_ACE_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 202, + .width =3D 2, + }, + [VCAP_AF_PAG_OVERRIDE_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 204, + .width =3D 8, + }, + [VCAP_AF_PAG_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 212, + .width =3D 8, + }, + [VCAP_AF_S2_KEY_SEL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 220, + .width =3D 1, + }, + [VCAP_AF_S2_KEY_SEL_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 221, + .width =3D 6, + }, + [VCAP_AF_INJ_MASQ_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 227, + .width =3D 1, + }, + [VCAP_AF_INJ_MASQ_PORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 228, + .width =3D 7, + }, + [VCAP_AF_LPORT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 235, + .width =3D 1, + }, + [VCAP_AF_INJ_MASQ_LPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 236, + .width =3D 7, + }, + [VCAP_AF_MATCH_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 243, + .width =3D 16, + }, + [VCAP_AF_MATCH_ID_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 259, + .width =3D 16, + }, + [VCAP_AF_PIPELINE_FORCE_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 275, + .width =3D 2, + }, + [VCAP_AF_PIPELINE_ACT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 277, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 278, + .width =3D 5, + }, + [VCAP_AF_NXT_KEY_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 283, + .width =3D 5, + }, + [VCAP_AF_NXT_NORM_W16_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 288, + .width =3D 5, + }, + [VCAP_AF_NXT_OFFSET_FROM_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 293, + .width =3D 2, + }, + [VCAP_AF_NXT_TYPE_AFTER_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 295, + .width =3D 2, + }, + [VCAP_AF_NXT_NORMALIZE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 297, + .width =3D 1, + }, + [VCAP_AF_NXT_IDX_CTRL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 298, + .width =3D 3, + }, + [VCAP_AF_NXT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 301, + .width =3D 12, + }, +}; + +static const struct vcap_field is0_class_reduced_actionfield[] =3D { + [VCAP_AF_TYPE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_COSID_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_COSID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 3, + }, + [VCAP_AF_QOS_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 5, + .width =3D 1, + }, + [VCAP_AF_QOS_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 6, + .width =3D 3, + }, + [VCAP_AF_DP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_AF_DP_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 2, + }, + [VCAP_AF_MAP_LOOKUP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 2, + }, + [VCAP_AF_MAP_KEY] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 3, + }, + [VCAP_AF_CLS_VID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 3, + }, + [VCAP_AF_GVID_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 3, + }, + [VCAP_AF_VID_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 23, + .width =3D 13, + }, + [VCAP_AF_VLAN_POP_CNT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 36, + .width =3D 1, + }, + [VCAP_AF_VLAN_POP_CNT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 37, + .width =3D 2, + }, + [VCAP_AF_VLAN_PUSH_CNT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 39, + .width =3D 1, + }, + [VCAP_AF_VLAN_PUSH_CNT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 40, + .width =3D 2, + }, + [VCAP_AF_TPID_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 42, + .width =3D 2, + }, + [VCAP_AF_VLAN_WAS_TAGGED] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 2, + }, + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 46, + .width =3D 1, + }, + [VCAP_AF_ISDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 47, + .width =3D 12, + }, + [VCAP_AF_FWD_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 59, + .width =3D 1, + }, + [VCAP_AF_CPU_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 60, + .width =3D 1, + }, + [VCAP_AF_CPU_Q] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 61, + .width =3D 3, + }, + [VCAP_AF_MIP_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 64, + .width =3D 2, + }, + [VCAP_AF_OAM_Y1731_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 66, + .width =3D 3, + }, + [VCAP_AF_LPORT_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 69, + .width =3D 1, + }, + [VCAP_AF_INJ_MASQ_LPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 70, + .width =3D 7, + }, + [VCAP_AF_PIPELINE_FORCE_ENA] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 77, + .width =3D 2, + }, + [VCAP_AF_PIPELINE_ACT_SEL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 79, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 80, + .width =3D 5, + }, + [VCAP_AF_NXT_KEY_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 85, + .width =3D 5, + }, + [VCAP_AF_NXT_IDX_CTRL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 90, + .width =3D 3, + }, + [VCAP_AF_NXT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 93, + .width =3D 12, + }, +}; + +static const struct vcap_field is2_base_type_actionfield[] =3D { + [VCAP_AF_IS_INNER_ACL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_FORCE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 5, + }, + [VCAP_AF_HIT_ME_ONCE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 7, + .width =3D 1, + }, + [VCAP_AF_INTR_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 8, + .width =3D 1, + }, + [VCAP_AF_CPU_COPY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_AF_CPU_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 3, + }, + [VCAP_AF_CPU_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_AF_LRN_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_AF_RT_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_AF_POLICE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 16, + .width =3D 1, + }, + [VCAP_AF_POLICE_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 6, + }, + [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_AF_DLB_OFFSET] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 24, + .width =3D 3, + }, + [VCAP_AF_MASK_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 3, + }, + [VCAP_AF_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 30, + .width =3D 68, + }, + [VCAP_AF_RSDX_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 98, + .width =3D 1, + }, + [VCAP_AF_RSDX_VAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 99, + .width =3D 12, + }, + [VCAP_AF_MIRROR_PROBE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 111, + .width =3D 2, + }, + [VCAP_AF_REW_CMD] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 113, + .width =3D 11, + }, + [VCAP_AF_TTL_UPDATE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 124, + .width =3D 1, + }, + [VCAP_AF_SAM_SEQ_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 125, + .width =3D 1, + }, + [VCAP_AF_TCP_UDP_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 126, + .width =3D 1, + }, + [VCAP_AF_TCP_UDP_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 127, + .width =3D 16, + }, + [VCAP_AF_TCP_UDP_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 143, + .width =3D 16, + }, + [VCAP_AF_MATCH_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 159, + .width =3D 16, + }, + [VCAP_AF_MATCH_ID_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 175, + .width =3D 16, + }, + [VCAP_AF_CNT_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 191, + .width =3D 12, + }, + [VCAP_AF_SWAP_MAC_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 203, + .width =3D 1, + }, + [VCAP_AF_ACL_RT_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 204, + .width =3D 4, + }, + [VCAP_AF_ACL_MAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 208, + .width =3D 48, + }, + [VCAP_AF_DMAC_OFFSET_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 256, + .width =3D 1, + }, + [VCAP_AF_PTP_MASTER_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 257, + .width =3D 2, + }, + [VCAP_AF_LOG_MSG_INTERVAL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 259, + .width =3D 4, + }, + [VCAP_AF_SIP_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 263, + .width =3D 5, + }, + [VCAP_AF_RLEG_STAT_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 268, + .width =3D 3, + }, + [VCAP_AF_IGR_ACL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 271, + .width =3D 1, + }, + [VCAP_AF_EGR_ACL_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 272, + .width =3D 1, + }, +}; + +static const struct vcap_field es2_base_type_actionfield[] =3D { + [VCAP_AF_HIT_ME_ONCE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 0, + .width =3D 1, + }, + [VCAP_AF_INTR_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_FWD_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 2, + }, + [VCAP_AF_COPY_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 4, + .width =3D 16, + }, + [VCAP_AF_COPY_PORT_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 7, + }, + [VCAP_AF_MIRROR_PROBE_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 2, + }, + [VCAP_AF_CPU_COPY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 29, + .width =3D 1, + }, + [VCAP_AF_CPU_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 30, + .width =3D 3, + }, + [VCAP_AF_POLICE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 33, + .width =3D 1, + }, + [VCAP_AF_POLICE_REMARK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 34, + .width =3D 1, + }, + [VCAP_AF_POLICE_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 35, + .width =3D 6, + }, + [VCAP_AF_ES2_REW_CMD] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 41, + .width =3D 3, + }, + [VCAP_AF_CNT_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 44, + .width =3D 11, + }, + [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, +}; + +/* actionfield_set */ +static const struct vcap_set is0_actionfield_set[] =3D { + [VCAP_AFS_MLBS] =3D { + .type_id =3D 0, + .sw_per_item =3D 2, + .sw_cnt =3D 6, + }, + [VCAP_AFS_MLBS_REDUCED] =3D { + .type_id =3D 0, + .sw_per_item =3D 1, + .sw_cnt =3D 12, + }, + [VCAP_AFS_CLASSIFICATION] =3D { + .type_id =3D 1, + .sw_per_item =3D 2, + .sw_cnt =3D 6, + }, + [VCAP_AFS_FULL] =3D { + .type_id =3D -1, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, + [VCAP_AFS_CLASS_REDUCED] =3D { + .type_id =3D 1, + .sw_per_item =3D 1, + .sw_cnt =3D 12, + }, +}; + +static const struct vcap_set is2_actionfield_set[] =3D { + [VCAP_AFS_BASE_TYPE] =3D { + .type_id =3D -1, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, +}; + +static const struct vcap_set es2_actionfield_set[] =3D { + [VCAP_AFS_BASE_TYPE] =3D { + .type_id =3D -1, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, +}; + +/* actionfield_set map */ +static const struct vcap_field *is0_actionfield_set_map[] =3D { + [VCAP_AFS_MLBS] =3D is0_mlbs_actionfield, + [VCAP_AFS_MLBS_REDUCED] =3D is0_mlbs_reduced_actionfield, + [VCAP_AFS_CLASSIFICATION] =3D is0_classification_actionfield, + [VCAP_AFS_FULL] =3D is0_full_actionfield, + [VCAP_AFS_CLASS_REDUCED] =3D is0_class_reduced_actionfield, +}; + +static const struct vcap_field *is2_actionfield_set_map[] =3D { + [VCAP_AFS_BASE_TYPE] =3D is2_base_type_actionfield, +}; + +static const struct vcap_field *es2_actionfield_set_map[] =3D { + [VCAP_AFS_BASE_TYPE] =3D es2_base_type_actionfield, +}; + +/* actionfield_set map size */ +static int is0_actionfield_set_map_size[] =3D { + [VCAP_AFS_MLBS] =3D ARRAY_SIZE(is0_mlbs_actionfield), + [VCAP_AFS_MLBS_REDUCED] =3D ARRAY_SIZE(is0_mlbs_reduced_actionfield), + [VCAP_AFS_CLASSIFICATION] =3D ARRAY_SIZE(is0_classification_actionfield), + [VCAP_AFS_FULL] =3D ARRAY_SIZE(is0_full_actionfield), + [VCAP_AFS_CLASS_REDUCED] =3D ARRAY_SIZE(is0_class_reduced_actionfield), +}; + +static int is2_actionfield_set_map_size[] =3D { + [VCAP_AFS_BASE_TYPE] =3D ARRAY_SIZE(is2_base_type_actionfield), +}; + +static int es2_actionfield_set_map_size[] =3D { + [VCAP_AFS_BASE_TYPE] =3D ARRAY_SIZE(es2_base_type_actionfield), +}; + +/* Type Groups */ +static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 5, + .value =3D 16, + }, + { + .offset =3D 52, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 104, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 156, + .width =3D 3, + .value =3D 0, + }, + { + .offset =3D 208, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 260, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 312, + .width =3D 4, + .value =3D 0, + }, + { + .offset =3D 364, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 416, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 468, + .width =3D 3, + .value =3D 0, + }, + { + .offset =3D 520, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 572, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 4, + .value =3D 8, + }, + { + .offset =3D 52, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 104, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 156, + .width =3D 3, + .value =3D 0, + }, + { + .offset =3D 208, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 260, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 52, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 104, + .width =3D 2, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 52, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 312, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 468, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 312, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 468, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 1, + .value =3D 1, + }, + {} +}; + +static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup *is0_keyfield_set_typegroups[] =3D { + [12] =3D is0_x12_keyfield_set_typegroups, + [6] =3D is0_x6_keyfield_set_typegroups, + [3] =3D is0_x3_keyfield_set_typegroups, + [2] =3D is0_x2_keyfield_set_typegroups, + [1] =3D is0_x1_keyfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup *is2_keyfield_set_typegroups[] =3D { + [12] =3D is2_x12_keyfield_set_typegroups, + [6] =3D is2_x6_keyfield_set_typegroups, + [3] =3D is2_x3_keyfield_set_typegroups, + [1] =3D is2_x1_keyfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup *es2_keyfield_set_typegroups[] =3D { + [12] =3D es2_x12_keyfield_set_typegroups, + [6] =3D es2_x6_keyfield_set_typegroups, + [3] =3D es2_x3_keyfield_set_typegroups, + [1] =3D es2_x1_keyfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 110, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 220, + .width =3D 2, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 110, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 1, + .value =3D 1, + }, + {} +}; + +static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 110, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 220, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] =3D= { + {} +}; + +static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 21, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 42, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] =3D= { + {} +}; + +static const struct vcap_typegroup *is0_actionfield_set_typegroups[] =3D { + [3] =3D is0_x3_actionfield_set_typegroups, + [2] =3D is0_x2_actionfield_set_typegroups, + [1] =3D is0_x1_actionfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup *is2_actionfield_set_typegroups[] =3D { + [3] =3D is2_x3_actionfield_set_typegroups, + [1] =3D is2_x1_actionfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup *es2_actionfield_set_typegroups[] =3D { + [3] =3D es2_x3_actionfield_set_typegroups, + [1] =3D es2_x1_actionfield_set_typegroups, + [13] =3D NULL, +}; + +/* Keyfieldset names */ +static const char * const vcap_keyfield_set_names[] =3D { + [VCAP_KFS_NO_VALUE] =3D "(None)", + [VCAP_KFS_ARP] =3D "VCAP_KFS_ARP", + [VCAP_KFS_ETAG] =3D "VCAP_KFS_ETAG", + [VCAP_KFS_IP4_OTHER] =3D "VCAP_KFS_IP4_OTHER", + [VCAP_KFS_IP4_TCP_UDP] =3D "VCAP_KFS_IP4_TCP_UDP", + [VCAP_KFS_IP4_VID] =3D "VCAP_KFS_IP4_VID", + [VCAP_KFS_IP6_STD] =3D "VCAP_KFS_IP6_STD", + [VCAP_KFS_IP6_VID] =3D "VCAP_KFS_IP6_VID", + [VCAP_KFS_IP_7TUPLE] =3D "VCAP_KFS_IP_7TUPLE", + [VCAP_KFS_LL_FULL] =3D "VCAP_KFS_LL_FULL", + [VCAP_KFS_MAC_ETYPE] =3D "VCAP_KFS_MAC_ETYPE", + [VCAP_KFS_MLL] =3D "VCAP_KFS_MLL", + [VCAP_KFS_NORMAL] =3D "VCAP_KFS_NORMAL", + [VCAP_KFS_NORMAL_5TUPLE_IP4] =3D "VCAP_KFS_NORMAL_5TUPLE_IP4= ", + [VCAP_KFS_NORMAL_7TUPLE] =3D "VCAP_KFS_NORMAL_7TUPLE", + [VCAP_KFS_PURE_5TUPLE_IP4] =3D "VCAP_KFS_PURE_5TUPLE_IP4", + [VCAP_KFS_TRI_VID] =3D "VCAP_KFS_TRI_VID", +}; + +/* Actionfieldset names */ +static const char * const vcap_actionfield_set_names[] =3D { + [VCAP_AFS_NO_VALUE] =3D "(None)", + [VCAP_AFS_BASE_TYPE] =3D "VCAP_AFS_BASE_TYPE", + [VCAP_AFS_CLASSIFICATION] =3D "VCAP_AFS_CLASSIFICATION", + [VCAP_AFS_CLASS_REDUCED] =3D "VCAP_AFS_CLASS_REDUCED", + [VCAP_AFS_FULL] =3D "VCAP_AFS_FULL", + [VCAP_AFS_MLBS] =3D "VCAP_AFS_MLBS", + [VCAP_AFS_MLBS_REDUCED] =3D "VCAP_AFS_MLBS_REDUCED", +}; + +/* Keyfield names */ +static const char * const vcap_keyfield_names[] =3D { + [VCAP_KF_NO_VALUE] =3D "(None)", + [VCAP_KF_8021BR_ECID_BASE] =3D "8021BR_ECID_BASE", + [VCAP_KF_8021BR_ECID_EXT] =3D "8021BR_ECID_EXT", + [VCAP_KF_8021BR_E_TAGGED] =3D "8021BR_E_TAGGED", + [VCAP_KF_8021BR_GRP] =3D "8021BR_GRP", + [VCAP_KF_8021BR_IGR_ECID_BASE] =3D "8021BR_IGR_ECID_BASE", + [VCAP_KF_8021BR_IGR_ECID_EXT] =3D "8021BR_IGR_ECID_EXT", + [VCAP_KF_8021Q_DEI0] =3D "8021Q_DEI0", + [VCAP_KF_8021Q_DEI1] =3D "8021Q_DEI1", + [VCAP_KF_8021Q_DEI2] =3D "8021Q_DEI2", + [VCAP_KF_8021Q_DEI_CLS] =3D "8021Q_DEI_CLS", + [VCAP_KF_8021Q_PCP0] =3D "8021Q_PCP0", + [VCAP_KF_8021Q_PCP1] =3D "8021Q_PCP1", + [VCAP_KF_8021Q_PCP2] =3D "8021Q_PCP2", + [VCAP_KF_8021Q_PCP_CLS] =3D "8021Q_PCP_CLS", + [VCAP_KF_8021Q_TPID0] =3D "8021Q_TPID0", + [VCAP_KF_8021Q_TPID1] =3D "8021Q_TPID1", + [VCAP_KF_8021Q_TPID2] =3D "8021Q_TPID2", + [VCAP_KF_8021Q_VID0] =3D "8021Q_VID0", + [VCAP_KF_8021Q_VID1] =3D "8021Q_VID1", + [VCAP_KF_8021Q_VID2] =3D "8021Q_VID2", + [VCAP_KF_8021Q_VID_CLS] =3D "8021Q_VID_CLS", + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D "8021Q_VLAN_TAGGED_IS", + [VCAP_KF_8021Q_VLAN_TAGS] =3D "8021Q_VLAN_TAGS", + [VCAP_KF_ACL_GRP_ID] =3D "ACL_GRP_ID", + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D "ARP_ADDR_SPACE_OK_IS", + [VCAP_KF_ARP_LEN_OK_IS] =3D "ARP_LEN_OK_IS", + [VCAP_KF_ARP_OPCODE] =3D "ARP_OPCODE", + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D "ARP_OPCODE_UNKNOWN_IS", + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D "ARP_PROTO_SPACE_OK_IS", + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D "ARP_SENDER_MATCH_IS", + [VCAP_KF_ARP_TGT_MATCH_IS] =3D "ARP_TGT_MATCH_IS", + [VCAP_KF_COSID_CLS] =3D "COSID_CLS", + [VCAP_KF_DST_ENTRY] =3D "DST_ENTRY", + [VCAP_KF_ES0_ISDX_KEY_ENA] =3D "ES0_ISDX_KEY_ENA", + [VCAP_KF_ETYPE] =3D "ETYPE", + [VCAP_KF_ETYPE_LEN_IS] =3D "ETYPE_LEN_IS", + [VCAP_KF_ETYPE_MPLS] =3D "ETYPE_MPLS", + [VCAP_KF_IF_EGR_PORT_MASK] =3D "IF_EGR_PORT_MASK", + [VCAP_KF_IF_EGR_PORT_MASK_RNG] =3D "IF_EGR_PORT_MASK_RNG", + [VCAP_KF_IF_IGR_PORT] =3D "IF_IGR_PORT", + [VCAP_KF_IF_IGR_PORT_MASK] =3D "IF_IGR_PORT_MASK", + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D "IF_IGR_PORT_MASK_L3", + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D "IF_IGR_PORT_MASK_RNG", + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D "IF_IGR_PORT_MASK_SEL", + [VCAP_KF_IF_IGR_PORT_SEL] =3D "IF_IGR_PORT_SEL", + [VCAP_KF_IP4_IS] =3D "IP4_IS", + [VCAP_KF_IP_MC_IS] =3D "IP_MC_IS", + [VCAP_KF_IP_PAYLOAD_5TUPLE] =3D "IP_PAYLOAD_5TUPLE", + [VCAP_KF_IP_SNAP_IS] =3D "IP_SNAP_IS", + [VCAP_KF_ISDX_CLS] =3D "ISDX_CLS", + [VCAP_KF_ISDX_GT0_IS] =3D "ISDX_GT0_IS", + [VCAP_KF_L2_BC_IS] =3D "L2_BC_IS", + [VCAP_KF_L2_DMAC] =3D "L2_DMAC", + [VCAP_KF_L2_FWD_IS] =3D "L2_FWD_IS", + [VCAP_KF_L2_MC_IS] =3D "L2_MC_IS", + [VCAP_KF_L2_PAYLOAD_ETYPE] =3D "L2_PAYLOAD_ETYPE", + [VCAP_KF_L2_SMAC] =3D "L2_SMAC", + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D "L3_DIP_EQ_SIP_IS", + [VCAP_KF_L3_DMAC_DIP_MATCH] =3D "L3_DMAC_DIP_MATCH", + [VCAP_KF_L3_DPL_CLS] =3D "L3_DPL_CLS", + [VCAP_KF_L3_DSCP] =3D "L3_DSCP", + [VCAP_KF_L3_DST_IS] =3D "L3_DST_IS", + [VCAP_KF_L3_FRAGMENT_TYPE] =3D "L3_FRAGMENT_TYPE", + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D "L3_FRAG_INVLD_L4_LEN", + [VCAP_KF_L3_IP4_DIP] =3D "L3_IP4_DIP", + [VCAP_KF_L3_IP4_SIP] =3D "L3_IP4_SIP", + [VCAP_KF_L3_IP6_DIP] =3D "L3_IP6_DIP", + [VCAP_KF_L3_IP6_SIP] =3D "L3_IP6_SIP", + [VCAP_KF_L3_IP_PROTO] =3D "L3_IP_PROTO", + [VCAP_KF_L3_OPTIONS_IS] =3D "L3_OPTIONS_IS", + [VCAP_KF_L3_PAYLOAD] =3D "L3_PAYLOAD", + [VCAP_KF_L3_RT_IS] =3D "L3_RT_IS", + [VCAP_KF_L3_SMAC_SIP_MATCH] =3D "L3_SMAC_SIP_MATCH", + [VCAP_KF_L3_TOS] =3D "L3_TOS", + [VCAP_KF_L3_TTL_GT0] =3D "L3_TTL_GT0", + [VCAP_KF_L4_ACK] =3D "L4_ACK", + [VCAP_KF_L4_DPORT] =3D "L4_DPORT", + [VCAP_KF_L4_FIN] =3D "L4_FIN", + [VCAP_KF_L4_PAYLOAD] =3D "L4_PAYLOAD", + [VCAP_KF_L4_PSH] =3D "L4_PSH", + [VCAP_KF_L4_RNG] =3D "L4_RNG", + [VCAP_KF_L4_RST] =3D "L4_RST", + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D "L4_SEQUENCE_EQ0_IS", + [VCAP_KF_L4_SPORT] =3D "L4_SPORT", + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D "L4_SPORT_EQ_DPORT_IS", + [VCAP_KF_L4_SYN] =3D "L4_SYN", + [VCAP_KF_L4_URG] =3D "L4_URG", + [VCAP_KF_LOOKUP_FIRST_IS] =3D "LOOKUP_FIRST_IS", + [VCAP_KF_LOOKUP_GEN_IDX] =3D "LOOKUP_GEN_IDX", + [VCAP_KF_LOOKUP_GEN_IDX_SEL] =3D "LOOKUP_GEN_IDX_SEL", + [VCAP_KF_LOOKUP_PAG] =3D "LOOKUP_PAG", + [VCAP_KF_MIRROR_ENA] =3D "MIRROR_ENA", + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D "OAM_CCM_CNTS_EQ0", + [VCAP_KF_OAM_MEL_FLAGS] =3D "OAM_MEL_FLAGS", + [VCAP_KF_OAM_Y1731_IS] =3D "OAM_Y1731_IS", + [VCAP_KF_PROT_ACTIVE] =3D "PROT_ACTIVE", + [VCAP_KF_TCP_IS] =3D "TCP_IS", + [VCAP_KF_TCP_UDP_IS] =3D "TCP_UDP_IS", + [VCAP_KF_TYPE] =3D "TYPE", +}; + +/* Actionfield names */ +static const char * const vcap_actionfield_names[] =3D { + [VCAP_AF_NO_VALUE] =3D "(None)", + [VCAP_AF_ACL_MAC] =3D "ACL_MAC", + [VCAP_AF_ACL_RT_MODE] =3D "ACL_RT_MODE", + [VCAP_AF_CLS_VID_SEL] =3D "CLS_VID_SEL", + [VCAP_AF_CNT_ID] =3D "CNT_ID", + [VCAP_AF_COPY_PORT_NUM] =3D "COPY_PORT_NUM", + [VCAP_AF_COPY_QUEUE_NUM] =3D "COPY_QUEUE_NUM", + [VCAP_AF_COSID_ENA] =3D "COSID_ENA", + [VCAP_AF_COSID_VAL] =3D "COSID_VAL", + [VCAP_AF_CPU_COPY_ENA] =3D "CPU_COPY_ENA", + [VCAP_AF_CPU_DIS] =3D "CPU_DIS", + [VCAP_AF_CPU_ENA] =3D "CPU_ENA", + [VCAP_AF_CPU_Q] =3D "CPU_Q", + [VCAP_AF_CPU_QUEUE_NUM] =3D "CPU_QUEUE_NUM", + [VCAP_AF_CUSTOM_ACE_ENA] =3D "CUSTOM_ACE_ENA", + [VCAP_AF_CUSTOM_ACE_OFFSET] =3D "CUSTOM_ACE_OFFSET", + [VCAP_AF_DEI_ENA] =3D "DEI_ENA", + [VCAP_AF_DEI_VAL] =3D "DEI_VAL", + [VCAP_AF_DLB_OFFSET] =3D "DLB_OFFSET", + [VCAP_AF_DMAC_OFFSET_ENA] =3D "DMAC_OFFSET_ENA", + [VCAP_AF_DP_ENA] =3D "DP_ENA", + [VCAP_AF_DP_VAL] =3D "DP_VAL", + [VCAP_AF_DSCP_ENA] =3D "DSCP_ENA", + [VCAP_AF_DSCP_VAL] =3D "DSCP_VAL", + [VCAP_AF_EGR_ACL_ENA] =3D "EGR_ACL_ENA", + [VCAP_AF_ES2_REW_CMD] =3D "ES2_REW_CMD", + [VCAP_AF_FWD_DIS] =3D "FWD_DIS", + [VCAP_AF_FWD_MODE] =3D "FWD_MODE", + [VCAP_AF_FWD_TYPE] =3D "FWD_TYPE", + [VCAP_AF_GVID_ADD_REPLACE_SEL] =3D "GVID_ADD_REPLACE_SEL", + [VCAP_AF_HIT_ME_ONCE] =3D "HIT_ME_ONCE", + [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D "IGNORE_PIPELINE_CTRL", + [VCAP_AF_IGR_ACL_ENA] =3D "IGR_ACL_ENA", + [VCAP_AF_INJ_MASQ_ENA] =3D "INJ_MASQ_ENA", + [VCAP_AF_INJ_MASQ_LPORT] =3D "INJ_MASQ_LPORT", + [VCAP_AF_INJ_MASQ_PORT] =3D "INJ_MASQ_PORT", + [VCAP_AF_INTR_ENA] =3D "INTR_ENA", + [VCAP_AF_ISDX_ADD_REPLACE_SEL] =3D "ISDX_ADD_REPLACE_SEL", + [VCAP_AF_ISDX_VAL] =3D "ISDX_VAL", + [VCAP_AF_IS_INNER_ACL] =3D "IS_INNER_ACL", + [VCAP_AF_L3_MAC_UPDATE_DIS] =3D "L3_MAC_UPDATE_DIS", + [VCAP_AF_LOG_MSG_INTERVAL] =3D "LOG_MSG_INTERVAL", + [VCAP_AF_LPM_AFFIX_ENA] =3D "LPM_AFFIX_ENA", + [VCAP_AF_LPM_AFFIX_VAL] =3D "LPM_AFFIX_VAL", + [VCAP_AF_LPORT_ENA] =3D "LPORT_ENA", + [VCAP_AF_LRN_DIS] =3D "LRN_DIS", + [VCAP_AF_MAP_IDX] =3D "MAP_IDX", + [VCAP_AF_MAP_KEY] =3D "MAP_KEY", + [VCAP_AF_MAP_LOOKUP_SEL] =3D "MAP_LOOKUP_SEL", + [VCAP_AF_MASK_MODE] =3D "MASK_MODE", + [VCAP_AF_MATCH_ID] =3D "MATCH_ID", + [VCAP_AF_MATCH_ID_MASK] =3D "MATCH_ID_MASK", + [VCAP_AF_MIP_SEL] =3D "MIP_SEL", + [VCAP_AF_MIRROR_PROBE] =3D "MIRROR_PROBE", + [VCAP_AF_MIRROR_PROBE_ID] =3D "MIRROR_PROBE_ID", + [VCAP_AF_MPLS_IP_CTRL_ENA] =3D "MPLS_IP_CTRL_ENA", + [VCAP_AF_MPLS_MEP_ENA] =3D "MPLS_MEP_ENA", + [VCAP_AF_MPLS_MIP_ENA] =3D "MPLS_MIP_ENA", + [VCAP_AF_MPLS_OAM_FLAVOR] =3D "MPLS_OAM_FLAVOR", + [VCAP_AF_MPLS_OAM_TYPE] =3D "MPLS_OAM_TYPE", + [VCAP_AF_NUM_VLD_LABELS] =3D "NUM_VLD_LABELS", + [VCAP_AF_NXT_IDX] =3D "NXT_IDX", + [VCAP_AF_NXT_IDX_CTRL] =3D "NXT_IDX_CTRL", + [VCAP_AF_NXT_KEY_TYPE] =3D "NXT_KEY_TYPE", + [VCAP_AF_NXT_NORMALIZE] =3D "NXT_NORMALIZE", + [VCAP_AF_NXT_NORM_W16_OFFSET] =3D "NXT_NORM_W16_OFFSET", + [VCAP_AF_NXT_NORM_W32_OFFSET] =3D "NXT_NORM_W32_OFFSET", + [VCAP_AF_NXT_OFFSET_FROM_TYPE] =3D "NXT_OFFSET_FROM_TYPE", + [VCAP_AF_NXT_TYPE_AFTER_OFFSET] =3D "NXT_TYPE_AFTER_OFFSET", + [VCAP_AF_OAM_IP_BFD_ENA] =3D "OAM_IP_BFD_ENA", + [VCAP_AF_OAM_TWAMP_ENA] =3D "OAM_TWAMP_ENA", + [VCAP_AF_OAM_Y1731_SEL] =3D "OAM_Y1731_SEL", + [VCAP_AF_PAG_OVERRIDE_MASK] =3D "PAG_OVERRIDE_MASK", + [VCAP_AF_PAG_VAL] =3D "PAG_VAL", + [VCAP_AF_PCP_ENA] =3D "PCP_ENA", + [VCAP_AF_PCP_VAL] =3D "PCP_VAL", + [VCAP_AF_PIPELINE_ACT_SEL] =3D "PIPELINE_ACT_SEL", + [VCAP_AF_PIPELINE_FORCE_ENA] =3D "PIPELINE_FORCE_ENA", + [VCAP_AF_PIPELINE_PT] =3D "PIPELINE_PT", + [VCAP_AF_PIPELINE_PT_REDUCED] =3D "PIPELINE_PT_REDUCED", + [VCAP_AF_POLICE_ENA] =3D "POLICE_ENA", + [VCAP_AF_POLICE_IDX] =3D "POLICE_IDX", + [VCAP_AF_POLICE_REMARK] =3D "POLICE_REMARK", + [VCAP_AF_PORT_MASK] =3D "PORT_MASK", + [VCAP_AF_PTP_MASTER_SEL] =3D "PTP_MASTER_SEL", + [VCAP_AF_QOS_ENA] =3D "QOS_ENA", + [VCAP_AF_QOS_VAL] =3D "QOS_VAL", + [VCAP_AF_REW_CMD] =3D "REW_CMD", + [VCAP_AF_RLEG_DMAC_CHK_DIS] =3D "RLEG_DMAC_CHK_DIS", + [VCAP_AF_RLEG_STAT_IDX] =3D "RLEG_STAT_IDX", + [VCAP_AF_RSDX_ENA] =3D "RSDX_ENA", + [VCAP_AF_RSDX_VAL] =3D "RSDX_VAL", + [VCAP_AF_RSVD_LBL_VAL] =3D "RSVD_LBL_VAL", + [VCAP_AF_RT_DIS] =3D "RT_DIS", + [VCAP_AF_RT_SEL] =3D "RT_SEL", + [VCAP_AF_S2_KEY_SEL_ENA] =3D "S2_KEY_SEL_ENA", + [VCAP_AF_S2_KEY_SEL_IDX] =3D "S2_KEY_SEL_IDX", + [VCAP_AF_SAM_SEQ_ENA] =3D "SAM_SEQ_ENA", + [VCAP_AF_SIP_IDX] =3D "SIP_IDX", + [VCAP_AF_SWAP_MAC_ENA] =3D "SWAP_MAC_ENA", + [VCAP_AF_TCP_UDP_DPORT] =3D "TCP_UDP_DPORT", + [VCAP_AF_TCP_UDP_ENA] =3D "TCP_UDP_ENA", + [VCAP_AF_TCP_UDP_SPORT] =3D "TCP_UDP_SPORT", + [VCAP_AF_TC_ENA] =3D "TC_ENA", + [VCAP_AF_TC_LABEL] =3D "TC_LABEL", + [VCAP_AF_TPID_SEL] =3D "TPID_SEL", + [VCAP_AF_TTL_DECR_DIS] =3D "TTL_DECR_DIS", + [VCAP_AF_TTL_ENA] =3D "TTL_ENA", + [VCAP_AF_TTL_LABEL] =3D "TTL_LABEL", + [VCAP_AF_TTL_UPDATE_ENA] =3D "TTL_UPDATE_ENA", + [VCAP_AF_TYPE] =3D "TYPE", + [VCAP_AF_VID_VAL] =3D "VID_VAL", + [VCAP_AF_VLAN_POP_CNT] =3D "VLAN_POP_CNT", + [VCAP_AF_VLAN_POP_CNT_ENA] =3D "VLAN_POP_CNT_ENA", + [VCAP_AF_VLAN_PUSH_CNT] =3D "VLAN_PUSH_CNT", + [VCAP_AF_VLAN_PUSH_CNT_ENA] =3D "VLAN_PUSH_CNT_ENA", + [VCAP_AF_VLAN_WAS_TAGGED] =3D "VLAN_WAS_TAGGED", +}; + +/* VCAPs */ +const struct vcap_info kunit_test_vcaps[] =3D { + [VCAP_TYPE_IS0] =3D { + .name =3D "is0", + .rows =3D 1024, + .sw_count =3D 12, + .sw_width =3D 52, + .sticky_width =3D 1, + .act_width =3D 110, + .default_cnt =3D 140, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D is0_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(is0_keyfield_set), + .actionfield_set =3D is0_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(is0_actionfield_set), + .keyfield_set_map =3D is0_keyfield_set_map, + .keyfield_set_map_size =3D is0_keyfield_set_map_size, + .actionfield_set_map =3D is0_actionfield_set_map, + .actionfield_set_map_size =3D is0_actionfield_set_map_size, + .keyfield_set_typegroups =3D is0_keyfield_set_typegroups, + .actionfield_set_typegroups =3D is0_actionfield_set_typegroups, + }, + [VCAP_TYPE_IS2] =3D { + .name =3D "is2", + .rows =3D 256, + .sw_count =3D 12, + .sw_width =3D 52, + .sticky_width =3D 1, + .act_width =3D 110, + .default_cnt =3D 73, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D is2_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(is2_keyfield_set), + .actionfield_set =3D is2_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(is2_actionfield_set), + .keyfield_set_map =3D is2_keyfield_set_map, + .keyfield_set_map_size =3D is2_keyfield_set_map_size, + .actionfield_set_map =3D is2_actionfield_set_map, + .actionfield_set_map_size =3D is2_actionfield_set_map_size, + .keyfield_set_typegroups =3D is2_keyfield_set_typegroups, + .actionfield_set_typegroups =3D is2_actionfield_set_typegroups, + }, + [VCAP_TYPE_ES2] =3D { + .name =3D "es2", + .rows =3D 1024, + .sw_count =3D 12, + .sw_width =3D 52, + .sticky_width =3D 1, + .act_width =3D 21, + .default_cnt =3D 74, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D es2_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(es2_keyfield_set), + .actionfield_set =3D es2_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(es2_actionfield_set), + .keyfield_set_map =3D es2_keyfield_set_map, + .keyfield_set_map_size =3D es2_keyfield_set_map_size, + .actionfield_set_map =3D es2_actionfield_set_map, + .actionfield_set_map_size =3D es2_actionfield_set_map_size, + .keyfield_set_typegroups =3D es2_keyfield_set_typegroups, + .actionfield_set_typegroups =3D es2_actionfield_set_typegroups, + }, +}; + +const struct vcap_statistics kunit_test_vcap_stats =3D { + .name =3D "kunit_test", + .count =3D 3, + .keyfield_set_names =3D vcap_keyfield_set_names, + .actionfield_set_names =3D vcap_actionfield_set_names, + .keyfield_names =3D vcap_keyfield_names, + .actionfield_names =3D vcap_actionfield_names, +}; diff --git a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.h b/drive= rs/net/ethernet/microchip/vcap/vcap_model_kunit.h new file mode 100644 index 000000000000..b5a74f0eef9b --- /dev/null +++ b/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. + * Microchip VCAP test model interface for kunit testing + */ + +#ifndef __VCAP_MODEL_KUNIT_H__ +#define __VCAP_MODEL_KUNIT_H__ +extern const struct vcap_info kunit_test_vcaps[]; +extern const struct vcap_statistics kunit_test_vcap_stats; +#endif /* __VCAP_MODEL_KUNIT_H__ */ --=20 2.38.1