From nobody Thu Oct 2 21:59:32 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6353C4332F for ; Thu, 20 Oct 2022 13:10:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230375AbiJTNKH (ORCPT ); Thu, 20 Oct 2022 09:10:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230346AbiJTNJ2 (ORCPT ); Thu, 20 Oct 2022 09:09:28 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36F6EB5; Thu, 20 Oct 2022 06:09:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1666271359; x=1697807359; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZYVJSZg23O9xPWkXhFps5NRNrCF8doHHdLhdjU/6sPk=; b=EX+TBhsMi5eBMVtLpL7oQcmgb7U0OuTtLsrNxVK2WYNH9BiiMgaP6RWK XLn4qubMVokP4t3+I1+c8EMbWb1gb8SKyxvwRONZvfsowO8KwzOmr3xrH E9PqKE3blKHQK3kRhg0wj+LAs/FmhqKQHpnx9S41yLt7yCFzFLdLtXtY8 4E3pnT1uIu9tUlzG23U+Sfz5holxKBH5ye+k9mofmYhAP35XYuN/C9lUb 7TIIGjnw+wDddzaMP4BQy5SkiRH1irxZYX6PzKNAMlgcukyj3KQdEqhtT MxFL2+wQrcTMkR4mGCbBuROhzkV+zFtZ056ZNre4MOYG+15YmCqer3f9R g==; X-IronPort-AV: E=Sophos;i="5.95,198,1661842800"; d="scan'208";a="119581789" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Oct 2022 06:09:17 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 20 Oct 2022 06:09:17 -0700 Received: from den-dk-m31857.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 20 Oct 2022 06:09:14 -0700 From: Steen Hegelund To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni CC: Steen Hegelund , , Randy Dunlap , "Casper Andersson" , Russell King , Wan Jiabing , "Nathan Huckleberry" , , , Subject: [PATCH net-next v3 2/9] net: microchip: sparx5: Adding IS2 VCAP model to VCAP API Date: Thu, 20 Oct 2022 15:08:57 +0200 Message-ID: <20221020130904.1215072-3-steen.hegelund@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221020130904.1215072-1-steen.hegelund@microchip.com> References: <20221020130904.1215072-1-steen.hegelund@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This provides the Sparx5 Ingress Stage 2 (IS2) model and adds it to the VCAP control instance that will be provided to the VCAP API. The Sparx5 IS2 C code model is generated from the Sparx5 RTL design model. Signed-off-by: Steen Hegelund --- .../net/ethernet/microchip/sparx5/Makefile | 2 +- .../microchip/sparx5/sparx5_vcap_ag_api.c | 1351 +++++++++++++++++ .../microchip/sparx5/sparx5_vcap_ag_api.h | 18 + .../microchip/sparx5/sparx5_vcap_impl.c | 4 + 4 files changed, 1374 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_ap= i.c create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_ap= i.h diff --git a/drivers/net/ethernet/microchip/sparx5/Makefile b/drivers/net/e= thernet/microchip/sparx5/Makefile index aa4dadb8a25d..b9c6831c2d92 100644 --- a/drivers/net/ethernet/microchip/sparx5/Makefile +++ b/drivers/net/ethernet/microchip/sparx5/Makefile @@ -9,7 +9,7 @@ sparx5-switch-y :=3D sparx5_main.o sparx5_packet.o \ sparx5_netdev.o sparx5_phylink.o sparx5_port.o sparx5_mactable.o sparx5_v= lan.o \ sparx5_switchdev.o sparx5_calendar.o sparx5_ethtool.o sparx5_fdma.o \ sparx5_ptp.o sparx5_pgid.o sparx5_tc.o sparx5_qos.o \ - sparx5_vcap_impl.o + sparx5_vcap_impl.o sparx5_vcap_ag_api.o =20 # Provide include files ccflags-y +=3D -I$(srctree)/drivers/net/ethernet/microchip/vcap diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c b/d= rivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c new file mode 100644 index 000000000000..1bd987c664e8 --- /dev/null +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c @@ -0,0 +1,1351 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. + * Microchip VCAP API + */ + +/* This file is autogenerated by cml-utils 2022-10-13 10:04:41 +0200. + * Commit ID: fd7cafd175899f0672c73afb3a30fc872500ae86 + */ + +#include +#include + +#include "vcap_api.h" +#include "sparx5_vcap_ag_api.h" + +/* keyfields */ +static const struct vcap_field is2_mac_etype_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 90, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 138, + .width =3D 48, + }, + [VCAP_KF_ETYPE_LEN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 186, + .width =3D 1, + }, + [VCAP_KF_ETYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 187, + .width =3D 16, + }, + [VCAP_KF_L2_PAYLOAD_ETYPE] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 203, + .width =3D 64, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 267, + .width =3D 16, + }, + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 283, + .width =3D 1, + }, + [VCAP_KF_OAM_Y1731_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 284, + .width =3D 1, + }, +}; + +static const struct vcap_field is2_arp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 86, + .width =3D 48, + }, + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 134, + .width =3D 1, + }, + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 135, + .width =3D 1, + }, + [VCAP_KF_ARP_LEN_OK_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 136, + .width =3D 1, + }, + [VCAP_KF_ARP_TGT_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 137, + .width =3D 1, + }, + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 138, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 139, + .width =3D 1, + }, + [VCAP_KF_ARP_OPCODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 140, + .width =3D 2, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 142, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 174, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 206, + .width =3D 1, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 207, + .width =3D 16, + }, +}; + +static const struct vcap_field is2_ip4_tcp_udp_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 96, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 104, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 136, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 168, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 169, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 170, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 186, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 202, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 219, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 220, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 221, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 222, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 223, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 224, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 225, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 226, + .width =3D 64, + }, +}; + +static const struct vcap_field is2_ip4_other_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 89, + .width =3D 1, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_L3_FRAGMENT_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 91, + .width =3D 2, + }, + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 93, + .width =3D 1, + }, + [VCAP_KF_L3_OPTIONS_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 94, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 95, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 96, + .width =3D 8, + }, + [VCAP_KF_L3_IP4_DIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 104, + .width =3D 32, + }, + [VCAP_KF_L3_IP4_SIP] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 136, + .width =3D 32, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 168, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 169, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 177, + .width =3D 16, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U112, + .offset =3D 193, + .width =3D 96, + }, +}; + +static const struct vcap_field is2_ip6_std_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 4, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 4, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 5, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 13, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 14, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 18, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 20, + .width =3D 32, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 52, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 53, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 54, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 55, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 56, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 68, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 81, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 82, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 88, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 90, + .width =3D 1, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 91, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 219, + .width =3D 1, + }, + [VCAP_KF_L3_IP_PROTO] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 220, + .width =3D 8, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 228, + .width =3D 16, + }, + [VCAP_KF_L3_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 244, + .width =3D 40, + }, +}; + +static const struct vcap_field is2_ip_7tuple_keyfield[] =3D { + [VCAP_KF_TYPE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 0, + .width =3D 2, + }, + [VCAP_KF_LOOKUP_FIRST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 2, + .width =3D 1, + }, + [VCAP_KF_LOOKUP_PAG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 3, + .width =3D 8, + }, + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 11, + .width =3D 1, + }, + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 12, + .width =3D 4, + }, + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 16, + .width =3D 2, + }, + [VCAP_KF_IF_IGR_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 18, + .width =3D 65, + }, + [VCAP_KF_L2_MC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 83, + .width =3D 1, + }, + [VCAP_KF_L2_BC_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 84, + .width =3D 1, + }, + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 85, + .width =3D 1, + }, + [VCAP_KF_ISDX_GT0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 86, + .width =3D 1, + }, + [VCAP_KF_ISDX_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 87, + .width =3D 12, + }, + [VCAP_KF_8021Q_VID_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 99, + .width =3D 13, + }, + [VCAP_KF_8021Q_DEI_CLS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 112, + .width =3D 1, + }, + [VCAP_KF_8021Q_PCP_CLS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 113, + .width =3D 3, + }, + [VCAP_KF_L2_FWD_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 116, + .width =3D 1, + }, + [VCAP_KF_L3_RT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 119, + .width =3D 1, + }, + [VCAP_KF_L3_DST_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 120, + .width =3D 1, + }, + [VCAP_KF_L2_DMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 121, + .width =3D 48, + }, + [VCAP_KF_L2_SMAC] =3D { + .type =3D VCAP_FIELD_U48, + .offset =3D 169, + .width =3D 48, + }, + [VCAP_KF_IP4_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 217, + .width =3D 1, + }, + [VCAP_KF_L3_TTL_GT0] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 218, + .width =3D 1, + }, + [VCAP_KF_L3_TOS] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 219, + .width =3D 8, + }, + [VCAP_KF_L3_IP6_DIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 227, + .width =3D 128, + }, + [VCAP_KF_L3_IP6_SIP] =3D { + .type =3D VCAP_FIELD_U128, + .offset =3D 355, + .width =3D 128, + }, + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 483, + .width =3D 1, + }, + [VCAP_KF_TCP_UDP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 484, + .width =3D 1, + }, + [VCAP_KF_TCP_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 485, + .width =3D 1, + }, + [VCAP_KF_L4_DPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 486, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 502, + .width =3D 16, + }, + [VCAP_KF_L4_RNG] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 518, + .width =3D 16, + }, + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 534, + .width =3D 1, + }, + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 535, + .width =3D 1, + }, + [VCAP_KF_L4_FIN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 536, + .width =3D 1, + }, + [VCAP_KF_L4_SYN] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 537, + .width =3D 1, + }, + [VCAP_KF_L4_RST] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 538, + .width =3D 1, + }, + [VCAP_KF_L4_PSH] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 539, + .width =3D 1, + }, + [VCAP_KF_L4_ACK] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 540, + .width =3D 1, + }, + [VCAP_KF_L4_URG] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 541, + .width =3D 1, + }, + [VCAP_KF_L4_PAYLOAD] =3D { + .type =3D VCAP_FIELD_U64, + .offset =3D 542, + .width =3D 64, + }, +}; + +/* keyfield_set */ +static const struct vcap_set is2_keyfield_set[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D { + .type_id =3D 0, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_ARP] =3D { + .type_id =3D 3, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_TCP_UDP] =3D { + .type_id =3D 4, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP4_OTHER] =3D { + .type_id =3D 5, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP6_STD] =3D { + .type_id =3D 6, + .sw_per_item =3D 6, + .sw_cnt =3D 2, + }, + [VCAP_KFS_IP_7TUPLE] =3D { + .type_id =3D 1, + .sw_per_item =3D 12, + .sw_cnt =3D 1, + }, +}; + +/* keyfield_set map */ +static const struct vcap_field *is2_keyfield_set_map[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D is2_mac_etype_keyfield, + [VCAP_KFS_ARP] =3D is2_arp_keyfield, + [VCAP_KFS_IP4_TCP_UDP] =3D is2_ip4_tcp_udp_keyfield, + [VCAP_KFS_IP4_OTHER] =3D is2_ip4_other_keyfield, + [VCAP_KFS_IP6_STD] =3D is2_ip6_std_keyfield, + [VCAP_KFS_IP_7TUPLE] =3D is2_ip_7tuple_keyfield, +}; + +/* keyfield_set map sizes */ +static int is2_keyfield_set_map_size[] =3D { + [VCAP_KFS_MAC_ETYPE] =3D ARRAY_SIZE(is2_mac_etype_keyfield), + [VCAP_KFS_ARP] =3D ARRAY_SIZE(is2_arp_keyfield), + [VCAP_KFS_IP4_TCP_UDP] =3D ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), + [VCAP_KFS_IP4_OTHER] =3D ARRAY_SIZE(is2_ip4_other_keyfield), + [VCAP_KFS_IP6_STD] =3D ARRAY_SIZE(is2_ip6_std_keyfield), + [VCAP_KFS_IP_7TUPLE] =3D ARRAY_SIZE(is2_ip_7tuple_keyfield), +}; + +/* actionfields */ +static const struct vcap_field is2_base_type_actionfield[] =3D { + [VCAP_AF_PIPELINE_FORCE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 1, + .width =3D 1, + }, + [VCAP_AF_PIPELINE_PT] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 2, + .width =3D 5, + }, + [VCAP_AF_HIT_ME_ONCE] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 7, + .width =3D 1, + }, + [VCAP_AF_INTR_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 8, + .width =3D 1, + }, + [VCAP_AF_CPU_COPY_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 9, + .width =3D 1, + }, + [VCAP_AF_CPU_QUEUE_NUM] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 10, + .width =3D 3, + }, + [VCAP_AF_LRN_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 14, + .width =3D 1, + }, + [VCAP_AF_RT_DIS] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 15, + .width =3D 1, + }, + [VCAP_AF_POLICE_ENA] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 16, + .width =3D 1, + }, + [VCAP_AF_POLICE_IDX] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 17, + .width =3D 6, + }, + [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D { + .type =3D VCAP_FIELD_BIT, + .offset =3D 23, + .width =3D 1, + }, + [VCAP_AF_MASK_MODE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 27, + .width =3D 3, + }, + [VCAP_AF_PORT_MASK] =3D { + .type =3D VCAP_FIELD_U72, + .offset =3D 30, + .width =3D 68, + }, + [VCAP_AF_MIRROR_PROBE] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 111, + .width =3D 2, + }, + [VCAP_AF_MATCH_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 159, + .width =3D 16, + }, + [VCAP_AF_MATCH_ID_MASK] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 175, + .width =3D 16, + }, + [VCAP_AF_CNT_ID] =3D { + .type =3D VCAP_FIELD_U32, + .offset =3D 191, + .width =3D 12, + }, +}; + +/* actionfield_set */ +static const struct vcap_set is2_actionfield_set[] =3D { + [VCAP_AFS_BASE_TYPE] =3D { + .type_id =3D -1, + .sw_per_item =3D 3, + .sw_cnt =3D 4, + }, +}; + +/* actionfield_set map */ +static const struct vcap_field *is2_actionfield_set_map[] =3D { + [VCAP_AFS_BASE_TYPE] =3D is2_base_type_actionfield, +}; + +/* actionfield_set map size */ +static int is2_actionfield_set_map_size[] =3D { + [VCAP_AFS_BASE_TYPE] =3D ARRAY_SIZE(is2_base_type_actionfield), +}; + +/* Type Groups */ +static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 3, + .value =3D 4, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 312, + .width =3D 2, + .value =3D 0, + }, + { + .offset =3D 468, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] =3D { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 156, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] =3D { + {} +}; + +static const struct vcap_typegroup *is2_keyfield_set_typegroups[] =3D { + [12] =3D is2_x12_keyfield_set_typegroups, + [6] =3D is2_x6_keyfield_set_typegroups, + [3] =3D is2_x3_keyfield_set_typegroups, + [1] =3D is2_x1_keyfield_set_typegroups, + [13] =3D NULL, +}; + +static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] =3D= { + { + .offset =3D 0, + .width =3D 2, + .value =3D 2, + }, + { + .offset =3D 110, + .width =3D 1, + .value =3D 0, + }, + { + .offset =3D 220, + .width =3D 1, + .value =3D 0, + }, + {} +}; + +static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] =3D= { + {} +}; + +static const struct vcap_typegroup *is2_actionfield_set_typegroups[] =3D { + [3] =3D is2_x3_actionfield_set_typegroups, + [1] =3D is2_x1_actionfield_set_typegroups, + [13] =3D NULL, +}; + +/* Keyfieldset names */ +static const char * const vcap_keyfield_set_names[] =3D { + [VCAP_KFS_NO_VALUE] =3D "(None)", + [VCAP_KFS_ARP] =3D "VCAP_KFS_ARP", + [VCAP_KFS_IP4_OTHER] =3D "VCAP_KFS_IP4_OTHER", + [VCAP_KFS_IP4_TCP_UDP] =3D "VCAP_KFS_IP4_TCP_UDP", + [VCAP_KFS_IP6_STD] =3D "VCAP_KFS_IP6_STD", + [VCAP_KFS_IP_7TUPLE] =3D "VCAP_KFS_IP_7TUPLE", + [VCAP_KFS_MAC_ETYPE] =3D "VCAP_KFS_MAC_ETYPE", +}; + +/* Actionfieldset names */ +static const char * const vcap_actionfield_set_names[] =3D { + [VCAP_AFS_NO_VALUE] =3D "(None)", + [VCAP_AFS_BASE_TYPE] =3D "VCAP_AFS_BASE_TYPE", +}; + +/* Keyfield names */ +static const char * const vcap_keyfield_names[] =3D { + [VCAP_KF_NO_VALUE] =3D "(None)", + [VCAP_KF_8021Q_DEI_CLS] =3D "8021Q_DEI_CLS", + [VCAP_KF_8021Q_PCP_CLS] =3D "8021Q_PCP_CLS", + [VCAP_KF_8021Q_VID_CLS] =3D "8021Q_VID_CLS", + [VCAP_KF_8021Q_VLAN_TAGGED_IS] =3D "8021Q_VLAN_TAGGED_IS", + [VCAP_KF_ARP_ADDR_SPACE_OK_IS] =3D "ARP_ADDR_SPACE_OK_IS", + [VCAP_KF_ARP_LEN_OK_IS] =3D "ARP_LEN_OK_IS", + [VCAP_KF_ARP_OPCODE] =3D "ARP_OPCODE", + [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] =3D "ARP_OPCODE_UNKNOWN_IS", + [VCAP_KF_ARP_PROTO_SPACE_OK_IS] =3D "ARP_PROTO_SPACE_OK_IS", + [VCAP_KF_ARP_SENDER_MATCH_IS] =3D "ARP_SENDER_MATCH_IS", + [VCAP_KF_ARP_TGT_MATCH_IS] =3D "ARP_TGT_MATCH_IS", + [VCAP_KF_ETYPE] =3D "ETYPE", + [VCAP_KF_ETYPE_LEN_IS] =3D "ETYPE_LEN_IS", + [VCAP_KF_IF_IGR_PORT_MASK] =3D "IF_IGR_PORT_MASK", + [VCAP_KF_IF_IGR_PORT_MASK_L3] =3D "IF_IGR_PORT_MASK_L3", + [VCAP_KF_IF_IGR_PORT_MASK_RNG] =3D "IF_IGR_PORT_MASK_RNG", + [VCAP_KF_IF_IGR_PORT_MASK_SEL] =3D "IF_IGR_PORT_MASK_SEL", + [VCAP_KF_IP4_IS] =3D "IP4_IS", + [VCAP_KF_ISDX_CLS] =3D "ISDX_CLS", + [VCAP_KF_ISDX_GT0_IS] =3D "ISDX_GT0_IS", + [VCAP_KF_L2_BC_IS] =3D "L2_BC_IS", + [VCAP_KF_L2_DMAC] =3D "L2_DMAC", + [VCAP_KF_L2_FWD_IS] =3D "L2_FWD_IS", + [VCAP_KF_L2_MC_IS] =3D "L2_MC_IS", + [VCAP_KF_L2_PAYLOAD_ETYPE] =3D "L2_PAYLOAD_ETYPE", + [VCAP_KF_L2_SMAC] =3D "L2_SMAC", + [VCAP_KF_L3_DIP_EQ_SIP_IS] =3D "L3_DIP_EQ_SIP_IS", + [VCAP_KF_L3_DST_IS] =3D "L3_DST_IS", + [VCAP_KF_L3_FRAGMENT_TYPE] =3D "L3_FRAGMENT_TYPE", + [VCAP_KF_L3_FRAG_INVLD_L4_LEN] =3D "L3_FRAG_INVLD_L4_LEN", + [VCAP_KF_L3_IP4_DIP] =3D "L3_IP4_DIP", + [VCAP_KF_L3_IP4_SIP] =3D "L3_IP4_SIP", + [VCAP_KF_L3_IP6_DIP] =3D "L3_IP6_DIP", + [VCAP_KF_L3_IP6_SIP] =3D "L3_IP6_SIP", + [VCAP_KF_L3_IP_PROTO] =3D "L3_IP_PROTO", + [VCAP_KF_L3_OPTIONS_IS] =3D "L3_OPTIONS_IS", + [VCAP_KF_L3_PAYLOAD] =3D "L3_PAYLOAD", + [VCAP_KF_L3_RT_IS] =3D "L3_RT_IS", + [VCAP_KF_L3_TOS] =3D "L3_TOS", + [VCAP_KF_L3_TTL_GT0] =3D "L3_TTL_GT0", + [VCAP_KF_L4_ACK] =3D "L4_ACK", + [VCAP_KF_L4_DPORT] =3D "L4_DPORT", + [VCAP_KF_L4_FIN] =3D "L4_FIN", + [VCAP_KF_L4_PAYLOAD] =3D "L4_PAYLOAD", + [VCAP_KF_L4_PSH] =3D "L4_PSH", + [VCAP_KF_L4_RNG] =3D "L4_RNG", + [VCAP_KF_L4_RST] =3D "L4_RST", + [VCAP_KF_L4_SEQUENCE_EQ0_IS] =3D "L4_SEQUENCE_EQ0_IS", + [VCAP_KF_L4_SPORT] =3D "L4_SPORT", + [VCAP_KF_L4_SPORT_EQ_DPORT_IS] =3D "L4_SPORT_EQ_DPORT_IS", + [VCAP_KF_L4_SYN] =3D "L4_SYN", + [VCAP_KF_L4_URG] =3D "L4_URG", + [VCAP_KF_LOOKUP_FIRST_IS] =3D "LOOKUP_FIRST_IS", + [VCAP_KF_LOOKUP_PAG] =3D "LOOKUP_PAG", + [VCAP_KF_OAM_CCM_CNTS_EQ0] =3D "OAM_CCM_CNTS_EQ0", + [VCAP_KF_OAM_Y1731_IS] =3D "OAM_Y1731_IS", + [VCAP_KF_TCP_IS] =3D "TCP_IS", + [VCAP_KF_TCP_UDP_IS] =3D "TCP_UDP_IS", + [VCAP_KF_TYPE] =3D "TYPE", +}; + +/* Actionfield names */ +static const char * const vcap_actionfield_names[] =3D { + [VCAP_AF_NO_VALUE] =3D "(None)", + [VCAP_AF_CNT_ID] =3D "CNT_ID", + [VCAP_AF_CPU_COPY_ENA] =3D "CPU_COPY_ENA", + [VCAP_AF_CPU_QUEUE_NUM] =3D "CPU_QUEUE_NUM", + [VCAP_AF_HIT_ME_ONCE] =3D "HIT_ME_ONCE", + [VCAP_AF_IGNORE_PIPELINE_CTRL] =3D "IGNORE_PIPELINE_CTRL", + [VCAP_AF_INTR_ENA] =3D "INTR_ENA", + [VCAP_AF_LRN_DIS] =3D "LRN_DIS", + [VCAP_AF_MASK_MODE] =3D "MASK_MODE", + [VCAP_AF_MATCH_ID] =3D "MATCH_ID", + [VCAP_AF_MATCH_ID_MASK] =3D "MATCH_ID_MASK", + [VCAP_AF_MIRROR_PROBE] =3D "MIRROR_PROBE", + [VCAP_AF_PIPELINE_FORCE_ENA] =3D "PIPELINE_FORCE_ENA", + [VCAP_AF_PIPELINE_PT] =3D "PIPELINE_PT", + [VCAP_AF_POLICE_ENA] =3D "POLICE_ENA", + [VCAP_AF_POLICE_IDX] =3D "POLICE_IDX", + [VCAP_AF_PORT_MASK] =3D "PORT_MASK", + [VCAP_AF_RT_DIS] =3D "RT_DIS", +}; + +/* VCAPs */ +const struct vcap_info sparx5_vcaps[] =3D { + [VCAP_TYPE_IS2] =3D { + .name =3D "is2", + .rows =3D 256, + .sw_count =3D 12, + .sw_width =3D 52, + .sticky_width =3D 1, + .act_width =3D 110, + .default_cnt =3D 73, + .require_cnt_dis =3D 0, + .version =3D 1, + .keyfield_set =3D is2_keyfield_set, + .keyfield_set_size =3D ARRAY_SIZE(is2_keyfield_set), + .actionfield_set =3D is2_actionfield_set, + .actionfield_set_size =3D ARRAY_SIZE(is2_actionfield_set), + .keyfield_set_map =3D is2_keyfield_set_map, + .keyfield_set_map_size =3D is2_keyfield_set_map_size, + .actionfield_set_map =3D is2_actionfield_set_map, + .actionfield_set_map_size =3D is2_actionfield_set_map_size, + .keyfield_set_typegroups =3D is2_keyfield_set_typegroups, + .actionfield_set_typegroups =3D is2_actionfield_set_typegroups, + }, +}; + +const struct vcap_statistics sparx5_vcap_stats =3D { + .name =3D "sparx5", + .count =3D 1, + .keyfield_set_names =3D vcap_keyfield_set_names, + .actionfield_set_names =3D vcap_actionfield_set_names, + .keyfield_names =3D vcap_keyfield_names, + .actionfield_names =3D vcap_actionfield_names, +}; diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h b/d= rivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h new file mode 100644 index 000000000000..7d106f1276fe --- /dev/null +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries. + * Microchip VCAP API + */ + +/* This file is autogenerated by cml-utils 2022-10-13 10:04:41 +0200. + * Commit ID: fd7cafd175899f0672c73afb3a30fc872500ae86 + */ + +#ifndef __SPARX5_VCAP_AG_API_H__ +#define __SPARX5_VCAP_AG_API_H__ + +/* VCAPs */ +extern const struct vcap_info sparx5_vcaps[]; +extern const struct vcap_statistics sparx5_vcap_stats; + +#endif /* __SPARX5_VCAP_AG_API_H__ */ + diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c b/dri= vers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c index 8df7cba77a28..68f6fed80556 100644 --- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c +++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c @@ -13,6 +13,7 @@ #include "vcap_api.h" #include "sparx5_main_regs.h" #include "sparx5_main.h" +#include "sparx5_vcap_ag_api.h" =20 /* Allocate a vcap control and vcap instances and configure the system */ int sparx5_vcap_init(struct sparx5 *sparx5) @@ -28,6 +29,9 @@ int sparx5_vcap_init(struct sparx5 *sparx5) return -ENOMEM; =20 sparx5->vcap_ctrl =3D ctrl; + /* select the sparx5 VCAP model */ + ctrl->vcaps =3D sparx5_vcaps; + ctrl->stats =3D &sparx5_vcap_stats; =20 return 0; } --=20 2.38.1