From nobody Tue Apr 7 22:16:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23B9CC4332F for ; Thu, 20 Oct 2022 07:59:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231185AbiJTH7P (ORCPT ); Thu, 20 Oct 2022 03:59:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231168AbiJTH7C (ORCPT ); Thu, 20 Oct 2022 03:59:02 -0400 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E71D18027C for ; Thu, 20 Oct 2022 00:59:00 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id 128so18536450pga.1 for ; Thu, 20 Oct 2022 00:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pAsIYw7sZ9pedrVTYHgIfzcW6BaLpjWwdgXvgEmQOaY=; b=KVCqQo/Qymbi41s1GUvHpj3Wa5ZypO8gqStPS/9xn5zgaSL7zarcIcxDhnsDA/Iv6H xDxS2Ox3UAG1mZR376x/ShdVFwZWb1o8wEai1lgskVK8Y2IGL9/Ulx0HVzk8RtyhbKhm QP/grnXg+4nuN2+5lplMkJjPRv6pcSnWZCLkH/y8xE86Y4JaQp9Cijci1o5tTkUDzGPj rZU62/JDjfV98OLvz/x0lhSpy3gj5m3JOcNChEIHA6cpCS4LSCXSz7KKmPPpcsPMgEdl JOAGQSC4At6e1OBUJ0L17wsET+PnN4fPY/XJvBo81AgTiL+SNJb5OfHwaMExuIQ2rZ+/ 2AzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pAsIYw7sZ9pedrVTYHgIfzcW6BaLpjWwdgXvgEmQOaY=; b=7+74mbtNyuRoyBJcpNfNmc6UQCE5DK3vCKfOMYxKvwar5RbwfceQAILkbX1ve+oIzP 6tEwViBTeiCJdv5QS/HkpsL4wB/0SyZbfux0frhMs10/CDa7UIKxTcWURgFbEBrwKdjr Akb3QwyOaIkaDathZ4N7U+23o9LCGWO7pIYjEuCzQga8rpln9N1mTMuT+G35zlH+Zgkv ddn2RZG/6qS7ENl9+LNpEWcfyimv0bDc/PrAZOWda2HL59Bg3dP5FkJkL0NBwFdV9jFH aoKgM+nQx2T8EmBPkMLet7IV6S3Y8Dt4/4UUWrp64HeUoJoSHrlucr5oHPqM1GiihLUF OyVQ== X-Gm-Message-State: ACrzQf2aD3VWOpBTmegn2jb0xd+xBg1Ld5tCyTsurBLkSgN/hpbpc9pn aro/kD5Senl8NYSTpY0CfC1F3w== X-Google-Smtp-Source: AMsMyM7UCFvQaa7jwg80SjAqa1N1TyrjSWdPX8DKXF4Z/drUnTh21rNLOzM1OFg/9Bs2UjVCRigQtQ== X-Received: by 2002:a63:cf4f:0:b0:462:da7a:1ded with SMTP id b15-20020a63cf4f000000b00462da7a1dedmr10543458pgj.605.1666252739916; Thu, 20 Oct 2022 00:58:59 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:58:59 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Andrew Jones , kernel test robot , Anup Patel , Conor Dooley Subject: [PATCH v5 1/4] RISC-V: Fix compilation without RISCV_ISA_ZICBOM Date: Thu, 20 Oct 2022 13:28:43 +0530 Message-Id: <20221020075846.305576-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Andrew Jones riscv_cbom_block_size and riscv_init_cbom_blocksize() should always be available and riscv_init_cbom_blocksize() should always be invoked, even when compiling without RISCV_ISA_ZICBOM enabled. This is because disabling RISCV_ISA_ZICBOM means "don't use zicbom instructions in the kernel" not "pretend there isn't zicbom, even when there is". When zicbom is available, whether the kernel enables its use with RISCV_ISA_ZICBOM or not, KVM will offer it to guests. Ensure we can build KVM and that the block size is initialized even when compiling without RISCV_ISA_ZICBOM. Fixes: 8f7e001e0325 ("RISC-V: Clean up the Zicbom block size probing") Reported-by: kernel test robot Signed-off-by: Andrew Jones Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- arch/riscv/include/asm/cacheflush.h | 8 ------ arch/riscv/mm/cacheflush.c | 38 ++++++++++++++++++++++++++ arch/riscv/mm/dma-noncoherent.c | 41 ----------------------------- 3 files changed, 38 insertions(+), 49 deletions(-) diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/c= acheflush.h index 8a5c246b0a21..f6fbe7042f1c 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -42,16 +42,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); =20 #endif /* CONFIG_SMP */ =20 -/* - * The T-Head CMO errata internally probe the CBOM block size, but otherwi= se - * don't depend on Zicbom. - */ extern unsigned int riscv_cbom_block_size; -#ifdef CONFIG_RISCV_ISA_ZICBOM void riscv_init_cbom_blocksize(void); -#else -static inline void riscv_init_cbom_blocksize(void) { } -#endif =20 #ifdef CONFIG_RISCV_DMA_NONCOHERENT void riscv_noncoherent_supported(void); diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c index 6cb7d96ad9c7..57b40a350420 100644 --- a/arch/riscv/mm/cacheflush.c +++ b/arch/riscv/mm/cacheflush.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive */ =20 +#include #include =20 #ifdef CONFIG_SMP @@ -86,3 +87,40 @@ void flush_icache_pte(pte_t pte) flush_icache_all(); } #endif /* CONFIG_MMU */ + +unsigned int riscv_cbom_block_size; +EXPORT_SYMBOL_GPL(riscv_cbom_block_size); + +void riscv_init_cbom_blocksize(void) +{ + struct device_node *node; + unsigned long cbom_hartid; + u32 val, probed_block_size; + int ret; + + probed_block_size =3D 0; + for_each_of_cpu_node(node) { + unsigned long hartid; + + ret =3D riscv_of_processor_hartid(node, &hartid); + if (ret) + continue; + + /* set block-size for cbom extension if available */ + ret =3D of_property_read_u32(node, "riscv,cbom-block-size", &val); + if (ret) + continue; + + if (!probed_block_size) { + probed_block_size =3D val; + cbom_hartid =3D hartid; + } else { + if (probed_block_size !=3D val) + pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", + cbom_hartid, hartid); + } + } + + if (probed_block_size) + riscv_cbom_block_size =3D probed_block_size; +} diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoheren= t.c index b0add983530a..d919efab6eba 100644 --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -8,13 +8,8 @@ #include #include #include -#include -#include #include =20 -unsigned int riscv_cbom_block_size; -EXPORT_SYMBOL_GPL(riscv_cbom_block_size); - static bool noncoherent_supported; =20 void arch_sync_dma_for_device(phys_addr_t paddr, size_t size, @@ -77,42 +72,6 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base= , u64 size, dev->dma_coherent =3D coherent; } =20 -#ifdef CONFIG_RISCV_ISA_ZICBOM -void riscv_init_cbom_blocksize(void) -{ - struct device_node *node; - unsigned long cbom_hartid; - u32 val, probed_block_size; - int ret; - - probed_block_size =3D 0; - for_each_of_cpu_node(node) { - unsigned long hartid; - - ret =3D riscv_of_processor_hartid(node, &hartid); - if (ret) - continue; - - /* set block-size for cbom extension if available */ - ret =3D of_property_read_u32(node, "riscv,cbom-block-size", &val); - if (ret) - continue; - - if (!probed_block_size) { - probed_block_size =3D val; - cbom_hartid =3D hartid; - } else { - if (probed_block_size !=3D val) - pr_warn("cbom-block-size mismatched between harts %lu and %lu\n", - cbom_hartid, hartid); - } - } - - if (probed_block_size) - riscv_cbom_block_size =3D probed_block_size; -} -#endif - void riscv_noncoherent_supported(void) { WARN(!riscv_cbom_block_size, --=20 2.34.1 From nobody Tue Apr 7 22:16:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2EB51C43217 for ; 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([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:59:03 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v5 2/4] RISC-V: Fix MEMREMAP_WB for systems with Svpbmt Date: Thu, 20 Oct 2022 13:28:44 +0530 Message-Id: <20221020075846.305576-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Currently, the memremap() called with MEMREMAP_WB maps memory using the generic ioremap() function which breaks on system with Svpbmt because memory mapped using _PAGE_IOREMAP page attributes is treated as strongly-ordered non-cacheable IO memory. To address this, we implement RISC-V specific arch_memremap_wb() which maps memory using _PAGE_KERNEL page attributes resulting in write-back cacheable mapping on systems with Svpbmt. Fixes: ff689fd21cb1 ("riscv: add RISC-V Svpbmt extension support") Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/include/asm/io.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 92080a227937..42497d487a17 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -135,4 +135,9 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) =20 #include =20 +#ifdef CONFIG_MMU +#define arch_memremap_wb(addr, size) \ + ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL)) +#endif + #endif /* _ASM_RISCV_IO_H */ --=20 2.34.1 From nobody Tue Apr 7 22:16:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E9E3C433FE for ; Thu, 20 Oct 2022 07:59:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231205AbiJTH7V (ORCPT ); Thu, 20 Oct 2022 03:59:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50464 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231237AbiJTH7J (ORCPT ); Thu, 20 Oct 2022 03:59:09 -0400 Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6883180257 for ; Thu, 20 Oct 2022 00:59:08 -0700 (PDT) Received: by mail-pg1-x536.google.com with SMTP id bh13so18521894pgb.4 for ; Thu, 20 Oct 2022 00:59:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VDJV4ZwRVQLzE0DQMb9i2tBKWni84XeHMbgigRoQK/0=; b=RtIs+Fo57m4OyjqREQ+GmkLa1gtB+nd1wI1cynGPWeyR4VuzuTZWYwxJp3qb38jND+ jXzllqItnzM8dXynZdtd4gBtlQcrTFv3q3wLdb9aYmU1re7J1CS7QNaEBpwC5Es4tMoP 8fhXm+QGwvfvAnRFygQrEktJR97lrpRTNwcBmjOVjVyH0enR9liXz+TuLkEd3jbxNgtS 0Q5pPUbWB2jqGj3mst8Fq1vF9FPWmupAtBR8zOnr4ZeSflblwpcDKp/m4D9umY0Ly4J6 EgHMvrkLGNAoI6X8hUK3eiUWTy+WmHETYpx3tSzPJFfbAnLWn8XU2jYA24Eu1d6/08Ar W+wA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VDJV4ZwRVQLzE0DQMb9i2tBKWni84XeHMbgigRoQK/0=; b=TgBb+aYLda1w0W6DSjRmXPwRaS3GkOmQNf5qF1X1MWZDoKq6q0hp7AIlB7GojRt/xw eIzIAcxdorCTQUK5sO4VTjuwg8RF5H1uRIol+Eg5J2kBTkhVLli6lBLJIv/fsiryjJrd lHE6FhWphm/oGsXGZiBuumvn0MAeO1jsziBsyPlfQZGU0fe3OsR+DYNGbicJlI4Mp4vL Hp+V1dTSTgqV+ZkyjVUQh0uTkQ5XHK2e7OziSSi7PH8Rsz5msf9dwEa23oueSYKBAKi5 fq6zxw678VJVm4o41mjrZmtJY4UTWN27Fq8P+Tcw/BcxtTtiN8IA8YZ2MWV2+gIYjWQ8 zs9Q== X-Gm-Message-State: ACrzQf3AJ07GFObNT1ndNcoEgwufJkm6b8DgqAsMUoyUVP4TLn/HpSMI gI9TidAr5KB515a77jfL2/Umig== X-Google-Smtp-Source: AMsMyM4+Y3j2NNCSyJHfzbf9XmZTArI3CBMgBB4JZwGFMWkS1y+U/PGzCotqjnP6BECxn5NkaxBZpA== X-Received: by 2002:a63:2b4b:0:b0:440:2963:5863 with SMTP id r72-20020a632b4b000000b0044029635863mr10501248pgr.28.1666252748070; Thu, 20 Oct 2022 00:59:08 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:59:07 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Mayuresh Chitale Subject: [PATCH v5 3/4] RISC-V: Implement arch specific PMEM APIs Date: Thu, 20 Oct 2022 13:28:45 +0530 Message-Id: <20221020075846.305576-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The NVDIMM PMEM driver expects arch specific APIs for cache maintenance and if arch does not provide these APIs then NVDIMM PMEM driver will always use MEMREMAP_WT to map persistent memory which in-turn maps as UC memory type defined by the RISC-V Svpbmt specification. Now that the Svpbmt and Zicbom support is available in RISC-V kernel, we implement PMEM APIs using ALT_CMO_OP() macros so that the NVDIMM PMEM driver can use MEMREMAP_WB to map persistent memory. Co-developed-by: Mayuresh Chitale Signed-off-by: Mayuresh Chitale Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 1 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/pmem.c | 21 +++++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 arch/riscv/mm/pmem.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6b48a3ae9843..025e2a1b1c60 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -25,6 +25,7 @@ config RISCV select ARCH_HAS_GIGANTIC_PAGE select ARCH_HAS_KCOV select ARCH_HAS_MMIOWB + select ARCH_HAS_PMEM_API select ARCH_HAS_PTE_SPECIAL select ARCH_HAS_SET_DIRECT_MAP if MMU select ARCH_HAS_SET_MEMORY if MMU diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile index d76aabf4b94d..3b368e547f83 100644 --- a/arch/riscv/mm/Makefile +++ b/arch/riscv/mm/Makefile @@ -31,3 +31,4 @@ endif =20 obj-$(CONFIG_DEBUG_VIRTUAL) +=3D physaddr.o obj-$(CONFIG_RISCV_DMA_NONCOHERENT) +=3D dma-noncoherent.o +obj-$(CONFIG_ARCH_HAS_PMEM_API) +=3D pmem.o diff --git a/arch/riscv/mm/pmem.c b/arch/riscv/mm/pmem.c new file mode 100644 index 000000000000..089df92ae876 --- /dev/null +++ b/arch/riscv/mm/pmem.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Ventana Micro Systems Inc. + */ + +#include +#include + +#include + +void arch_wb_cache_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(clean, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_wb_cache_pmem); + +void arch_invalidate_pmem(void *addr, size_t size) +{ + ALT_CMO_OP(inval, addr, size, riscv_cbom_block_size); +} +EXPORT_SYMBOL_GPL(arch_invalidate_pmem); --=20 2.34.1 From nobody Tue Apr 7 22:16:30 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C23AAC433FE for ; Thu, 20 Oct 2022 07:59:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231199AbiJTH70 (ORCPT ); Thu, 20 Oct 2022 03:59:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231158AbiJTH7N (ORCPT ); Thu, 20 Oct 2022 03:59:13 -0400 Received: from mail-pg1-x52a.google.com (mail-pg1-x52a.google.com [IPv6:2607:f8b0:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6FD718027C for ; Thu, 20 Oct 2022 00:59:12 -0700 (PDT) Received: by mail-pg1-x52a.google.com with SMTP id f193so18559306pgc.0 for ; Thu, 20 Oct 2022 00:59:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5TnLW0RVC/l/l6ZpSJGiQ9RS55Sh7Bww2u/zF6eZ2bY=; b=eL/0WYugw3H/1sxFC9WdKuigQo+DLOOuD80Q50Flm9AQs84m3h9nhYf0lLQYFWRd39 DXs4iq9U35DNMud1OLd+16okiAB2eoq7QcO9OSbRglrpg20DSO8trF8j8xmLmCcLLGPC cN3DT63GsaCqDSugUopR1AvikeqYg8gC613t1k9CY7q9hO9lJ8lvKYl8Ek4e6lDvJMlw vPg3fbNz3pUhmLaNqjOoHF5hZZCC/VZeRstJaWGQUmsQd8PNC4hcrRrPGFxTNz1xt4pK Bw1uR/NrBdi2x1QlXQ8AkRO/ok1dsPlcpY1fOB2o0/DwqFlo7APjo4OD+L3+tAq4gC1g HMtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5TnLW0RVC/l/l6ZpSJGiQ9RS55Sh7Bww2u/zF6eZ2bY=; b=WhwFTrE8ftZYt4ogBf4NIcY4ehAP3y9KdJxxEXVVXWbIx6WPeuQNgkTNn1HpXmIuvX +FYu3WIrh/jAvt0smaAu0IOsVHd7UzCp7iTMCklmt5fh+MkDS68U9J8/uqxKMnxMuIOE dhRN+jdQUjM03fIAkvLy52oyKCieJtMGaYlBFU623pRdxz6oiJyIgRvl2iMIXComa6zF diVmFy3YlMXi6TNbjzXdt1bYkC3hDF8f7+UcHlGKjFehfUkusoHEtmROfnU2YlFwo8mm cdzFQk2I6qdgW8u6TuFACiCZpmdWL+u7cN0d0Jw7TnFc404QIiUkfpia4r3ylFrpia/G MK9w== X-Gm-Message-State: ACrzQf1v1+BMm12DyjTxNbW6WhsNKjLUOmBTBu2SIiCZkTY6e88MGRm1 ESIV8yM9hvvjQXDCVkSZBYXHiQ== X-Google-Smtp-Source: AMsMyM5695BW3bf/MyxpS9FPVNImhqrzxiREVKiQzjuNPGrSayyB3orzN/hf7wn69DCszXPk5MNb7w== X-Received: by 2002:a63:ef18:0:b0:439:befc:d89c with SMTP id u24-20020a63ef18000000b00439befcd89cmr10373730pgh.504.1666252752020; Thu, 20 Oct 2022 00:59:12 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.80.23]) by smtp.gmail.com with ESMTPSA id h30-20020aa79f5e000000b0052dfe83e19csm13206438pfr.16.2022.10.20.00.59.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 00:59:11 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley Cc: Atish Patra , Heiko Stuebner , Arnd Bergmann , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v5 4/4] RISC-V: Enable PMEM drivers Date: Thu, 20 Oct 2022 13:28:46 +0530 Message-Id: <20221020075846.305576-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221020075846.305576-1-apatel@ventanamicro.com> References: <20221020075846.305576-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We now have PMEM arch support available in RISC-V kernel so let us enable relevant drivers in defconfig. Signed-off-by: Anup Patel --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 05fd5fcf24f9..462da9f7410d 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -159,6 +159,7 @@ CONFIG_VIRTIO_MMIO=3Dy CONFIG_RPMSG_CHAR=3Dy CONFIG_RPMSG_CTRL=3Dy CONFIG_RPMSG_VIRTIO=3Dy +CONFIG_LIBNVDIMM=3Dy CONFIG_EXT4_FS=3Dy CONFIG_EXT4_FS_POSIX_ACL=3Dy CONFIG_EXT4_FS_SECURITY=3Dy --=20 2.34.1