From nobody Sat Sep 21 11:56:01 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1F1EC4332F for ; Thu, 20 Oct 2022 02:42:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230372AbiJTCmX (ORCPT ); Wed, 19 Oct 2022 22:42:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229731AbiJTCmR (ORCPT ); Wed, 19 Oct 2022 22:42:17 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A05BB18D46A; Wed, 19 Oct 2022 19:42:09 -0700 (PDT) X-UUID: fdbc2e923b3d47649f80acc9c35e4fc8-20221020 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=6XvUd0dwp6H2FgsEGlACEaC7L9K/yg0t2tm8pNN9aVc=; b=Aqh8+CGZjL19In9oo5LVxH5CHki6wMOMANVsKqp+54DKx9LyxLiCUXEnWILn3guuGjIXWi88v3y4picbiPiiPLAHMaAHP1dNkU5nqmKbrp84cLronVJwibukiBLNcyxd+eghuZPY4Ik0P1/PGL+r7iWBn7FLBN8FRaUkdpvSf/k=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:23ff96c0-779d-4eff-9b90-b456905d532e,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.12,REQID:23ff96c0-779d-4eff-9b90-b456905d532e,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:62cd327,CLOUDID:9e8c5ca4-ebb2-41a8-a87c-97702aaf2e20,B ulkID:221020104206TMTQZLMN,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: fdbc2e923b3d47649f80acc9c35e4fc8-20221020 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1229771477; Thu, 20 Oct 2022 10:42:04 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Thu, 20 Oct 2022 10:42:04 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 20 Oct 2022 10:42:03 +0800 From: Biao Huang To: AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , Biao Huang , Subject: [PATCH v3] arm64: dts: mt8195: Add Ethernet controller Date: Thu, 20 Oct 2022 10:41:55 +0800 Message-ID: <20221020024155.24520-2-biao.huang@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221020024155.24520-1-biao.huang@mediatek.com> References: <20221020024155.24520-1-biao.huang@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add Ethernet controller node for mt8195. Signed-off-by: Biao Huang Reviewed-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 88 ++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 88 ++++++++++++++++++++ 2 files changed, 176 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot= /dts/mediatek/mt8195-demo.dts index 4fbd99eb496a..0e8496d837ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -258,6 +258,72 @@ &mt6359_vsram_others_ldo_reg { }; =20 &pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + pins-cc { + pinmux =3D , + , + , + ; + drive-strength =3D ; + }; + pins-rxd { + pinmux =3D , + , + , + ; + }; + pins-mdio { + pinmux =3D , + ; + input-enable; + }; + pins-power { + pinmux =3D , + ; + output-high; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux =3D , + , + , + ; + }; + pins-cc { + pinmux =3D , + , + , + ; + }; + pins-rxd { + pinmux =3D , + , + , + ; + }; + pins-mdio { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + pins-power { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + }; + gpio_keys_pins: gpio-keys-pins { pins { pinmux =3D ; @@ -434,6 +500,28 @@ &xhci0 { status =3D "okay"; }; =20 +ð { + phy-mode =3D"rgmii-rxid"; + phy-handle =3D <ðernet_phy0>; + snps,reset-gpio =3D <&pio 93 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us =3D <0 10000 10000>; + mediatek,tx-delay-ps =3D <2030>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default_pins>; + pinctrl-1 =3D <ð_sleep_pins>; + status =3D "okay"; + + mdio { + compatible =3D "snps,dwmac-mdio"; + #address-cells =3D <1>; + #size-cells =3D <0>; + ethernet_phy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-id001c.c916"; + reg =3D <0x1>; + }; + }; +}; + &xhci1 { vusb33-supply =3D <&mt6359_vusb_ldo_reg>; status =3D "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 905d1a90b406..7efaf92c5ff3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1042,6 +1042,94 @@ spis1: spi@1101e000 { status =3D "disabled"; }; =20 + eth: ethernet@11021000 { + compatible =3D "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; + reg =3D <0 0x11021000 0 0x4000>; + interrupts =3D ; + interrupt-names =3D "macirq"; + clock-names =3D "axi", + "apb", + "mac_cg", + "mac_main", + "ptp_ref", + "rmii_internal"; + clocks =3D <&pericfg_ao CLK_PERI_AO_ETHERNET>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, + <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>, + <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clocks =3D <&topckgen CLK_TOP_SNPS_ETH_250M>, + <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, + <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; + assigned-clock-parents =3D <&topckgen CLK_TOP_ETHPLL_D2>, + <&topckgen CLK_TOP_ETHPLL_D8>, + <&topckgen CLK_TOP_ETHPLL_D10>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_ETHER>; + mediatek,pericfg =3D <&infracfg_ao>; + snps,axi-config =3D <&stmmac_axi_setup>; + snps,mtl-rx-config =3D <&mtl_rx_setup>; + snps,mtl-tx-config =3D <&mtl_tx_setup>; + snps,txpbl =3D <16>; + snps,rxpbl =3D <16>; + snps,clk-csr =3D <0>; + #address-cells =3D <0>; + #size-cells =3D <0>; + status =3D "disabled"; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt =3D <0x7>; + snps,rd_osr_lmt =3D <0x7>; + snps,blen =3D <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use =3D <4>; + snps,rx-sched-sp; + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue2 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + queue3 { + snps,dcb-algorithm; + snps,map-to-dma-channel =3D <0x0>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use =3D <4>; + snps,tx-sched-wrr; + queue0 { + snps,weight =3D <0x10>; + snps,dcb-algorithm; + snps,priority =3D <0x0>; + }; + queue1 { + snps,weight =3D <0x11>; + snps,dcb-algorithm; + snps,priority =3D <0x1>; + }; + queue2 { + snps,weight =3D <0x12>; + snps,dcb-algorithm; + snps,priority =3D <0x2>; + }; + queue3 { + snps,weight =3D <0x13>; + snps,dcb-algorithm; + snps,priority =3D <0x3>; + }; + }; + }; + xhci0: usb@11200000 { compatible =3D "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; --=20 2.25.1