From nobody Wed Dec 17 06:00:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 556A8C4332F for ; Wed, 19 Oct 2022 12:00:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232401AbiJSMAv (ORCPT ); Wed, 19 Oct 2022 08:00:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232105AbiJSL7f (ORCPT ); Wed, 19 Oct 2022 07:59:35 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26BD8183E35 for ; Wed, 19 Oct 2022 04:37:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666179475; x=1697715475; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FwpnNa97Mj/Phd95ve5SDiYa4ysBAsIf7rLrYAdSLJI=; b=ignOS9oKZAQ12MOD4Pr3qZjWgd+0DbcDcTERSM/oAtoap2YiCgJhxDm0 ZTu5ZWk/o3nDgycMgOxg2y5YwZVVizNrBZMDKwSBdOLPdsUxtEIzTe8qY qvUJ568aIXeEfQfk9+XBph1uY90Hqb/Q/GjlJasZ4HyXvHGjk2CHkPetU a8tlxNvBLnMNKZ1dblIFF04/u5x0iSRmlsoGj6B23Pu8JtqduvL5aZNAT KnyV+Kk2IknMI9bpS81KQGaEYKYF50wukQuzretrI64t8j7VRe0jfgRzU CY0W1MdTHnQDH4defRA7JWL0ZxnEl2fkAE35WPWhUwVoUxetY4vIVvlZX w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="308054293" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="308054293" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 03:13:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="692312610" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="692312610" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:31 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 1/5] x86/cpufeature: add the cpu feature bit for LKGS Date: Wed, 19 Oct 2022 02:50:31 -0700 Message-Id: <20221019095035.10823-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "H. Peter Anvin (Intel)" Add the CPU feature bit for LKGS (Load "Kernel" GS). LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specificaton https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment=E2=80=99s descriptor cache, which is exactly what Linux kernel does to load a user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- Change since V2: * add "" not to show "lkgs" in /proc/cpuinfo (Chang S. Bae). --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index b71f4f2ecdd5..3dc1a48c2796 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index ef4775c6db01..9d45071d1730 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ --=20 2.34.1 From nobody Wed Dec 17 06:00:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A94EC433FE for ; Wed, 19 Oct 2022 12:01:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231165AbiJSMBi (ORCPT ); Wed, 19 Oct 2022 08:01:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230389AbiJSMAD (ORCPT ); Wed, 19 Oct 2022 08:00:03 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 874C8F01A6 for ; Wed, 19 Oct 2022 04:38:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666179487; x=1697715487; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LPkLGLb6ct3NaqkfE/fcmAkN388PX6Fn1d7MFn2Rg6I=; b=DwhpCYb0A6UYEzxVgCBxYgEPaaFihKWUGhL/lM5cKwltJ9tvNGq5nxlS MngdJUHWZfVxZtK9xSZGMUKc4QQjNoyquXvSm16aAHZpaPfkjKr11sDP1 RJQWuubk3ApxItO8eS4YBr8D7OEMaTxHOwUYk3NglcT87kpjSkPtJTT3q Vk7reYIG1gtufVbD5wvrvjvxhJ4hkaSG3z5WZ/N4Qfg4HfZJmiF/Ti0Od G/HwWb/b+FbsFlHeP10cpjY99v8K4amgnpolCMEKusb/vw+xuprL3mP11 qgyRr8QrzbH9kebz9WCL5/Al8TvabWXuUqjCY7ZIECEBz019itdAK5cZj A==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="308054294" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="308054294" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 03:13:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="692312613" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="692312613" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:32 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 2/5] x86/opcode: add the LKGS instruction to x86-opcode-map Date: Wed, 19 Oct 2022 02:50:32 -0700 Message-Id: <20221019095035.10823-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Add the instruction opcode used by LKGS. Opcode number is per public FRED draft spec v3.0 https://cdrdv2.intel.com/v1/dl/getContent/678938. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.= txt index d12d1358f96d..5168ee0360b2 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable =20 GrpTable: Grp7 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86= -opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable =20 GrpTable: Grp7 --=20 2.34.1 From nobody Wed Dec 17 06:00:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B35DC4321E for ; Wed, 19 Oct 2022 12:01:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232284AbiJSMBK (ORCPT ); Wed, 19 Oct 2022 08:01:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232231AbiJSL7o (ORCPT ); Wed, 19 Oct 2022 07:59:44 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA1BB1285FE for ; Wed, 19 Oct 2022 04:38:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666179488; x=1697715488; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1YbzoiUXSvQWzBUraiDzjfmE9NvY0qFctz1F+7sN7Sw=; b=h0aAip2JBSMYhQuK+6RhnMi1DTAfpvNE3mHX54BJCFQoWoPob1NRcn4G W7+pm0UjWQXFh65fpM/U0aQy7nUwz29siPo2qYWOG2n2RGelBJBsNn7Xb asAKpip2ZCZNO7qw01a3NxCwxAxFXtbpbum1KlRO5G635YN66Mi/M0dkJ ikXCF8zv/T0mVhIk8J67w3He7nD3r+I6EGWehH4dqy3M7dw68aDYehDIj YgnrmKgNDlbLFqVDuLwGyr3oR8/0aag64YMy+IuLUqlTDvXJntD4nOVz+ PL4ezJFtrH2OSiny/qPAj6jwIO+JXQ4wyazOHrqppwSe1gWVnt+LWFyEz Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="308054296" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="308054296" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 03:13:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="692312619" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="692312619" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:32 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 3/5] x86/gsseg: make asm_load_gs_index() take an u16 Date: Wed, 19 Oct 2022 02:50:33 -0700 Message-Id: <20221019095035.10823-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..e0c48998d2fb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -779,7 +779,7 @@ _ASM_NOKPROBE(common_interrupt_return) =20 /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } =20 -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); =20 static inline void native_load_gs_index(unsigned int selector) { --=20 2.34.1 From nobody Wed Dec 17 06:00:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94DDAC433FE for ; Wed, 19 Oct 2022 12:01:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232286AbiJSMBu (ORCPT ); Wed, 19 Oct 2022 08:01:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232068AbiJSMBD (ORCPT ); Wed, 19 Oct 2022 08:01:03 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 785C41C19CA for ; Wed, 19 Oct 2022 04:38:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666179493; x=1697715493; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3IzxOY7iZxpDqFZXqjU2m7iuBaRk3oOqMz/MsyK/kHA=; b=MbNhhzPCCOGsizWK2XHjihtJeQQCw+QyVBFCCtA4iaasZKnXu+PIq7Ym cn8FndXwZEFJTdeKwR1YbscrZMh2BlvreI3ZPA+5xOHosjHu+FNKMv+yZ Bj/dK3a5NxoqF9X/rNsj3FMzZfOYE0pz6L/I8tt1FN7oiG7x1iVqDgY5+ JQ5GYpuDjxx+VL62EVo8mGEWsGCDJpyryHG1RY8sFmmACLBJpwufEC3Iw YIqHz+0zU9vUEhATRKLI4A2gLldfr7eQjOaWgTLqgbfr3SsaGzTN2M+vp oAYejIuP5M5pxOHwyUq/WrkLGO9Xj64R3jbeS8njW00aYy3yglyRBW4sY w==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="308054299" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="308054299" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 03:13:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="692312622" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="692312622" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:32 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 4/5] x86/gsseg: move load_gs_index() to its own new header file Date: Wed, 19 Oct 2022 02:50:34 -0700 Message-Id: <20221019095035.10823-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" GS is a special segment on x86_64, move load_gs_index() to its own new header file. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/gsseg.h | 41 ++++++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 21 -------------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + 6 files changed, 45 insertions(+), 21 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index c9c3859322fa..14c739303099 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -34,6 +34,7 @@ #include #include #include +#include =20 static inline void reload_segments(struct sigcontext_32 *sc) { diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h new file mode 100644 index 000000000000..d15577c39e8d --- /dev/null +++ b/arch/x86/include/asm/gsseg.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_GSSEG_H +#define _ASM_X86_GSSEG_H + +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_X86_64 + +extern asmlinkage void asm_load_gs_index(u16 selector); + +static inline void native_load_gs_index(unsigned int selector) +{ + unsigned long flags; + + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); +} + +#endif /* CONFIG_X86_64 */ + +#ifndef CONFIG_PARAVIRT_XXL + +static inline void load_gs_index(unsigned int selector) +{ +#ifdef CONFIG_X86_64 + native_load_gs_index(selector); +#else + loadsegment(gs, selector); +#endif +} + +#endif /* CONFIG_PARAVIRT_XXL */ + +#endif /* _ASM_X86_GSSEG_H */ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index b8d40ddeab00..e01aa74a6de7 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -12,6 +12,7 @@ #include #include #include +#include =20 extern atomic64_t last_mm_ctx_id; =20 diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index a71d0e8d4684..cfd9499b617c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,17 +120,6 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } =20 -extern asmlinkage void asm_load_gs_index(u16 selector); - -static inline void native_load_gs_index(unsigned int selector) -{ - unsigned long flags; - - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); -} - static inline unsigned long __read_cr4(void) { return native_read_cr4(); @@ -184,16 +173,6 @@ static inline void wbinvd(void) native_wbinvd(); } =20 - -static inline void load_gs_index(unsigned int selector) -{ -#ifdef CONFIG_X86_64 - native_load_gs_index(selector); -#else - loadsegment(gs, selector); -#endif -} - #endif /* CONFIG_PARAVIRT_XXL */ =20 static inline void clflush(volatile void *__p) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 7ca2d46c08cc..00f6a92551d2 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -32,6 +32,7 @@ #include #include #include +#include =20 /* * nop stub, which must not clobber anything *including the stack* to diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 3c883e064242..3ffbab0081f4 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #include "tls.h" =20 --=20 2.34.1 From nobody Wed Dec 17 06:00:35 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07E0EC4332F for ; Wed, 19 Oct 2022 12:02:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231730AbiJSMCH (ORCPT ); Wed, 19 Oct 2022 08:02:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232349AbiJSMBi (ORCPT ); Wed, 19 Oct 2022 08:01:38 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24998F53D9 for ; Wed, 19 Oct 2022 04:38:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666179502; x=1697715502; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j1nrWwUKj7h3R57+EPy6Nb6HTjf2lvY1jPi2BPfuQLU=; b=MVWjmA7M8BJ609W7/eAn6+thiMRjXL6bdKADh5VJLLaPVzvo4AB1ajUT YbBPw9N+8DqvVtwrSRyZsglqNpHNyJ4hGJIktpgPUNZOmo/B53C1DF8sG 4wr9kjS2YlIQgLf4eAustdA+keMuLCOSvdtMp8KpJSV7+rpl6ZQ/h30Wq zhkTu0YGlwlariRd1QS0FointFcen4Cx9xRNZd8zKylcmqQ/QSi56Zvox a9xCbW49jAJ1aF6z04CLD8V8IeO8HVFxyBgK3mcKimrqcJO4/NGN8BDcz oUjHXnJ3WJYEuo5l/YASmwT4r5MaEtu8UNI8PHOxM+f8rNFQdgNgW9QDa A==; X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="308054300" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="308054300" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 03:13:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10504"; a="692312627" X-IronPort-AV: E=Sophos;i="5.95,195,1661842800"; d="scan'208";a="692312627" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 03:13:32 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v4 5/5] x86/gsseg: use the LKGS instruction if available for load_gs_index() Date: Wed, 19 Oct 2022 02:50:35 -0700 Message-Id: <20221019095035.10823-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221019095035.10823-1-xin3.li@intel.com> References: <20221019095035.10823-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Brian Gerst Signed-off-by: Xin Li --- Changes since v3: * We want less ASM not more, thus keep local_irq_save/restore() inside native_load_gs_index() (Thomas Gleixner). * For paravirt enabled kernels, initialize pv_ops.cpu.load_gs_index to native_lkgs (Thomas Gleixner). Changes since V2: * Mark DI as input and output (+D) as in V1, since the exception handler modifies it (Brian Gerst). Changes since V1: * Use EX_TYPE_ZERO_REG instead of fixup code in the obsolete .fixup code section (Peter Zijlstra). * Add a comment that states the LKGS_DI macro will be repalced with "lkgs %= di" once the binutils support the LKGS instruction (Peter Zijlstra). --- arch/x86/include/asm/gsseg.h | 33 +++++++++++++++++++++++++++++---- arch/x86/kernel/cpu/common.c | 1 + 2 files changed, 30 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h index d15577c39e8d..ab6a595cea70 100644 --- a/arch/x86/include/asm/gsseg.h +++ b/arch/x86/include/asm/gsseg.h @@ -14,17 +14,42 @@ =20 extern asmlinkage void asm_load_gs_index(u16 selector); =20 +/* Replace with "lkgs %di" once binutils support LKGS instruction */ +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7) + +static inline void native_lkgs(unsigned int selector) +{ + u16 sel =3D selector; + asm_inline volatile("1: " LKGS_DI + _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel]) + : [sel] "+D" (sel)); +} + static inline void native_load_gs_index(unsigned int selector) { - unsigned long flags; + if (cpu_feature_enabled(X86_FEATURE_LKGS)) { + native_lkgs(selector); + } else { + unsigned long flags; =20 - local_irq_save(flags); - asm_load_gs_index(selector); - local_irq_restore(flags); + local_irq_save(flags); + asm_load_gs_index(selector); + local_irq_restore(flags); + } } =20 #endif /* CONFIG_X86_64 */ =20 +static inline void __init lkgs_init(void) +{ +#ifdef CONFIG_PARAVIRT_XXL +#ifdef CONFIG_X86_64 + if (cpu_feature_enabled(X86_FEATURE_LKGS)) + pv_ops.cpu.load_gs_index =3D native_lkgs; +#endif +#endif +} + #ifndef CONFIG_PARAVIRT_XXL =20 static inline void load_gs_index(unsigned int selector) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 3e508f239098..d6eb4f60b47d 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1939,6 +1939,7 @@ void __init identify_boot_cpu(void) setup_cr_pinning(); =20 tsx_init(); + lkgs_init(); } =20 void identify_secondary_cpu(struct cpuinfo_x86 *c) --=20 2.34.1