From nobody Fri Oct 17 13:25:58 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 994D8C433FE for ; Wed, 19 Oct 2022 13:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232499AbiJSNkz (ORCPT ); Wed, 19 Oct 2022 09:40:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232565AbiJSNiy (ORCPT ); Wed, 19 Oct 2022 09:38:54 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB8DEC8950; Wed, 19 Oct 2022 06:26:23 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id BF738B82428; Wed, 19 Oct 2022 08:57:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F91EC433C1; Wed, 19 Oct 2022 08:57:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1666169855; bh=QE29W445skf+b67eNF58++sy3X82ljVGxWpQJ0ChOqc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WHLoCBf8JsZaosJNlvfI/JjDw0OwuXN7PYBonePMavyPOJRfo1DfotgDfwPb+r2Qx oBtMk1YtAkgp0hXbAIEoRwlgLvnC+HvavPjEuXRgHwvaVeU81X7dkIZuBPRANxG2ET Cv94GYp35myXiztKsxIwgOQJVy2DyaopLyUjs1HY= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, =?UTF-8?q?Marek=20Beh=C3=BAn?= , Gregory CLEMENT , Sasha Levin Subject: [PATCH 6.0 434/862] ARM: dts: turris-omnia: Fix mpp26 pin name and comment Date: Wed, 19 Oct 2022 10:28:41 +0200 Message-Id: <20221019083309.154357076@linuxfoundation.org> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221019083249.951566199@linuxfoundation.org> References: <20221019083249.951566199@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marek Beh=C3=BAn [ Upstream commit 49e93898f0dc177e645c22d0664813567fd9ec00 ] There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin, which is routed to CN11 pin header, is documented as SPI CS1, but MPP[26] pin does not support this function. Instead it controls chip select 2 if in "spi0" mode. Fix the name of the pin node in pinctrl node and fix the comment in SPI node. Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia") Signed-off-by: Marek Beh=C3=BAn Signed-off-by: Gregory CLEMENT Signed-off-by: Sasha Levin --- arch/arm/boot/dts/armada-385-turris-omnia.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/= dts/armada-385-turris-omnia.dts index d1e0db6e5730..a41902e3815c 100644 --- a/arch/arm/boot/dts/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts @@ -476,7 +476,7 @@ marvell,function =3D "spi0"; }; =20 - spi0cs1_pins: spi0cs1-pins { + spi0cs2_pins: spi0cs2-pins { marvell,pins =3D "mpp26"; marvell,function =3D "spi0"; }; @@ -511,7 +511,7 @@ }; }; =20 - /* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */ + /* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */ }; =20 &uart0 { --=20 2.35.1