From nobody Fri Oct 17 10:32:20 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB75CC4332F for ; Wed, 19 Oct 2022 08:52:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231777AbiJSIwO (ORCPT ); Wed, 19 Oct 2022 04:52:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231723AbiJSItI (ORCPT ); Wed, 19 Oct 2022 04:49:08 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58FE79185F; Wed, 19 Oct 2022 01:47:03 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A9FD061831; Wed, 19 Oct 2022 08:47:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9C911C433C1; Wed, 19 Oct 2022 08:47:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1666169222; bh=IfWrrYSMy5ZOVDZlf3ehBiPo9AMi1p4jSVtv16gPtBo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t1vo3Fbkc7RGb0PJYakkmzHPRtcqXFmiAqAeNIsJgJA3tBVSOsAps8Ox/tfkKyBx0 n+4bo59DcxYoImVUpRcxQ0WPp2K0qpKriw7bHYIWdeN38rgiT4dciQMNyUs8FbcPBg JqEr1TxoD+Lo72E31BT2b4enhQDPmPtg0ZF1jY6o= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Ruili Ji , Yifan Zhang , Alex Deucher Subject: [PATCH 6.0 200/862] drm/amdgpu: Enable F32_WPTR_POLL_ENABLE in mqd Date: Wed, 19 Oct 2022 10:24:47 +0200 Message-Id: <20221019083258.845787699@linuxfoundation.org> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221019083249.951566199@linuxfoundation.org> References: <20221019083249.951566199@linuxfoundation.org> User-Agent: quilt/0.67 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Ruili Ji commit 21a550de5faf9f54013334c9a6a7643b8fd80b36 upstream. This patch is to fix the SDMA user queue doorbell missing issue on SDMA 6.0. F32_WPTR_POLL_ENABLE has to be set if doorbell mode is used. Otherwise ringing SDMA user queue doorbell can't wake up system from gfxoff. Signed-off-by: Ruili Ji Reviewed-by: Yifan Zhang Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.0.x Signed-off-by: Greg Kroah-Hartman --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -910,7 +910,8 @@ static int sdma_v6_0_mqd_init(struct amd m->sdmax_rlcx_rb_cntl =3D order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHI= FT | 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | - 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; + 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | + 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; =20 m->sdmax_rlcx_rb_base =3D lower_32_bits(prop->hqd_base_gpu_addr >> 8); m->sdmax_rlcx_rb_base_hi =3D upper_32_bits(prop->hqd_base_gpu_addr >> 8); --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v11.c @@ -375,7 +375,8 @@ static void update_mqd_sdma(struct mqd_m << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT | q->vmid << SDMA0_QUEUE0_RB_CNTL__RB_VMID__SHIFT | 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT | - 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT; + 6 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT | + 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT; =20 m->sdmax_rlcx_rb_base =3D lower_32_bits(q->queue_address >> 8); m->sdmax_rlcx_rb_base_hi =3D upper_32_bits(q->queue_address >> 8);