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Tue, 18 Oct 2022 09:28:32 -0700 From: Akhil R To: , , , , , , , CC: Subject: [PATCH RESEND v2 1/3] dt-bindings: dmaengine: Add dma-channel-mask to Tegra GPCDMA Date: Tue, 18 Oct 2022 21:58:10 +0530 Message-ID: <20221018162812.69673-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221018162812.69673-1-akhilrajeev@nvidia.com> References: <20221018162812.69673-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT018:EE_|MN0PR12MB5907:EE_ X-MS-Office365-Filtering-Correlation-Id: e3975ff4-ee76-40f2-8aea-08dab125d636 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: oks7N8ldAqCmQIAd88prKkm102GY0g6/a+vD8NXPZeA4pmGnXdk+XSK7xST8LZVQbAFe3i63T2mctIbboTxkRvWkiqyUcm0BLhz3bZSUD7BDnjaq4EgkoqtroD4Nwn1kYYIWvUyCIBCUZK2bmtJKMfIKBSb9zS3pH9btiRF9SqRv3W8CGmBo5HAx5/UyBSgGIZdTi/8cvP+yG6lIrYLKdZsX0QHihjh/xcYeyCE5d9MqSeJvhfndl8usY0LgSPAUY7HTR+1rNV9avrcrS7Ie/08I0SPQfuZbLh0gNWtgB/gXHmbI0tIqB2qNxMyuvaPlJB1/1kfuRVRnG0DI01/26BP7+SQQaiaOT2QcQCGmqN/gEPE6oyY8FEV+tlp4cTBTJhwzbesz8aKqFfHiMfYHFZVufHezXYkQXKXa2OcfnG1nt1sChPuZVn1WCZ6ydoEHRt8GWjr9piFTd3wwZhZYAY/jnBvif/t9Z2GjtRO4ZuResLJ1Q1A2AbdrK/WRhPNh7y7vTfeQMdqPV+DEDkocbJRIyM+Ui2xjOw9soIkihmk14HTdRMfRJ6AY7WvB+XuLtkMc0M8XHcJzr1DDxADoAZ0UHTS4d9JcqKJ3I1TKvXpen9BxQkxkYNaZO3h8eRYQ7hcc3ZJ/21eljhqWGWgt4W6Ka8XJcwhDG67erVgLrIV7pRXtUt2vPgEA6AREfLCRRBW/8Rd7sIxDAb8D32YkJ5cfQwQCTCc9Z13zO9GgRQYFbwWbdbv38XO/9ARaUXfVeLrzNfjuGlrLsKMsMMHVwQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(136003)(346002)(39860400002)(451199015)(46966006)(36840700001)(40470700004)(82740400003)(36860700001)(82310400005)(7636003)(356005)(478600001)(7696005)(36756003)(336012)(41300700001)(2906002)(186003)(1076003)(2616005)(316002)(47076005)(86362001)(4326008)(6666004)(8676002)(40480700001)(107886003)(426003)(70206006)(70586007)(110136005)(40460700003)(8936002)(5660300002)(26005)(83380400001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2022 16:28:49.0120 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3975ff4-ee76-40f2-8aea-08dab125d636 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5907 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dma-channel-mask property in Tegra GPCDMA document. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. Now since we can list all 32 channels, update the interrupts property as well to list all 32 interrupts. Signed-off-by: Akhil R Acked-by: Thierry Reding --- .../devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.= yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index c8894476b6ab..851bd50ee67f 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -39,7 +39,7 @@ properties: Should contain all of the per-channel DMA interrupts in ascending order with respect to the DMA channel index. minItems: 1 - maxItems: 31 + maxItems: 32 =20 resets: maxItems: 1 @@ -52,6 +52,9 @@ properties: =20 dma-coherent: true =20 + dma-channel-mask: + maxItems: 1 + required: - compatible - reg @@ -60,6 +63,7 @@ required: - reset-names - "#dma-cells" - iommus + - dma-channel-mask =20 additionalProperties: false =20 @@ -108,5 +112,6 @@ examples: #dma-cells =3D <1>; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2022 16:28:52.7033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fbebc32c-66be-4e12-9117-08dab125d86e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7357 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add dma-channel-mask property in Tegra GPCDMA device tree node. The property would help to specify the channels to be used in kernel and reserve few for the firmware. This was previously achieved by limiting the channel number to 31 in the driver. Now since we can list all 32 channels, update the interrupts property as well to list all 32 interrupts. Signed-off-by: Akhil R --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts= /nvidia/tegra186.dtsi index 6602fe421ee8..db479064ff72 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -78,7 +78,8 @@ reg =3D <0x0 0x2600000 0x0 0x210000>; resets =3D <&bpmp TEGRA186_RESET_GPCDMA>; reset-names =3D "gpcdma"; - interrupts =3D , + interrupts =3D , + , , , , @@ -112,6 +113,7 @@ #dma-cells =3D <1>; iommus =3D <&smmu TEGRA186_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask =3D <0xfffffffe>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts= /nvidia/tegra194.dtsi index 41f3a7e188d0..b009f8145016 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -142,7 +142,8 @@ reg =3D <0x2600000 0x210000>; resets =3D <&bpmp TEGRA194_RESET_GPCDMA>; reset-names =3D "gpcdma"; - interrupts =3D , + interrupts =3D , + , , , , @@ -176,6 +177,7 @@ #dma-cells =3D <1>; iommus =3D <&smmu TEGRA194_SID_GPCDMA_0>; dma-coherent; + dma-channel-mask =3D <0xfffffffe>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts= /nvidia/tegra234.dtsi index 0170bfa8a467..ccc1a4bd094d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -27,7 +27,8 @@ reg =3D <0x2600000 0x210000>; resets =3D <&bpmp TEGRA234_RESET_GPCDMA>; reset-names =3D "gpcdma"; - interrupts =3D , + interrupts =3D , + , , , , @@ -60,6 +61,7 @@ ; #dma-cells =3D <1>; iommus =3D <&smmu_niso0 TEGRA234_SID_GPCDMA>; + dma-channel-mask =3D <0xfffffffe>; dma-coherent; }; =20 --=20 2.17.1 From nobody Tue Apr 7 17:39:25 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5833CC433FE for ; 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Tue, 18 Oct 2022 09:28:44 -0700 From: Akhil R To: , , , , , , , CC: Subject: [PATCH RESEND v2 3/3] dmaengine: tegra: Add support for dma-channel-mask Date: Tue, 18 Oct 2022 21:58:12 +0530 Message-ID: <20221018162812.69673-4-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221018162812.69673-1-akhilrajeev@nvidia.com> References: <20221018162812.69673-1-akhilrajeev@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT085:EE_|SA1PR12MB7223:EE_ X-MS-Office365-Filtering-Correlation-Id: 40123605-acf8-414d-3bc5-08dab125def2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: zZxOWxw930dfHXMEvveriM9BT0cgnXx0plZ8vWQoQNqzeGhAs+8l4ZK/FAXKtDOKOCpdPzYUZhI1gSbVHO/z9JLpnFkUxvfF74fAHjAkAopsq/hzfj77fbGe1mQ/s/9GJu2xwpgz/HJ4Z9Wmargc7F0DqwKzBnzNj663tZmMdVSD7jRL5TQxqzqZeY+9awIWFu39nIV1Xmq21w492urnDH/pA4uQXUvv3XHbvoddKmZXoTWpeKQMZvmqgroBwk+OpXmUd9AP1IAXpA7kUacpdkXBmhfuPutzExHJ+HDuhx4fcR33xxPpZWgQnCcXMk0F5yDyh45la/YbKq2PcOY5m1YYmBrG/bj6jNQWg11CIokTAy65kCxAKbtGAgOpmh7SBGZf9fU6MXah/14Z3dEu+oVeFRScLOuKmM1Qq9vSYTk//3SR8v5CFvTk31iAfFdNTiFrFyrpQE0Grkt6SpXwgyb2ZTxKbboCpBS7/BInAWDO7F22GD50ifMldU9ymdYVaF/arzaz4McA9fXjJ4eo5lDK6wpouq5IxlyOp7l8JdSxzNgC9D7ZNMc8JJYm4DsY7L/J3oOXAUr/Cfnlr4lJjJfhSLic4KNEHde8GyxhGuz5ctVXvLX3ddDrxCTUbxvj6MTDTSfAEyDdsnLga6KEvKbvGMw/cA0ig5DGLytylumTN7c+3ZoiXoHI+MjOiG5/7POF8S99TkpZh8aXKoZHQqHdzWQWb0EuM82kha+hK0w+Alwn9wyTLDDhBBaP1dDlrjINFF45hMlxHlfV/0gfqA== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(396003)(136003)(376002)(451199015)(46966006)(40470700004)(36840700001)(36756003)(2906002)(82310400005)(8936002)(5660300002)(86362001)(4326008)(107886003)(40460700003)(41300700001)(186003)(26005)(2616005)(1076003)(478600001)(336012)(6666004)(8676002)(426003)(47076005)(7636003)(40480700001)(70586007)(356005)(83380400001)(70206006)(7696005)(316002)(82740400003)(110136005)(36860700001);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2022 16:29:03.6326 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 40123605-acf8-414d-3bc5-08dab125def2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7223 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for dma-channel-mask so that only the specified channels are used. This helps to reserve some channels for the firmware. This was initially achieved by limiting the channel number to 31 in the driver and adjusting the register address to skip channel0 which was reserved for a firmware. Now, with this change, the driver can align more to the actual hardware which has 32 channels. Signed-off-by: Akhil R Reviewed-by: Jon Hunter --- drivers/dma/tegra186-gpc-dma.c | 37 +++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c index fa9bda4a2bc6..1d1180db6d4e 100644 --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -161,7 +161,10 @@ #define TEGRA_GPCDMA_BURST_COMPLETION_TIMEOUT 5000 /* 5 msec */ =20 /* Channel base address offset from GPCDMA base address */ -#define TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET 0x20000 +#define TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET 0x10000 + +/* Default channel mask reserving channel0 */ +#define TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK 0xfffffffe =20 struct tegra_dma; struct tegra_dma_channel; @@ -246,6 +249,7 @@ struct tegra_dma { const struct tegra_dma_chip_data *chip_data; unsigned long sid_m2d_reserved; unsigned long sid_d2m_reserved; + u32 chan_mask; void __iomem *base_addr; struct device *dev; struct dma_device dma_dev; @@ -1288,7 +1292,7 @@ static struct dma_chan *tegra_dma_of_xlate(struct of_= phandle_args *dma_spec, } =20 static const struct tegra_dma_chip_data tegra186_dma_chip_data =3D { - .nr_channels =3D 31, + .nr_channels =3D 32, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D false, @@ -1296,7 +1300,7 @@ static const struct tegra_dma_chip_data tegra186_dma_= chip_data =3D { }; =20 static const struct tegra_dma_chip_data tegra194_dma_chip_data =3D { - .nr_channels =3D 31, + .nr_channels =3D 32, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, @@ -1304,7 +1308,7 @@ static const struct tegra_dma_chip_data tegra194_dma_= chip_data =3D { }; =20 static const struct tegra_dma_chip_data tegra234_dma_chip_data =3D { - .nr_channels =3D 31, + .nr_channels =3D 32, .channel_reg_size =3D SZ_64K, .max_dma_count =3D SZ_1G, .hw_support_pause =3D true, @@ -1380,15 +1384,28 @@ static int tegra_dma_probe(struct platform_device *= pdev) } stream_id =3D iommu_spec->ids[0] & 0xffff; =20 + ret =3D device_property_read_u32(&pdev->dev, "dma-channel-mask", + &tdma->chan_mask); + if (ret) { + dev_warn(&pdev->dev, + "Missing dma-channel-mask property, using default channel mask %#x\n", + TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK); + tdma->chan_mask =3D TEGRA_GPCDMA_DEFAULT_CHANNEL_MASK; + } + INIT_LIST_HEAD(&tdma->dma_dev.channels); for (i =3D 0; i < cdata->nr_channels; i++) { struct tegra_dma_channel *tdc =3D &tdma->channels[i]; =20 + /* Check for channel mask */ + if (!(tdma->chan_mask & BIT(i))) + continue; + tdc->irq =3D platform_get_irq(pdev, i); if (tdc->irq < 0) return tdc->irq; =20 - tdc->chan_base_offset =3D TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET + + tdc->chan_base_offset =3D TEGRA_GPCDMA_CHANNEL_BASE_ADDR_OFFSET + i * cdata->channel_reg_size; snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); tdc->tdma =3D tdma; @@ -1449,8 +1466,8 @@ static int tegra_dma_probe(struct platform_device *pd= ev) return ret; } =20 - dev_info(&pdev->dev, "GPC DMA driver register %d channels\n", - cdata->nr_channels); + dev_info(&pdev->dev, "GPC DMA driver register %lu channels\n", + hweight_long(tdma->chan_mask)); =20 return 0; } @@ -1473,6 +1490,9 @@ static int __maybe_unused tegra_dma_pm_suspend(struct= device *dev) for (i =3D 0; i < tdma->chip_data->nr_channels; i++) { struct tegra_dma_channel *tdc =3D &tdma->channels[i]; =20 + if (!(tdma->chan_mask & BIT(i))) + continue; + if (tdc->dma_desc) { dev_err(tdma->dev, "channel %u busy\n", i); return -EBUSY; @@ -1492,6 +1512,9 @@ static int __maybe_unused tegra_dma_pm_resume(struct = device *dev) for (i =3D 0; i < tdma->chip_data->nr_channels; i++) { struct tegra_dma_channel *tdc =3D &tdma->channels[i]; =20 + if (!(tdma->chan_mask & BIT(i))) + continue; + tegra_dma_program_sid(tdc, tdc->stream_id); } =20 --=20 2.17.1