From nobody Tue Apr 7 19:03:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DD3BC4332F for ; Tue, 18 Oct 2022 13:15:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230359AbiJRNPK (ORCPT ); Tue, 18 Oct 2022 09:15:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230220AbiJRNO6 (ORCPT ); Tue, 18 Oct 2022 09:14:58 -0400 Received: from egress-ip33b.ess.de.barracuda.com (egress-ip33b.ess.de.barracuda.com [18.185.115.237]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13B1D399F0 for ; Tue, 18 Oct 2022 06:14:48 -0700 (PDT) Received: from mail-pj1-f70.google.com (mail-pj1-f70.google.com [209.85.216.70]) by mx-outbound21-93.eu-central-1b.ess.aws.cudaops.com (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 18 Oct 2022 13:14:44 +0000 Received: by mail-pj1-f70.google.com with SMTP id oo18-20020a17090b1c9200b0020bdba475afso11786850pjb.4 for ; Tue, 18 Oct 2022 06:14:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mistralsolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7gUNAKJLQD4mhpB+2CwqveRQRM7i9T+yPyinXJEn1U4=; b=EVNsbouI6gDqzPK7MXpozm4ZyZwlRfAbR5HN2EldEvwuAluEXsSDgsQRpj9i6jRntk IYj/IJZlvT2g9C/R7b3mMc1MHy/3yNrlfOcdzyScOzJg3La9T4aIn3JLYksMQOjU+U1U Aj2J8IFnd4vMeX6c4b8sp+/gMHEZba/r1fAuw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7gUNAKJLQD4mhpB+2CwqveRQRM7i9T+yPyinXJEn1U4=; b=ZiMrjyjffKz/MJb2Wy3WZs+4kNMt/krP1l74jBJ2QT+aMIUArdo8cs4VGus3HRAtQY zcb0NsX9htCjqnaAMztFvoDK1cPV0eA4aOQU7fRN43Vid68PEHSDEHXhEIh/8S+wO5Gq ZZs0BC9haDU42Jf4gtOuPFd/M27bWt6d1OD3QoJM9k9cS0uZxZemKor8CYXB6gJZofl2 3O3Vb03vUickoNfy+IVdVbX+pW5jPJgt26wVpSVPXg285zRr1I68ZYguowX98iRx7kLK MLT6qKj/rqImTSzM9inyaf9rA9c9pxiRHV7Jd1PcdG6e8mJ/uyiw1379Bl9kywdoTf6W Jgzg== X-Gm-Message-State: ACrzQf3L0p3p39ZeqZg4pG4VWnxoDeJzediz8HUZIwXog9d1F094ccI3 5aWZ52tEwYaNbYQMNU8pLQ8pS1P9uN0xdUhGKTzfqfZbxZfe67ME+7JQh/njziQwBTipdJ+Mmgi 9ocarbGwCoN0tsMIzuabPUEJ+oxsOjO9GkAg5OFf2bXxUaGLt9c3qEE9gQdLy X-Received: by 2002:a17:902:e945:b0:179:ce23:dd4d with SMTP id b5-20020a170902e94500b00179ce23dd4dmr2801742pll.68.1666097115290; Tue, 18 Oct 2022 05:45:15 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5o05ybVbZ4LZwR88IubUMEwIwak+n6lyRukisx/n6fWe/H35PWqVQiw4PtniwV12oM6LOKUw== X-Received: by 2002:a17:902:e945:b0:179:ce23:dd4d with SMTP id b5-20020a170902e94500b00179ce23dd4dmr2801706pll.68.1666097114878; Tue, 18 Oct 2022 05:45:14 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:330a:c5d2:e90c:db79:45c8:3513]) by smtp.gmail.com with ESMTPSA id a17-20020a621a11000000b00563ce1905f4sm9110102pfa.5.2022.10.18.05.45.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 05:45:14 -0700 (PDT) From: Sinthu Raja X-Google-Original-From: Sinthu Raja To: Nishanth Menon , Tero Kristo , Rob Herring Cc: Vignesh Raghavendra , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sinthu Raja Subject: [PATCH 3/3] arch: arm64: ti: Add support for AM68 SK base board Date: Tue, 18 Oct 2022 18:08:49 +0530 Message-Id: <20221018123849.23695-4-sinthu.raja@ti.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221018123849.23695-1-sinthu.raja@ti.com> References: <20221018123849.23695-1-sinthu.raja@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-BESS-ID: 1666098884-305469-5648-12970-1 X-BESS-VER: 2019.1_20221004.2324 X-BESS-Apparent-Source-IP: 209.85.216.70 X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.243545 [from cloudscan9-14.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_SC0_MISMATCH_TO, BSF_RULE7568M, BSF_BESS_OUTBOUND X-BESS-BRTS-Status: 1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sinthu Raja The SK architecture comprises of baseboard and a SOM board. It is as follows, +--------------------------------------+---+ | | |<--Connectors | +---| | +---------------------------+ | | | | SOM | +---| | | | | | | | | +---| Power Supply | | | | | | +---------------------------+ | | | |<--+ | BASE BOARD | +------------------------------------------+ AM68 Starter Kit's baseboard contains most of the actual connectors, power supply etc. The System on Module (SoM) is plugged on to the base board. Therefore, add support for peripherals brought out in the base board. Schematics: https://www.ti.com/lit/zip/SPRR463 Signed-off-by: Sinthu Raja --- arch/arm64/boot/dts/ti/Makefile | 2 + .../boot/dts/ti/k3-am68-sk-base-board.dts | 459 ++++++++++++++++++ 2 files changed, 461 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index 4555a5be2257..498b089d96f8 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -19,6 +19,8 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j7200-common-proc-board.dtb =20 dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-common-proc-board.dtb =20 +dtb-$(CONFIG_ARCH_K3) +=3D k3-am68-sk-base-board.dtb + dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am642-sk.dtb =20 diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts new file mode 100644 index 000000000000..f51cbd2e3b72 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -0,0 +1,459 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ + * + * Base Board: https://www.ti.com/lit/zip/SPRR463 + */ + +/dts-v1/; + +#include "k3-am68-sk-som.dtsi" +#include +#include +#include +#include + +/ { + compatible =3D "ti,am68-sk", "ti,j721s2"; + model =3D "Texas Instruments AM68 SK"; + + chosen { + stdout-path =3D "serial2:115200n8"; + bootargs =3D "console=3DttyS2,115200n8 earlycon=3Dns16550a,mmio32,0x2880= 000"; + }; + + aliases { + serial2 =3D &main_uart8; + mmc1 =3D &main_sdhci1; + can0 =3D &mcu_mcan0; + can1 =3D &mcu_mcan1; + can2 =3D &main_mcan6; + can3 =3D &main_mcan7; + }; + + vusb_main: fixedregulator-vusb-main5v0 { + /* USB MAIN INPUT 5V DC */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vusb-main5v0"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: fixedregulator-vsys3v3 { + /* Output of LM5141 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vusb_main>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_mmc1: fixedregulator-sd { + /* Output of TPS22918 */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vdd_mmc1"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply =3D <&vsys_3v3>; + gpio =3D <&exp1 10 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: gpio-regulator-TLV71033 { + /* Output of TLV71033 */ + compatible =3D "regulator-gpio"; + regulator-name =3D "tlv71033"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_sd_dv_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + vin-supply =3D <&vsys_3v3>; + gpios =3D <&main_gpio0 49 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + }; + + vsys_io_1v8: regulator-vsys-io-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys_io_1v2: regulator-vsys-io-1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys_io_1v2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + transceiver1: can-phy0 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_pins_default>; + standby-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; + }; + + transceiver2: can-phy1 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_pins_default>; + standby-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; + }; + + transceiver3: can-phy2 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan6_pins_default>; + standby-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; + }; + + transceiver4: can-phy3 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan7_pins_default>; + standby-gpios =3D <&exp1 6 GPIO_ACTIVE_HIGH>; + }; +}; + +&main_pmx0 { + + main_uart8_pins_default: main-uart8-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ + J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ + >; + }; + + main_i2c0_pins_default: i2c0_pins_default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0e0, PIN_INPUT, 0) /* (AH25) I2C0_SCL */ + J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ + J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ + J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ + J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ + J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ + J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ + J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0c4, PIN_INPUT, 7) /* (AB26) ECAP0_IN_APWM_OUT.GPIO0_49 = */ + >; + }; + + main_usbss0_pins_default: main-usbss0-pins-default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */ + >; + }; + + main_mcan6_pins_default: mcan6_pins_default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x098, PIN_INPUT, 0) /* (V25) MCASP0_AXR10.MCAN6_RX */ + J721S2_IOPAD(0x094, PIN_INPUT, 0) /* (AA25) MCASP0_AXR9.MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: mcan7_pins_default { + pinctrl-single,pins =3D < + J721S2_IOPAD(0x0a0, PIN_INPUT, 0) /* (AB25) MCASP0_AXR12.MCAN7_RX */ + J721S2_IOPAD(0x09c, PIN_INPUT, 0) /* (T24) MCASP0_AXR11.MCAN7_TX */ + >; + }; + +}; + +&wkup_pmx0 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ + J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ + J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ + J721S2_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ + J721S2_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ + J721S2_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ + J721S2_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ + J721S2_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ + J721S2_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ + J721S2_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ + J721S2_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ + J721S2_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ + J721S2_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ + >; + }; + + mcu_mcan0_pins_default: mcu-mcan0-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x0bc, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ + J721S2_WKUP_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-pins-default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (F26) WKUP_GPIO0_5.MCU_MCAN1_= RX */ + J721S2_WKUP_IOPAD(0x0d0, PIN_OUTPUT, 0) /* (C23) WKUP_GPIO0_4.MCU_MCAN1= _TX*/ + >; + }; + + mcu_i2c1_pins_default: mcu_i2c1_pins_default { + pinctrl-single,pins =3D < + J721S2_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_S= CL */ + J721S2_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_S= DA */ + >; + }; + +}; + +&main_gpio2 { + status =3D "disabled"; +}; + +&main_gpio4 { + status =3D "disabled"; +}; + +&main_gpio6 { + status =3D "disabled"; +}; + +&wkup_gpio1 { + status =3D "disabled"; +}; + +&wkup_uart0 { + status =3D "reserved"; +}; + +&main_uart0 { + status =3D "disabled"; +}; + +&main_uart1 { + status =3D "disabled"; +}; + +&main_uart2 { + status =3D "disabled"; +}; + +&main_uart3 { + status =3D "disabled"; +}; + +&main_uart4 { + status =3D "disabled"; +}; + +&main_uart5 { + status =3D "disabled"; +}; + +&main_uart6 { + status =3D "disabled"; +}; + +&main_uart7 { + status =3D "disabled"; +}; + +&main_uart8 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart8_pins_default>; + /* Shared with TFA on this platform */ + power-domains =3D <&k3_pds 357 TI_SCI_PD_SHARED>; +}; + +&main_uart9 { + status =3D "disabled"; +}; + +&main_i2c0 { + clock-frequency =3D <400000>; + + exp1: gpio@21 { + compatible =3D "ti,tca6424"; + reg =3D <0x21>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", "HDMI_PDn", + "HDMI_LS_OE", "DP0_3V3 _EN", "BOARDID_EEPROM_WP", + "CAN_STB", " ", "GPIO_uSD_PWR_EN", "eDP_ENABLE", + "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_MCU_RGMII_RST#", + "IO_EXP_CSI2_EXP_RSTz", " ", "CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; +}; + +&main_i2c1 { + status =3D "disabled"; +}; + +&main_i2c2 { + status =3D "disabled"; +}; + +&main_i2c3 { + status =3D "disabled"; +}; + +&main_i2c4 { + status =3D "disabled"; +}; + +&main_i2c5 { + status =3D "disabled"; +}; + +&main_i2c6 { + status =3D "disabled"; +}; + +&main_sdhci0 { + status =3D "disabled"; +}; + +&main_sdhci1 { + /* SD card */ + pinctrl-0 =3D <&main_mmc1_pins_default>; + pinctrl-names =3D "default"; + disable-wp; + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vdd_sd_dv>; +}; + +&mcu_cpsw { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; +}; + +&davinci_mdio { + phy0: ethernet-phy@0 { + reg =3D <0>; + ti,rx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + }; +}; + +&cpsw_port1 { + phy-mode =3D "rgmii-rxid"; + phy-handle =3D <&phy0>; +}; + +&mcu_mcan0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_pins_default>; + phys =3D <&transceiver1>; +}; + +&mcu_mcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_pins_default>; + phys =3D <&transceiver2>; +}; + +&main_mcan0 { + status =3D "disabled"; +}; + +&main_mcan1 { + status =3D "disabled"; +}; + +&main_mcan2 { + status =3D "disabled"; +}; + +&main_mcan3 { + status =3D "disabled"; +}; + +&main_mcan4 { + status =3D "disabled"; +}; + +&main_mcan5 { + status =3D "disabled"; +}; + +&main_mcan6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan6_pins_default>; + phys =3D <&transceiver3>; +}; + +&main_mcan7 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan7_pins_default>; + phys =3D <&transceiver4>; +}; + +&main_mcan8 { + status =3D "disabled"; +}; + +&main_mcan9 { + status =3D "disabled"; +}; + +&main_mcan10 { + status =3D "disabled"; +}; + +&main_mcan11 { + status =3D "disabled"; +}; + +&main_mcan12 { + status =3D "disabled"; +}; + +&main_mcan13 { + status =3D "disabled"; +}; + +&main_mcan14 { + status =3D "disabled"; +}; + +&main_mcan15 { + status =3D "disabled"; +}; + +&main_mcan17 { + status =3D "disabled"; +}; --=20 2.36.1