From nobody Tue Apr 7 19:02:34 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEFD6C4332F for ; Tue, 18 Oct 2022 11:37:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230271AbiJRLhb (ORCPT ); Tue, 18 Oct 2022 07:37:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229605AbiJRLh3 (ORCPT ); Tue, 18 Oct 2022 07:37:29 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3287BA27B for ; Tue, 18 Oct 2022 04:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666093024; x=1697629024; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YRI2YivWJDaeR3A5b46DIJCCsip9GmvTxTmH9XsxWxQ=; b=a1c91sRgQnEQxKto/7Jx6EmVW6MSiLh3Hg91hpNfqyyA/YP+NeYlJo1W zfA/fyOJx9hqVkIH5yACX76YSk4TusA6Lk0hqdyQWgI/OA3rPI+FHRIN8 TwJQhMWFFKQMtdDGmBfrzuyyW2tztTBrGQ6nJzK7SrbwBcweEo9ipUIN0 QgJ1+N0CeMdhEmrqJznPfM/cok8PkpU1LyrH+WxyccAKVXlHGTN3+/dA7 dNmNwOhGRyJoHsO9miX4SaUP853hKxTAPwgccDz4hFDNCjioj3fjzL+Wj JIvPTxwOy0FTyDo9CFX51DbY5+Iz5mBgnWNBiA+H7OiLAxnT6syaAH312 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="332620544" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="332620544" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:11 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861119" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861119" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:06 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id EDF1F1046BE; Tue, 18 Oct 2022 14:34:03 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 01/15] x86/mm: Fix CR3_ADDR_MASK Date: Tue, 18 Oct 2022 14:33:44 +0300 Message-Id: <20221018113358.7833-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mask must not include bits above physical address mask. These bits are reserved and can be used for other things. Bits 61 and 62 are used for Linear Address Masking. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe Reviewed-by: Alexander Potapenko Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/processor-flags.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/= processor-flags.h index 02c2cbda4a74..a7f3d9100adb 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -35,7 +35,7 @@ */ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63) =20 --=20 2.38.0