From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEFD6C4332F for ; Tue, 18 Oct 2022 11:37:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230271AbiJRLhb (ORCPT ); Tue, 18 Oct 2022 07:37:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229605AbiJRLh3 (ORCPT ); Tue, 18 Oct 2022 07:37:29 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3287BA27B for ; Tue, 18 Oct 2022 04:37:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666093024; x=1697629024; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YRI2YivWJDaeR3A5b46DIJCCsip9GmvTxTmH9XsxWxQ=; b=a1c91sRgQnEQxKto/7Jx6EmVW6MSiLh3Hg91hpNfqyyA/YP+NeYlJo1W zfA/fyOJx9hqVkIH5yACX76YSk4TusA6Lk0hqdyQWgI/OA3rPI+FHRIN8 TwJQhMWFFKQMtdDGmBfrzuyyW2tztTBrGQ6nJzK7SrbwBcweEo9ipUIN0 QgJ1+N0CeMdhEmrqJznPfM/cok8PkpU1LyrH+WxyccAKVXlHGTN3+/dA7 dNmNwOhGRyJoHsO9miX4SaUP853hKxTAPwgccDz4hFDNCjioj3fjzL+Wj JIvPTxwOy0FTyDo9CFX51DbY5+Iz5mBgnWNBiA+H7OiLAxnT6syaAH312 A==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="332620544" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="332620544" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:11 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861119" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861119" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:06 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id EDF1F1046BE; Tue, 18 Oct 2022 14:34:03 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 01/15] x86/mm: Fix CR3_ADDR_MASK Date: Tue, 18 Oct 2022 14:33:44 +0300 Message-Id: <20221018113358.7833-2-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The mask must not include bits above physical address mask. These bits are reserved and can be used for other things. Bits 61 and 62 are used for Linear Address Masking. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe Reviewed-by: Alexander Potapenko Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/processor-flags.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/= processor-flags.h index 02c2cbda4a74..a7f3d9100adb 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -35,7 +35,7 @@ */ #ifdef CONFIG_X86_64 /* Mask off the address space ID and SME encryption bits. */ -#define CR3_ADDR_MASK __sme_clr(0x7FFFFFFFFFFFF000ull) +#define CR3_ADDR_MASK __sme_clr(PHYSICAL_PAGE_MASK) #define CR3_PCID_MASK 0xFFFull #define CR3_NOFLUSH BIT_ULL(63) =20 --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D1AFC4332F for ; Tue, 18 Oct 2022 11:37:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230305AbiJRLhf (ORCPT ); Tue, 18 Oct 2022 07:37:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229834AbiJRLha (ORCPT ); Tue, 18 Oct 2022 07:37:30 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2AAFBBE20 for ; Tue, 18 Oct 2022 04:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666093025; x=1697629025; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7qeZVouD+LQqNvYdTdPAJZv4Un9wdAzppe5kV3GbELE=; b=ftu7jpDFhwJyvT/jiqamwVXex080M6OCvEtzVJpe/MIGgWa9ugpgjvUz kTJSE8X10GafU3byJ65uNBCmiNtswaO4xAZ5dQ89gHrilideEChmbhzPb Shor+OlrwABuhwCm3v3S1QfY2s4M56fLXEyLj0Pu/LVcGkMe+ghXdbCfQ 6xsFyxRjDBjwwDbUX9PmPhQwEd285os0q41wk3ZJQ0OuPQlDiJtv5HGK6 SoN2bAW035CVp76jn8Fo6RclgTBF5vI6VwVhWZ5kT5l/rxIUdLwwCTD2W PlC/REdWUFIYdwO0anY/QVHpAdQ2cyXPPSpMrZbzovuhSo5mSbcGWBrFs w==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="332620547" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="332620547" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:11 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861121" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861121" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:06 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 04B111046BF; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 02/15] x86: CPUID and CR3/CR4 flags for Linear Address Masking Date: Tue, 18 Oct 2022 14:33:45 +0300 Message-Id: <20221018113358.7833-3-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enumerate Linear Address Masking and provide defines for CR3 and CR4 flags. Signed-off-by: Kirill A. Shutemov Reviewed-by: Alexander Potapenko Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/processor-flags.h | 2 ++ arch/x86/include/uapi/asm/processor-flags.h | 6 ++++++ 3 files changed, 9 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index b71f4f2ecdd5..265805e71806 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/arch/x86/include/asm/processor-flags.h b/arch/x86/include/asm/= processor-flags.h index a7f3d9100adb..d8cccadc83a6 100644 --- a/arch/x86/include/asm/processor-flags.h +++ b/arch/x86/include/asm/processor-flags.h @@ -28,6 +28,8 @@ * On systems with SME, one bit (in a variable position!) is stolen to ind= icate * that the top-level paging structure is encrypted. * + * On systemms with LAM, bits 61 and 62 are used to indicate LAM mode. + * * All of the remaining bits indicate the physical address of the top-level * paging structure. * diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include= /uapi/asm/processor-flags.h index c47cc7f2feeb..d898432947ff 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -82,6 +82,10 @@ #define X86_CR3_PCID_BITS 12 #define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL)) =20 +#define X86_CR3_LAM_U57_BIT 61 /* Activate LAM for userspace, 62:57 bits m= asked */ +#define X86_CR3_LAM_U57 _BITULL(X86_CR3_LAM_U57_BIT) +#define X86_CR3_LAM_U48_BIT 62 /* Activate LAM for userspace, 62:48 bits m= asked */ +#define X86_CR3_LAM_U48 _BITULL(X86_CR3_LAM_U48_BIT) #define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */ #define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT) =20 @@ -132,6 +136,8 @@ #define X86_CR4_PKE _BITUL(X86_CR4_PKE_BIT) #define X86_CR4_CET_BIT 23 /* enable Control-flow Enforcement Technology = */ #define X86_CR4_CET _BITUL(X86_CR4_CET_BIT) +#define X86_CR4_LAM_SUP_BIT 28 /* LAM for supervisor pointers */ +#define X86_CR4_LAM_SUP _BITUL(X86_CR4_LAM_SUP_BIT) =20 /* * x86-64 Task Priority Register, CR8 --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DD4EC4332F for ; Tue, 18 Oct 2022 11:37:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230318AbiJRLhs (ORCPT ); Tue, 18 Oct 2022 07:37:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35098 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230310AbiJRLho (ORCPT ); Tue, 18 Oct 2022 07:37:44 -0400 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36AD786F94 for ; Tue, 18 Oct 2022 04:37:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666093039; x=1697629039; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5MPChFauMs1s1DfrpOjLtQAJkHTo9iMj4SeNYDjzaIc=; b=HZ7iZ7cmjoMSBREaiL/wlZWaV14e4GvFsf1XxzHFAeOOHqU4yqaOBs2i mndegStiCPqupezaunN0epUqBEUmsam4twuu2I9JdpENqVoM76a8g0opM AcCzPEDiyc1Ia5VjyD6MRImeiE0ysJpEiHyqPKmd9ZcqT3LttCja5dw0L Zr5xycCEgPDXR703LWb0ZLSfn7kht7aWtGNh7h6Rvly2u1FyJwQRgMOA1 tj+L6qN4GexsH/UULbihz4/odPNSgiBWzINyJQiaBfEAPSNPBPCJhaODF 5sJc1qa/Qt1RkELAhxViOf49wPNb1LqudsQOe97IIaD1Oxmz9qdNAVZ4A A==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="332620550" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="332620550" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:11 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861124" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861124" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:06 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 0FDCA1046CA; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 03/15] mm: Pass down mm_struct to untagged_addr() Date: Tue, 18 Oct 2022 14:33:46 +0300 Message-Id: <20221018113358.7833-4-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Intel Linear Address Masking (LAM) brings per-mm untagging rules. Pass down mm_struct to the untagging helper. It will help to apply untagging policy correctly. In most cases, current->mm is the one to use, but there are some exceptions, such as get_user_page_remote(). Move dummy implementation of untagged_addr() from to . can override the implementation. Moving the dummy header outside helps to avoid header hell if you need to defer mm_struct within the helper. Signed-off-by: Kirill A. Shutemov Reviewed-by: Rick Edgecombe Reviewed-by: Alexander Potapenko Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/arm64/include/asm/memory.h | 4 ++-- arch/arm64/include/asm/signal.h | 2 +- arch/arm64/include/asm/uaccess.h | 2 +- arch/arm64/kernel/hw_breakpoint.c | 2 +- arch/arm64/kernel/traps.c | 4 ++-- arch/arm64/mm/fault.c | 10 +++++----- arch/sparc/include/asm/pgtable_64.h | 2 +- arch/sparc/include/asm/uaccess_64.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- drivers/gpu/drm/radeon/radeon_gem.c | 2 +- drivers/infiniband/hw/mlx4/mr.c | 2 +- drivers/media/common/videobuf2/frame_vector.c | 2 +- drivers/media/v4l2-core/videobuf-dma-contig.c | 2 +- drivers/staging/media/atomisp/pci/hmm/hmm_bo.c | 2 +- drivers/tee/tee_shm.c | 2 +- drivers/vfio/vfio_iommu_type1.c | 2 +- fs/proc/task_mmu.c | 2 +- include/linux/mm.h | 11 ----------- include/linux/uaccess.h | 15 +++++++++++++++ lib/strncpy_from_user.c | 2 +- lib/strnlen_user.c | 2 +- mm/gup.c | 6 +++--- mm/madvise.c | 2 +- mm/mempolicy.c | 6 +++--- mm/migrate.c | 2 +- mm/mincore.c | 2 +- mm/mlock.c | 4 ++-- mm/mmap.c | 2 +- mm/mprotect.c | 2 +- mm/mremap.c | 2 +- mm/msync.c | 2 +- virt/kvm/kvm_main.c | 2 +- 33 files changed, 58 insertions(+), 52 deletions(-) diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memor= y.h index 9dd08cd339c3..5b24ef93c6b9 100644 --- a/arch/arm64/include/asm/memory.h +++ b/arch/arm64/include/asm/memory.h @@ -227,8 +227,8 @@ static inline unsigned long kaslr_offset(void) #define __untagged_addr(addr) \ ((__force __typeof__(addr))sign_extend64((__force u64)(addr), 55)) =20 -#define untagged_addr(addr) ({ \ - u64 __addr =3D (__force u64)(addr); \ +#define untagged_addr(mm, addr) ({ \ + u64 __addr =3D (__force u64)(addr); \ __addr &=3D __untagged_addr(__addr); \ (__force __typeof__(addr))__addr; \ }) diff --git a/arch/arm64/include/asm/signal.h b/arch/arm64/include/asm/signa= l.h index ef449f5f4ba8..0899c355c398 100644 --- a/arch/arm64/include/asm/signal.h +++ b/arch/arm64/include/asm/signal.h @@ -18,7 +18,7 @@ static inline void __user *arch_untagged_si_addr(void __u= ser *addr, if (sig =3D=3D SIGTRAP && si_code =3D=3D TRAP_BRKPT) return addr; =20 - return untagged_addr(addr); + return untagged_addr(current->mm, addr); } #define arch_untagged_si_addr arch_untagged_si_addr =20 diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uacc= ess.h index 5c7b2f9d5913..122d894a4136 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -44,7 +44,7 @@ static inline int access_ok(const void __user *addr, unsi= gned long size) */ if (IS_ENABLED(CONFIG_ARM64_TAGGED_ADDR_ABI) && (current->flags & PF_KTHREAD || test_thread_flag(TIF_TAGGED_ADDR))) - addr =3D untagged_addr(addr); + addr =3D untagged_addr(current->mm, addr); =20 return likely(__access_ok(addr, size)); } diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_break= point.c index b29a311bb055..d637cee7b771 100644 --- a/arch/arm64/kernel/hw_breakpoint.c +++ b/arch/arm64/kernel/hw_breakpoint.c @@ -715,7 +715,7 @@ static u64 get_distance_from_watchpoint(unsigned long a= ddr, u64 val, u64 wp_low, wp_high; u32 lens, lene; =20 - addr =3D untagged_addr(addr); + addr =3D untagged_addr(current->mm, addr); =20 lens =3D __ffs(ctrl->len); lene =3D __fls(ctrl->len); diff --git a/arch/arm64/kernel/traps.c b/arch/arm64/kernel/traps.c index 23d281ed7621..f40f3885b674 100644 --- a/arch/arm64/kernel/traps.c +++ b/arch/arm64/kernel/traps.c @@ -477,7 +477,7 @@ void arm64_notify_segfault(unsigned long addr) int code; =20 mmap_read_lock(current->mm); - if (find_vma(current->mm, untagged_addr(addr)) =3D=3D NULL) + if (find_vma(current->mm, untagged_addr(current->mm, addr)) =3D=3D NULL) code =3D SEGV_MAPERR; else code =3D SEGV_ACCERR; @@ -551,7 +551,7 @@ static void user_cache_maint_handler(unsigned long esr,= struct pt_regs *regs) int ret =3D 0; =20 tagged_address =3D pt_regs_read_reg(regs, rt); - address =3D untagged_addr(tagged_address); + address =3D untagged_addr(current->mm, tagged_address); =20 switch (crm) { case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 5b391490e045..b8799e9c7e1b 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -454,7 +454,7 @@ static void set_thread_esr(unsigned long address, unsig= ned long esr) static void do_bad_area(unsigned long far, unsigned long esr, struct pt_regs *regs) { - unsigned long addr =3D untagged_addr(far); + unsigned long addr =3D untagged_addr(current->mm, far); =20 /* * If we are in kernel mode at this point, we have no context to @@ -524,7 +524,7 @@ static int __kprobes do_page_fault(unsigned long far, u= nsigned long esr, vm_fault_t fault; unsigned long vm_flags; unsigned int mm_flags =3D FAULT_FLAG_DEFAULT; - unsigned long addr =3D untagged_addr(far); + unsigned long addr =3D untagged_addr(mm, far); =20 if (kprobe_page_fault(regs, esr)) return 0; @@ -679,7 +679,7 @@ static int __kprobes do_translation_fault(unsigned long= far, unsigned long esr, struct pt_regs *regs) { - unsigned long addr =3D untagged_addr(far); + unsigned long addr =3D untagged_addr(current->mm, far); =20 if (is_ttbr0_addr(addr)) return do_page_fault(far, esr, regs); @@ -726,7 +726,7 @@ static int do_sea(unsigned long far, unsigned long esr,= struct pt_regs *regs) * UNKNOWN for synchronous external aborts. Mask them out now * so that userspace doesn't see them. */ - siaddr =3D untagged_addr(far); + siaddr =3D untagged_addr(current->mm, far); } arm64_notify_die(inf->name, regs, inf->sig, inf->code, siaddr, esr); =20 @@ -816,7 +816,7 @@ static const struct fault_info fault_info[] =3D { void do_mem_abort(unsigned long far, unsigned long esr, struct pt_regs *re= gs) { const struct fault_info *inf =3D esr_to_fault_info(esr); - unsigned long addr =3D untagged_addr(far); + unsigned long addr =3D untagged_addr(current->mm, far); =20 if (!inf->fn(far, esr, regs)) return; diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/p= gtable_64.h index a779418ceba9..aa996ffe5c8c 100644 --- a/arch/sparc/include/asm/pgtable_64.h +++ b/arch/sparc/include/asm/pgtable_64.h @@ -1052,7 +1052,7 @@ static inline unsigned long __untagged_addr(unsigned = long start) =20 return start; } -#define untagged_addr(addr) \ +#define untagged_addr(mm, addr) \ ((__typeof__(addr))(__untagged_addr((unsigned long)(addr)))) =20 static inline bool pte_access_permitted(pte_t pte, bool write) diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/u= access_64.h index 94266a5c5b04..b825a5dd0210 100644 --- a/arch/sparc/include/asm/uaccess_64.h +++ b/arch/sparc/include/asm/uaccess_64.h @@ -8,8 +8,10 @@ =20 #include #include +#include #include #include +#include =20 #include #include diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu= /drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 978d3970b5cc..173f0b5ccba1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1659,7 +1659,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { if (!offset || !*offset) return -EINVAL; - user_addr =3D untagged_addr(*offset); + user_addr =3D untagged_addr(current->mm, *offset); } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { bo_type =3D ttm_bo_type_sg; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_gem.c index 8ef31d687ef3..691dfb3f2c0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -382,7 +382,7 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, vo= id *data, uint32_t handle; int r; =20 - args->addr =3D untagged_addr(args->addr); + args->addr =3D untagged_addr(current->mm, args->addr); =20 if (offset_in_page(args->addr | args->size)) return -EINVAL; diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/r= adeon_gem.c index 261fcbae88d7..cba2f4b19838 100644 --- a/drivers/gpu/drm/radeon/radeon_gem.c +++ b/drivers/gpu/drm/radeon/radeon_gem.c @@ -371,7 +371,7 @@ int radeon_gem_userptr_ioctl(struct drm_device *dev, vo= id *data, uint32_t handle; int r; =20 - args->addr =3D untagged_addr(args->addr); + args->addr =3D untagged_addr(current->mm, args->addr); =20 if (offset_in_page(args->addr | args->size)) return -EINVAL; diff --git a/drivers/infiniband/hw/mlx4/mr.c b/drivers/infiniband/hw/mlx4/m= r.c index a40bf58bcdd3..383ac9e40dfa 100644 --- a/drivers/infiniband/hw/mlx4/mr.c +++ b/drivers/infiniband/hw/mlx4/mr.c @@ -379,7 +379,7 @@ static struct ib_umem *mlx4_get_umem_mr(struct ib_devic= e *device, u64 start, * again */ if (!ib_access_writable(access_flags)) { - unsigned long untagged_start =3D untagged_addr(start); + unsigned long untagged_start =3D untagged_addr(current->mm, start); struct vm_area_struct *vma; =20 mmap_read_lock(current->mm); diff --git a/drivers/media/common/videobuf2/frame_vector.c b/drivers/media/= common/videobuf2/frame_vector.c index 542dde9d2609..7e62f7a2555d 100644 --- a/drivers/media/common/videobuf2/frame_vector.c +++ b/drivers/media/common/videobuf2/frame_vector.c @@ -47,7 +47,7 @@ int get_vaddr_frames(unsigned long start, unsigned int nr= _frames, if (WARN_ON_ONCE(nr_frames > vec->nr_allocated)) nr_frames =3D vec->nr_allocated; =20 - start =3D untagged_addr(start); + start =3D untagged_addr(mm, start); =20 ret =3D pin_user_pages_fast(start, nr_frames, FOLL_FORCE | FOLL_WRITE | FOLL_LONGTERM, diff --git a/drivers/media/v4l2-core/videobuf-dma-contig.c b/drivers/media/= v4l2-core/videobuf-dma-contig.c index 52312ce2ba05..a1444f8afa05 100644 --- a/drivers/media/v4l2-core/videobuf-dma-contig.c +++ b/drivers/media/v4l2-core/videobuf-dma-contig.c @@ -157,8 +157,8 @@ static void videobuf_dma_contig_user_put(struct videobu= f_dma_contig_memory *mem) static int videobuf_dma_contig_user_get(struct videobuf_dma_contig_memory = *mem, struct videobuf_buffer *vb) { - unsigned long untagged_baddr =3D untagged_addr(vb->baddr); struct mm_struct *mm =3D current->mm; + unsigned long untagged_baddr =3D untagged_addr(mm, vb->baddr); struct vm_area_struct *vma; unsigned long prev_pfn, this_pfn; unsigned long pages_done, user_address; diff --git a/drivers/staging/media/atomisp/pci/hmm/hmm_bo.c b/drivers/stagi= ng/media/atomisp/pci/hmm/hmm_bo.c index f50494123f03..a43c65950554 100644 --- a/drivers/staging/media/atomisp/pci/hmm/hmm_bo.c +++ b/drivers/staging/media/atomisp/pci/hmm/hmm_bo.c @@ -794,7 +794,7 @@ static int alloc_user_pages(struct hmm_buffer_object *b= o, * and map to user space */ =20 - userptr =3D untagged_addr(userptr); + userptr =3D untagged_addr(current->mm, userptr); =20 if (vma->vm_flags & (VM_IO | VM_PFNMAP)) { page_nr =3D pin_user_pages((unsigned long)userptr, bo->pgnr, diff --git a/drivers/tee/tee_shm.c b/drivers/tee/tee_shm.c index 27295bda3e0b..5c85445f3a65 100644 --- a/drivers/tee/tee_shm.c +++ b/drivers/tee/tee_shm.c @@ -262,7 +262,7 @@ register_shm_helper(struct tee_context *ctx, unsigned l= ong addr, shm->flags =3D flags; shm->ctx =3D ctx; shm->id =3D id; - addr =3D untagged_addr(addr); + addr =3D untagged_addr(current->mm, addr); start =3D rounddown(addr, PAGE_SIZE); shm->offset =3D addr - start; shm->size =3D length; diff --git a/drivers/vfio/vfio_iommu_type1.c b/drivers/vfio/vfio_iommu_type= 1.c index 23c24fe98c00..74b6aecea8b0 100644 --- a/drivers/vfio/vfio_iommu_type1.c +++ b/drivers/vfio/vfio_iommu_type1.c @@ -573,7 +573,7 @@ static int vaddr_get_pfns(struct mm_struct *mm, unsigne= d long vaddr, goto done; } =20 - vaddr =3D untagged_addr(vaddr); + vaddr =3D untagged_addr(mm, vaddr); =20 retry: vma =3D vma_lookup(mm, vaddr); diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c index 8b4f3073f8f5..665e36885f21 100644 --- a/fs/proc/task_mmu.c +++ b/fs/proc/task_mmu.c @@ -1685,7 +1685,7 @@ static ssize_t pagemap_read(struct file *file, char _= _user *buf, /* watch out for wraparound */ start_vaddr =3D end_vaddr; if (svpfn <=3D (ULONG_MAX >> PAGE_SHIFT)) - start_vaddr =3D untagged_addr(svpfn << PAGE_SHIFT); + start_vaddr =3D untagged_addr(mm, svpfn << PAGE_SHIFT); =20 /* Ensure the address is inside the task */ if (start_vaddr > mm->task_size) diff --git a/include/linux/mm.h b/include/linux/mm.h index 8bbcccbc5565..bfac5a166cb8 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -95,17 +95,6 @@ extern int mmap_rnd_compat_bits __read_mostly; #include #include =20 -/* - * Architectures that support memory tagging (assigning tags to memory reg= ions, - * embedding these tags into addresses that point to these memory regions,= and - * checking that the memory and the pointer tags match on memory accesses) - * redefine this macro to strip tags from pointers. - * It's defined as noop for architectures that don't support memory taggin= g. - */ -#ifndef untagged_addr -#define untagged_addr(addr) (addr) -#endif - #ifndef __pa_symbol #define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) #endif diff --git a/include/linux/uaccess.h b/include/linux/uaccess.h index afb18f198843..46680189d761 100644 --- a/include/linux/uaccess.h +++ b/include/linux/uaccess.h @@ -10,6 +10,21 @@ =20 #include =20 +/* + * Architectures that support memory tagging (assigning tags to memory reg= ions, + * embedding these tags into addresses that point to these memory regions,= and + * checking that the memory and the pointer tags match on memory accesses) + * redefine this macro to strip tags from pointers. + * + * Passing down mm_struct allows to define untagging rules on per-process + * basis. + * + * It's defined as noop for architectures that don't support memory taggin= g. + */ +#ifndef untagged_addr +#define untagged_addr(mm, addr) (addr) +#endif + /* * Architectures should provide two primitives (raw_copy_{to,from}_user()) * and get rid of their private instances of copy_{to,from}_user() and diff --git a/lib/strncpy_from_user.c b/lib/strncpy_from_user.c index 6432b8c3e431..6e1e2aa0c994 100644 --- a/lib/strncpy_from_user.c +++ b/lib/strncpy_from_user.c @@ -121,7 +121,7 @@ long strncpy_from_user(char *dst, const char __user *sr= c, long count) return 0; =20 max_addr =3D TASK_SIZE_MAX; - src_addr =3D (unsigned long)untagged_addr(src); + src_addr =3D (unsigned long)untagged_addr(current->mm, src); if (likely(src_addr < max_addr)) { unsigned long max =3D max_addr - src_addr; long retval; diff --git a/lib/strnlen_user.c b/lib/strnlen_user.c index feeb935a2299..abc096a68f05 100644 --- a/lib/strnlen_user.c +++ b/lib/strnlen_user.c @@ -97,7 +97,7 @@ long strnlen_user(const char __user *str, long count) return 0; =20 max_addr =3D TASK_SIZE_MAX; - src_addr =3D (unsigned long)untagged_addr(str); + src_addr =3D (unsigned long)untagged_addr(current->mm, str); if (likely(src_addr < max_addr)) { unsigned long max =3D max_addr - src_addr; long retval; diff --git a/mm/gup.c b/mm/gup.c index fe195d47de74..f585e4a185ca 100644 --- a/mm/gup.c +++ b/mm/gup.c @@ -1168,7 +1168,7 @@ static long __get_user_pages(struct mm_struct *mm, if (!nr_pages) return 0; =20 - start =3D untagged_addr(start); + start =3D untagged_addr(mm, start); =20 VM_BUG_ON(!!pages !=3D !!(gup_flags & (FOLL_GET | FOLL_PIN))); =20 @@ -1342,7 +1342,7 @@ int fixup_user_fault(struct mm_struct *mm, struct vm_area_struct *vma; vm_fault_t ret; =20 - address =3D untagged_addr(address); + address =3D untagged_addr(mm, address); =20 if (unlocked) fault_flags |=3D FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE; @@ -3027,7 +3027,7 @@ static int internal_get_user_pages_fast(unsigned long= start, if (!(gup_flags & FOLL_FAST_ONLY)) might_lock_read(¤t->mm->mmap_lock); =20 - start =3D untagged_addr(start) & PAGE_MASK; + start =3D untagged_addr(current->mm, start) & PAGE_MASK; len =3D nr_pages << PAGE_SHIFT; if (check_add_overflow(start, len, &end)) return 0; diff --git a/mm/madvise.c b/mm/madvise.c index 2baa93ca2310..1319a18da8bc 100644 --- a/mm/madvise.c +++ b/mm/madvise.c @@ -1382,7 +1382,7 @@ int do_madvise(struct mm_struct *mm, unsigned long st= art, size_t len_in, int beh size_t len; struct blk_plug plug; =20 - start =3D untagged_addr(start); + start =3D untagged_addr(mm, start); =20 if (!madvise_behavior_valid(behavior)) return -EINVAL; diff --git a/mm/mempolicy.c b/mm/mempolicy.c index a937eaec5b68..4fdeef477fbd 100644 --- a/mm/mempolicy.c +++ b/mm/mempolicy.c @@ -1467,7 +1467,7 @@ static long kernel_mbind(unsigned long start, unsigne= d long len, int lmode =3D mode; int err; =20 - start =3D untagged_addr(start); + start =3D untagged_addr(current->mm, start); err =3D sanitize_mpol_flags(&lmode, &mode_flags); if (err) return err; @@ -1491,7 +1491,7 @@ SYSCALL_DEFINE4(set_mempolicy_home_node, unsigned lon= g, start, unsigned long, le int err =3D -ENOENT; VMA_ITERATOR(vmi, mm, start); =20 - start =3D untagged_addr(start); + start =3D untagged_addr(mm, start); if (start & ~PAGE_MASK) return -EINVAL; /* @@ -1692,7 +1692,7 @@ static int kernel_get_mempolicy(int __user *policy, if (nmask !=3D NULL && maxnode < nr_node_ids) return -EINVAL; =20 - addr =3D untagged_addr(addr); + addr =3D untagged_addr(current->mm, addr); =20 err =3D do_get_mempolicy(&pval, &nodes, addr, flags); =20 diff --git a/mm/migrate.c b/mm/migrate.c index 1379e1912772..8e7823bef31d 100644 --- a/mm/migrate.c +++ b/mm/migrate.c @@ -1795,7 +1795,7 @@ static int do_pages_move(struct mm_struct *mm, nodema= sk_t task_nodes, goto out_flush; if (get_user(node, nodes + i)) goto out_flush; - addr =3D (unsigned long)untagged_addr(p); + addr =3D (unsigned long)untagged_addr(mm, p); =20 err =3D -ENODEV; if (node < 0 || node >=3D MAX_NUMNODES) diff --git a/mm/mincore.c b/mm/mincore.c index fa200c14185f..72c55bd9d184 100644 --- a/mm/mincore.c +++ b/mm/mincore.c @@ -236,7 +236,7 @@ SYSCALL_DEFINE3(mincore, unsigned long, start, size_t, = len, unsigned long pages; unsigned char *tmp; =20 - start =3D untagged_addr(start); + start =3D untagged_addr(current->mm, start); =20 /* Check the start address: needs to be page-aligned.. */ if (start & ~PAGE_MASK) diff --git a/mm/mlock.c b/mm/mlock.c index 7032f6dd0ce1..d969703c08ff 100644 --- a/mm/mlock.c +++ b/mm/mlock.c @@ -570,7 +570,7 @@ static __must_check int do_mlock(unsigned long start, s= ize_t len, vm_flags_t fla unsigned long lock_limit; int error =3D -ENOMEM; =20 - start =3D untagged_addr(start); + start =3D untagged_addr(current->mm, start); =20 if (!can_do_mlock()) return -EPERM; @@ -633,7 +633,7 @@ SYSCALL_DEFINE2(munlock, unsigned long, start, size_t, = len) { int ret; =20 - start =3D untagged_addr(start); + start =3D untagged_addr(current->mm, start); =20 len =3D PAGE_ALIGN(len + (offset_in_page(start))); start &=3D PAGE_MASK; diff --git a/mm/mmap.c b/mm/mmap.c index bf2122af94e7..bb8037840160 100644 --- a/mm/mmap.c +++ b/mm/mmap.c @@ -2796,7 +2796,7 @@ EXPORT_SYMBOL(vm_munmap); =20 SYSCALL_DEFINE2(munmap, unsigned long, addr, size_t, len) { - addr =3D untagged_addr(addr); + addr =3D untagged_addr(current->mm, addr); return __vm_munmap(addr, len, true); } =20 diff --git a/mm/mprotect.c b/mm/mprotect.c index 668bfaa6ed2a..dee44e3a0527 100644 --- a/mm/mprotect.c +++ b/mm/mprotect.c @@ -680,7 +680,7 @@ static int do_mprotect_pkey(unsigned long start, size_t= len, struct mmu_gather tlb; MA_STATE(mas, ¤t->mm->mm_mt, 0, 0); =20 - start =3D untagged_addr(start); + start =3D untagged_addr(current->mm, start); =20 prot &=3D ~(PROT_GROWSDOWN|PROT_GROWSUP); if (grows =3D=3D (PROT_GROWSDOWN|PROT_GROWSUP)) /* can't be both */ diff --git a/mm/mremap.c b/mm/mremap.c index e465ffe279bb..81c857281a52 100644 --- a/mm/mremap.c +++ b/mm/mremap.c @@ -909,7 +909,7 @@ SYSCALL_DEFINE5(mremap, unsigned long, addr, unsigned l= ong, old_len, * * See Documentation/arm64/tagged-address-abi.rst for more information. */ - addr =3D untagged_addr(addr); + addr =3D untagged_addr(mm, addr); =20 if (flags & ~(MREMAP_FIXED | MREMAP_MAYMOVE | MREMAP_DONTUNMAP)) return ret; diff --git a/mm/msync.c b/mm/msync.c index ac4c9bfea2e7..f941e9bb610f 100644 --- a/mm/msync.c +++ b/mm/msync.c @@ -37,7 +37,7 @@ SYSCALL_DEFINE3(msync, unsigned long, start, size_t, len,= int, flags) int unmapped_error =3D 0; int error =3D -EINVAL; =20 - start =3D untagged_addr(start); + start =3D untagged_addr(mm, start); =20 if (flags & ~(MS_ASYNC | MS_INVALIDATE | MS_SYNC)) goto out; diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index e30f1b4ecfa5..8c86b06b35da 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -1945,7 +1945,7 @@ int __kvm_set_memory_region(struct kvm *kvm, return -EINVAL; /* We can read the guest memory with __xxx_user() later on. */ if ((mem->userspace_addr & (PAGE_SIZE - 1)) || - (mem->userspace_addr !=3D untagged_addr(mem->userspace_addr)) || + (mem->userspace_addr !=3D untagged_addr(kvm->mm, mem->userspace_addr)= ) || !access_ok((void __user *)(unsigned long)mem->userspace_addr, mem->memory_size)) return -EINVAL; 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Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 04/15] x86/mm: Handle LAM on context switch Date: Tue, 18 Oct 2022 14:33:47 +0300 Message-Id: <20221018113358.7833-5-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Linear Address Masking mode for userspace pointers encoded in CR3 bits. The mode is selected per-process and stored in mm_context_t. switch_mm_irqs_off() now respects selected LAM mode and constructs CR3 accordingly. The active LAM mode gets recorded in the tlb_state. Signed-off-by: Kirill A. Shutemov Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mmu.h | 3 ++ arch/x86/include/asm/mmu_context.h | 24 +++++++++++++++ arch/x86/include/asm/tlbflush.h | 35 ++++++++++++++++++++++ arch/x86/mm/tlb.c | 48 ++++++++++++++++++++---------- 4 files changed, 94 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 5d7494631ea9..002889ca8978 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -40,6 +40,9 @@ typedef struct { =20 #ifdef CONFIG_X86_64 unsigned short flags; + + /* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */ + unsigned long lam_cr3_mask; #endif =20 struct mutex lock; diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index b8d40ddeab00..69c943b2ae90 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -91,6 +91,29 @@ static inline void switch_ldt(struct mm_struct *prev, st= ruct mm_struct *next) } #endif =20 +#ifdef CONFIG_X86_64 +static inline unsigned long mm_lam_cr3_mask(struct mm_struct *mm) +{ + return mm->context.lam_cr3_mask; +} + +static inline void dup_lam(struct mm_struct *oldmm, struct mm_struct *mm) +{ + mm->context.lam_cr3_mask =3D oldmm->context.lam_cr3_mask; +} + +#else + +static inline unsigned long mm_lam_cr3_mask(struct mm_struct *mm) +{ + return 0; +} + +static inline void dup_lam(struct mm_struct *oldmm, struct mm_struct *mm) +{ +} +#endif + #define enter_lazy_tlb enter_lazy_tlb extern void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk); =20 @@ -168,6 +191,7 @@ static inline int arch_dup_mmap(struct mm_struct *oldmm= , struct mm_struct *mm) { arch_dup_pkeys(oldmm, mm); paravirt_arch_dup_mmap(oldmm, mm); + dup_lam(oldmm, mm); return ldt_dup_context(oldmm, mm); } =20 diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflus= h.h index cda3118f3b27..1ad080163363 100644 --- a/arch/x86/include/asm/tlbflush.h +++ b/arch/x86/include/asm/tlbflush.h @@ -101,6 +101,16 @@ struct tlb_state { */ bool invalidate_other; =20 +#ifdef CONFIG_X86_64 + /* + * Active LAM mode. + * + * X86_CR3_LAM_U57/U48 shifted right by X86_CR3_LAM_U57_BIT or 0 if LAM + * disabled. + */ + u8 lam; +#endif + /* * Mask that contains TLB_NR_DYN_ASIDS+1 bits to indicate * the corresponding user PCID needs a flush next time we @@ -357,6 +367,30 @@ static inline bool huge_pmd_needs_flush(pmd_t oldpmd, = pmd_t newpmd) } #define huge_pmd_needs_flush huge_pmd_needs_flush =20 +#ifdef CONFIG_X86_64 +static inline unsigned long tlbstate_lam_cr3_mask(void) +{ + unsigned long lam =3D this_cpu_read(cpu_tlbstate.lam); + + return lam << X86_CR3_LAM_U57_BIT; +} + +static inline void set_tlbstate_cr3_lam_mask(unsigned long mask) +{ + this_cpu_write(cpu_tlbstate.lam, mask >> X86_CR3_LAM_U57_BIT); +} + +#else + +static inline unsigned long tlbstate_lam_cr3_mask(void) +{ + return 0; +} + +static inline void set_tlbstate_cr3_lam_mask(u64 mask) +{ +} +#endif #endif /* !MODULE */ =20 static inline void __native_tlb_flush_global(unsigned long cr4) @@ -364,4 +398,5 @@ static inline void __native_tlb_flush_global(unsigned l= ong cr4) native_write_cr4(cr4 ^ X86_CR4_PGE); native_write_cr4(cr4); } + #endif /* _ASM_X86_TLBFLUSH_H */ diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index c1e31e9a85d7..d6c9c15d2ad2 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -154,26 +154,30 @@ static inline u16 user_pcid(u16 asid) return ret; } =20 -static inline unsigned long build_cr3(pgd_t *pgd, u16 asid) +static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long = lam) { + unsigned long cr3 =3D __sme_pa(pgd) | lam; + if (static_cpu_has(X86_FEATURE_PCID)) { - return __sme_pa(pgd) | kern_pcid(asid); + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE); + cr3 |=3D kern_pcid(asid); } else { VM_WARN_ON_ONCE(asid !=3D 0); - return __sme_pa(pgd); } + + return cr3; } =20 -static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid) +static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid, + unsigned long lam) { - VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE); /* * Use boot_cpu_has() instead of this_cpu_has() as this function * might be called during early boot. This should work even after * boot because all CPU's the have same capabilities: */ VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID)); - return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH; + return build_cr3(pgd, asid, lam) | CR3_NOFLUSH; } =20 /* @@ -274,15 +278,16 @@ static inline void invalidate_user_asid(u16 asid) (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask)); } =20 -static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush) +static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, unsigned long lam, + bool need_flush) { unsigned long new_mm_cr3; =20 if (need_flush) { invalidate_user_asid(new_asid); - new_mm_cr3 =3D build_cr3(pgdir, new_asid); + new_mm_cr3 =3D build_cr3(pgdir, new_asid, lam); } else { - new_mm_cr3 =3D build_cr3_noflush(pgdir, new_asid); + new_mm_cr3 =3D build_cr3_noflush(pgdir, new_asid, lam); } =20 /* @@ -491,6 +496,8 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct = mm_struct *next, { struct mm_struct *real_prev =3D this_cpu_read(cpu_tlbstate.loaded_mm); u16 prev_asid =3D this_cpu_read(cpu_tlbstate.loaded_mm_asid); + unsigned long prev_lam =3D tlbstate_lam_cr3_mask(); + unsigned long new_lam =3D mm_lam_cr3_mask(next); bool was_lazy =3D this_cpu_read(cpu_tlbstate_shared.is_lazy); unsigned cpu =3D smp_processor_id(); u64 next_tlb_gen; @@ -520,7 +527,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct = mm_struct *next, * isn't free. */ #ifdef CONFIG_DEBUG_VM - if (WARN_ON_ONCE(__read_cr3() !=3D build_cr3(real_prev->pgd, prev_asid)))= { + if (WARN_ON_ONCE(__read_cr3() !=3D build_cr3(real_prev->pgd, prev_asid, p= rev_lam))) { /* * If we were to BUG here, we'd be very likely to kill * the system so hard that we don't see the call trace. @@ -554,6 +561,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct = mm_struct *next, if (real_prev =3D=3D next) { VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=3D next->context.ctx_id); + VM_WARN_ON(prev_lam !=3D new_lam); =20 /* * Even in lazy TLB mode, the CPU should stay set in the @@ -622,15 +630,16 @@ void switch_mm_irqs_off(struct mm_struct *prev, struc= t mm_struct *next, barrier(); } =20 + set_tlbstate_cr3_lam_mask(new_lam); if (need_flush) { this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); - load_new_mm_cr3(next->pgd, new_asid, true); + load_new_mm_cr3(next->pgd, new_asid, new_lam, true); =20 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL); } else { /* The new ASID is already up to date. */ - load_new_mm_cr3(next->pgd, new_asid, false); + load_new_mm_cr3(next->pgd, new_asid, new_lam, false); =20 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0); } @@ -691,6 +700,10 @@ void initialize_tlbstate_and_flush(void) /* Assert that CR3 already references the right mm. */ WARN_ON((cr3 & CR3_ADDR_MASK) !=3D __pa(mm->pgd)); =20 + /* LAM expected to be disabled in CR3 and init_mm */ + WARN_ON(cr3 & (X86_CR3_LAM_U48 | X86_CR3_LAM_U57)); + WARN_ON(mm_lam_cr3_mask(&init_mm)); + /* * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization * doesn't work like other CR4 bits because it can only be set from @@ -699,8 +712,8 @@ void initialize_tlbstate_and_flush(void) WARN_ON(boot_cpu_has(X86_FEATURE_PCID) && !(cr4_read_shadow() & X86_CR4_PCIDE)); =20 - /* Force ASID 0 and force a TLB flush. */ - write_cr3(build_cr3(mm->pgd, 0)); + /* Disable LAM, force ASID 0 and force a TLB flush. */ + write_cr3(build_cr3(mm->pgd, 0, 0)); =20 /* Reinitialize tlbstate. */ this_cpu_write(cpu_tlbstate.last_user_mm_spec, LAST_USER_MM_INIT); @@ -708,6 +721,7 @@ void initialize_tlbstate_and_flush(void) this_cpu_write(cpu_tlbstate.next_asid, 1); this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id); this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen); + set_tlbstate_cr3_lam_mask(0); =20 for (i =3D 1; i < TLB_NR_DYN_ASIDS; i++) this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0); @@ -1071,8 +1085,10 @@ void flush_tlb_kernel_range(unsigned long start, uns= igned long end) */ unsigned long __get_current_cr3_fast(void) { - unsigned long cr3 =3D build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pg= d, - this_cpu_read(cpu_tlbstate.loaded_mm_asid)); + unsigned long cr3 =3D + build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd, + this_cpu_read(cpu_tlbstate.loaded_mm_asid), + tlbstate_lam_cr3_mask()); =20 /* For now, be very restrictive about when this can be called. */ VM_WARN_ON(in_nmi() || preemptible()); --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E12FEC4332F for ; Tue, 18 Oct 2022 11:36:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230259AbiJRLgb (ORCPT ); Tue, 18 Oct 2022 07:36:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230101AbiJRLfo (ORCPT ); Tue, 18 Oct 2022 07:35:44 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDEEDBA27D for ; Tue, 18 Oct 2022 04:35:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666092916; x=1697628916; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=URl4+yXuTZU7i5eHga9UDkYb72zi7S2whgUd+vZqeAk=; b=D+UwM9cnOKfHSbfnZXzEAOwkYc/ez5q3JUFT52pkj/PGAl6QIUbaMIOD z1P8zM72DEZRefp8wPNbcvvZZse4ic5R111jXENe5VMXHEN5/UqjIIzlC XLk7WoCwuKsmoIZloBPwUoeCzyYR02gbtC7laQvPG25O5JSfjFXtCm1ZE QvkwvMkxqpwpN3HdhGFbCVd+gLDgnafRxCZqwgJ9lX1tzjTzGeRUD8YDS m2qE2JyqNIx3LMjh7xCgY6Mgsx5FNMIMeZbtY042KtaIJBABhFoQKsZge qC6yRKR2XAEdM5Gh/hOWj/MhIPorUfQ+Q7ZB8fzWSJEZIyhOUgAdrbnO2 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="368105822" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368105822" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:17 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="691763173" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="691763173" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 252BC1046FB; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 05/15] x86/uaccess: Provide untagged_addr() and remove tags before address check Date: Tue, 18 Oct 2022 14:33:48 +0300 Message-Id: <20221018113358.7833-6-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" untagged_addr() is a helper used by the core-mm to strip tag bits and get the address to the canonical shape. In only handles userspace addresses. The untagging mask is stored in mmu_context and will be set on enabling LAM for the process. The tags must not be included into check whether it's okay to access the userspace address. Strip tags in access_ok(). get_user() and put_user() don't use access_ok(), but check access against TASK_SIZE directly in assembly. Strip tags, before calling into the assembly helper. Signed-off-by: Kirill A. Shutemov Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mmu.h | 3 +++ arch/x86/include/asm/mmu_context.h | 11 ++++++++ arch/x86/include/asm/uaccess.h | 42 +++++++++++++++++++++++++++--- arch/x86/kernel/process.c | 3 +++ 4 files changed, 56 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 002889ca8978..2fdb390040b5 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -43,6 +43,9 @@ typedef struct { =20 /* Active LAM mode: X86_CR3_LAM_U48 or X86_CR3_LAM_U57 or 0 (disabled) */ unsigned long lam_cr3_mask; + + /* Significant bits of the virtual address. Excludes tag bits. */ + u64 untag_mask; #endif =20 struct mutex lock; diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index 69c943b2ae90..5bd3d46685dc 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -100,6 +100,12 @@ static inline unsigned long mm_lam_cr3_mask(struct mm_= struct *mm) static inline void dup_lam(struct mm_struct *oldmm, struct mm_struct *mm) { mm->context.lam_cr3_mask =3D oldmm->context.lam_cr3_mask; + mm->context.untag_mask =3D oldmm->context.untag_mask; +} + +static inline void mm_reset_untag_mask(struct mm_struct *mm) +{ + mm->context.untag_mask =3D -1UL; } =20 #else @@ -112,6 +118,10 @@ static inline unsigned long mm_lam_cr3_mask(struct mm_= struct *mm) static inline void dup_lam(struct mm_struct *oldmm, struct mm_struct *mm) { } + +static inline void mm_reset_untag_mask(struct mm_struct *mm) +{ +} #endif =20 #define enter_lazy_tlb enter_lazy_tlb @@ -138,6 +148,7 @@ static inline int init_new_context(struct task_struct *= tsk, mm->context.execute_only_pkey =3D -1; } #endif + mm_reset_untag_mask(mm); init_new_context_ldt(mm); return 0; } diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index 8bc614cfe21b..c6062c07ccd2 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -21,6 +22,30 @@ static inline bool pagefault_disabled(void); # define WARN_ON_IN_IRQ() #endif =20 +#ifdef CONFIG_X86_64 +/* + * Mask out tag bits from the address. + * + * Magic with the 'sign' allows to untag userspace pointer without any bra= nches + * while leaving kernel addresses intact. + */ +#define untagged_addr(mm, addr) ({ \ + u64 __addr =3D (__force u64)(addr); \ + s64 sign =3D (s64)__addr >> 63; \ + __addr &=3D (mm)->context.untag_mask | sign; \ + (__force __typeof__(addr))__addr; \ +}) + +#define untagged_ptr(mm, ptr) ({ \ + u64 __ptrval =3D (__force u64)(ptr); \ + __ptrval =3D untagged_addr(mm, __ptrval); \ + (__force __typeof__(*(ptr)) *)__ptrval; \ +}) +#else +#define untagged_addr(mm, addr) (addr) +#define untagged_ptr(mm, ptr) (ptr) +#endif + /** * access_ok - Checks if a user space pointer is valid * @addr: User space pointer to start of block to check @@ -41,7 +66,7 @@ static inline bool pagefault_disabled(void); #define access_ok(addr, size) \ ({ \ WARN_ON_IN_IRQ(); \ - likely(__access_ok(addr, size)); \ + likely(__access_ok(untagged_addr(current->mm, addr), size)); \ }) =20 #include @@ -127,7 +152,13 @@ extern int __get_user_bad(void); * Return: zero on success, or -EFAULT on error. * On error, the variable @x is set to zero. */ -#define get_user(x,ptr) ({ might_fault(); do_get_user_call(get_user,x,ptr)= ; }) +#define get_user(x,ptr) \ +({ \ + __typeof__(*(ptr)) __user *__ptr_clean; \ + __ptr_clean =3D untagged_ptr(current->mm, ptr); \ + might_fault(); \ + do_get_user_call(get_user,x,__ptr_clean); \ +}) =20 /** * __get_user - Get a simple variable from user space, with less checking. @@ -227,7 +258,12 @@ extern void __put_user_nocheck_8(void); * * Return: zero on success, or -EFAULT on error. */ -#define put_user(x, ptr) ({ might_fault(); do_put_user_call(put_user,x,ptr= ); }) +#define put_user(x, ptr) ({ \ + __typeof__(*(ptr)) __user *__ptr_clean; \ + __ptr_clean =3D untagged_ptr(current->mm, ptr); \ + might_fault(); \ + do_put_user_call(put_user,x,__ptr_clean); \ +}) =20 /** * __put_user - Write a simple value into user space, with less checking. diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index c21b7347a26d..d1e83ba21130 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -47,6 +47,7 @@ #include #include #include +#include =20 #include "process.h" =20 @@ -367,6 +368,8 @@ void arch_setup_new_exec(void) task_clear_spec_ssb_noexec(current); speculation_ctrl_update(read_thread_flags()); } + + mm_reset_untag_mask(current->mm); } =20 #ifdef CONFIG_X86_IOPL_IOPERM --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 341E1C433FE for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="392382133" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="392382133" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861181" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861181" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 3000D104716; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" , Marc Zyngier Subject: [PATCHv10 06/15] KVM: Serialize tagged address check against tagging enabling Date: Tue, 18 Oct 2022 14:33:49 +0300 Message-Id: <20221018113358.7833-7-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" KVM forbids usage of tagged userspace addresses for memslots. It is done by checking if the address stays the same after untagging. It is works fine for ARM TBI, but it the check gets racy for LAM. TBI enabling happens per-thread, so nobody can enable tagging for the thread while the memslot gets added. LAM gets enabled per-process. If it gets enabled after the untagged_addr() check, but before access_ok() check the kernel can wrongly allow tagged userspace_addr. Use mmap lock to protect against parallel LAM enabling. Signed-off-by: Kirill A. Shutemov Reported-by: Rick Edgecombe Cc: Marc Zyngier --- virt/kvm/kvm_main.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c index 8c86b06b35da..833742c21c91 100644 --- a/virt/kvm/kvm_main.c +++ b/virt/kvm/kvm_main.c @@ -1943,12 +1943,22 @@ int __kvm_set_memory_region(struct kvm *kvm, return -EINVAL; if (mem->guest_phys_addr & (PAGE_SIZE - 1)) return -EINVAL; + + /* Serialize against tagging enabling */ + if (mmap_read_lock_killable(kvm->mm)) + return -EINTR; + /* We can read the guest memory with __xxx_user() later on. */ if ((mem->userspace_addr & (PAGE_SIZE - 1)) || (mem->userspace_addr !=3D untagged_addr(kvm->mm, mem->userspace_addr)= ) || !access_ok((void __user *)(unsigned long)mem->userspace_addr, - mem->memory_size)) + mem->memory_size)) { + mmap_read_unlock(kvm->mm); return -EINVAL; + } + + mmap_read_unlock(kvm->mm); + if (as_id >=3D KVM_ADDRESS_SPACE_NUM || id >=3D KVM_MEM_SLOTS_NUM) return -EINVAL; if (mem->guest_phys_addr + mem->memory_size < mem->guest_phys_addr) --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFB75C433FE for ; Tue, 18 Oct 2022 11:36:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230243AbiJRLgU (ORCPT ); Tue, 18 Oct 2022 07:36:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230132AbiJRLfs (ORCPT ); Tue, 18 Oct 2022 07:35:48 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2CB8BA91A for ; Tue, 18 Oct 2022 04:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666092920; x=1697628920; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1RmDlHjank+08AvRxU4Dq3nTeuAWGKaZTDb08aAe7to=; b=jK/dwJ7Ul61emAbaOoppOksFM66niauKjbrzzpE9hiKypmDU6nm5v1S5 YeszmEYg0/i4W64JdK7dGLLgtwTXqqPMldghpEqREiY6/mq7HR4t3UXY5 5mgLW9yEvhfrWd8eqGYZuxn6iN/UxhT11BiR8CiFeXRtYHGkaGFwNoA8E OoDGvpEIQNxdIvRvVxn1CwIyOi2/JdBy136+hPvjqQFoyTs5gQCkw8r2p wkFEWzxotFVHvg5mVOIcjRcduMv7tu7P1QjvdXXukkwotIIvSCYRjBD0d IByk7VteTm4nCVJ3cFXvMLWmC+r8+msrALVWsDkVM/v9AAfFpq8V3wcaX w==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="368105823" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368105823" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:17 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="691763175" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="691763175" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 3AAA610479E; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 07/15] x86/mm: Provide arch_prctl() interface for LAM Date: Tue, 18 Oct 2022 14:33:50 +0300 Message-Id: <20221018113358.7833-8-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a couple of arch_prctl() handles: - ARCH_ENABLE_TAGGED_ADDR enabled LAM. The argument is required number of tag bits. It is rounded up to the nearest LAM mode that can provide it. For now only LAM_U57 is supported, with 6 tag bits. - ARCH_GET_UNTAG_MASK returns untag mask. It can indicates where tag bits located in the address. - ARCH_GET_MAX_TAG_BITS returns the maximum tag bits user can request. Zero if LAM is not supported. Signed-off-by: Kirill A. Shutemov Tested-by: Alexander Potapenko Reviewed-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/uapi/asm/prctl.h | 4 ++ arch/x86/kernel/process_64.c | 65 ++++++++++++++++++++++++++++++- 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/uapi/asm/prctl.h b/arch/x86/include/uapi/asm/= prctl.h index 500b96e71f18..a31e27b95b19 100644 --- a/arch/x86/include/uapi/asm/prctl.h +++ b/arch/x86/include/uapi/asm/prctl.h @@ -20,4 +20,8 @@ #define ARCH_MAP_VDSO_32 0x2002 #define ARCH_MAP_VDSO_64 0x2003 =20 +#define ARCH_GET_UNTAG_MASK 0x4001 +#define ARCH_ENABLE_TAGGED_ADDR 0x4002 +#define ARCH_GET_MAX_TAG_BITS 0x4003 + #endif /* _ASM_X86_PRCTL_H */ diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 6b3418bff326..a98536101447 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -743,6 +743,60 @@ static long prctl_map_vdso(const struct vdso_image *im= age, unsigned long addr) } #endif =20 +static void enable_lam_func(void *mm) +{ + struct mm_struct *loaded_mm =3D this_cpu_read(cpu_tlbstate.loaded_mm); + unsigned long lam_mask; + unsigned long cr3; + + if (loaded_mm !=3D mm) + return; + + lam_mask =3D READ_ONCE(loaded_mm->context.lam_cr3_mask); + + /* Update CR3 to get LAM active on the CPU */ + cr3 =3D __read_cr3(); + cr3 &=3D ~(X86_CR3_LAM_U48 | X86_CR3_LAM_U57); + cr3 |=3D lam_mask; + write_cr3(cr3); + set_tlbstate_cr3_lam_mask(lam_mask); +} + +#define LAM_U57_BITS 6 + +static int prctl_enable_tagged_addr(struct mm_struct *mm, unsigned long nr= _bits) +{ + int ret =3D 0; + + if (!cpu_feature_enabled(X86_FEATURE_LAM)) + return -ENODEV; + + if (mmap_write_lock_killable(mm)) + return -EINTR; + + /* Already enabled? */ + if (mm->context.lam_cr3_mask) { + ret =3D -EBUSY; + goto out; + } + + if (!nr_bits) { + ret =3D -EINVAL; + goto out; + } else if (nr_bits <=3D LAM_U57_BITS) { + mm->context.lam_cr3_mask =3D X86_CR3_LAM_U57; + mm->context.untag_mask =3D ~GENMASK(62, 57); + } else { + ret =3D -EINVAL; + goto out; + } + + on_each_cpu_mask(mm_cpumask(mm), enable_lam_func, mm, true); +out: + mmap_write_unlock(mm); + return ret; +} + long do_arch_prctl_64(struct task_struct *task, int option, unsigned long = arg2) { int ret =3D 0; @@ -830,7 +884,16 @@ long do_arch_prctl_64(struct task_struct *task, int op= tion, unsigned long arg2) case ARCH_MAP_VDSO_64: return prctl_map_vdso(&vdso_image_64, arg2); #endif - + case ARCH_GET_UNTAG_MASK: + return put_user(task->mm->context.untag_mask, + (unsigned long __user *)arg2); + case ARCH_ENABLE_TAGGED_ADDR: + return prctl_enable_tagged_addr(task->mm, arg2); + case ARCH_GET_MAX_TAG_BITS: + if (!cpu_feature_enabled(X86_FEATURE_LAM)) + return put_user(0, (unsigned long __user *)arg2); + else + return put_user(LAM_U57_BITS, (unsigned long __user *)arg2); default: ret =3D -EINVAL; break; --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71ABCC433FE for ; Tue, 18 Oct 2022 11:36:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230250AbiJRLgW (ORCPT ); Tue, 18 Oct 2022 07:36:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50564 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230118AbiJRLfs (ORCPT ); Tue, 18 Oct 2022 07:35:48 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0F8CBA90E for ; Tue, 18 Oct 2022 04:35:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666092920; x=1697628920; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fhYTon+Hc+WcBW6ZSEbgkDupKrv70IXcyEjN02jeYOc=; b=mVyrR2LESIXtqC1t8pe/d9+9I9ucwmtgaSsZNke6LgLaqxkYtGYQcX/O b3NMAlydiMbfQ3nWHzSnWvjGwOxsnE0VkL7XjGuDhTUTwzPtIxdVUwNiN 9nAHB+ze1PSN5VvjrkKkVfkYgPbudLoe8Yf0B97xqBhOThUyUkQPPdHe4 APQ0amEulHzP1l+31VO1NyWh63xRsCLeC8+5hqhrWxCmDT8czCes8QkFh WuzlRgzuVqYeE0Q6xcl4Ei4DG8M+7GL+DZvgLmgWgEDbTGwmXGf4roCWJ G03Lqb54BQotV085NBF6IR3fnBDqG2xrxsWPwRr6kaqbcw53nM6zBymfX A==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="392382134" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="392382134" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861182" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861182" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 4530D104A70; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 08/15] x86/mm: Reduce untagged_addr() overhead until the first LAM user Date: Tue, 18 Oct 2022 14:33:51 +0300 Message-Id: <20221018113358.7833-9-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use static key to reduce untagged_addr() overhead. The key only gets enabled when the first process enables LAM. Signed-off-by: Kirill A. Shutemov --- arch/x86/include/asm/uaccess.h | 8 ++++++-- arch/x86/kernel/process_64.c | 4 ++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h index c6062c07ccd2..820234f1f750 100644 --- a/arch/x86/include/asm/uaccess.h +++ b/arch/x86/include/asm/uaccess.h @@ -23,6 +23,8 @@ static inline bool pagefault_disabled(void); #endif =20 #ifdef CONFIG_X86_64 +DECLARE_STATIC_KEY_FALSE(tagged_addr_key); + /* * Mask out tag bits from the address. * @@ -31,8 +33,10 @@ static inline bool pagefault_disabled(void); */ #define untagged_addr(mm, addr) ({ \ u64 __addr =3D (__force u64)(addr); \ - s64 sign =3D (s64)__addr >> 63; \ - __addr &=3D (mm)->context.untag_mask | sign; \ + if (static_branch_likely(&tagged_addr_key)) { \ + s64 sign =3D (s64)__addr >> 63; \ + __addr &=3D (mm)->context.untag_mask | sign; \ + } \ (__force __typeof__(addr))__addr; \ }) =20 diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index a98536101447..9952e9f517ec 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -743,6 +743,9 @@ static long prctl_map_vdso(const struct vdso_image *ima= ge, unsigned long addr) } #endif =20 +DEFINE_STATIC_KEY_FALSE(tagged_addr_key); +EXPORT_SYMBOL_GPL(tagged_addr_key); + static void enable_lam_func(void *mm) { struct mm_struct *loaded_mm =3D this_cpu_read(cpu_tlbstate.loaded_mm); @@ -792,6 +795,7 @@ static int prctl_enable_tagged_addr(struct mm_struct *m= m, unsigned long nr_bits) } =20 on_each_cpu_mask(mm_cpumask(mm), enable_lam_func, mm, true); + static_branch_enable(&tagged_addr_key); out: mmap_write_unlock(mm); return ret; --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8182BC4332F for ; Tue, 18 Oct 2022 11:36:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230287AbiJRLgz (ORCPT ); Tue, 18 Oct 2022 07:36:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229894AbiJRLgQ (ORCPT ); Tue, 18 Oct 2022 07:36:16 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1460A28E3F for ; Tue, 18 Oct 2022 04:35:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666092945; x=1697628945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NHTbKElyyJKm9Q90dm05YZun/yPzZoA5KBxzSmXyv5U=; b=V4CP86l0NszdyOPsM1p99Nmee85VDR+h1el9Jb8J6fEdBSl4WiKjUL3g 7BM3TAiCz/SxzT4eTASASxcNi3+L3UI1b6UCmNlHVpEaIHM23Ahc4Daqe YrUYXs4Z/SQi9xh+6scTsr2qOOGEMNrhpTyxvpKrFZ2gF7+9gf/Xx2KvA taDKUcU+8wMbaQ3kFiSet6jCyQjLSE5UpjlaGSuYSqhR1JahfwOltQlaT 6FWYdvDSV41HwheLl1LtBAfPa6rBTDYUXiUAGm31u7bmF47/X6zYyNAHg bpVeg2863MBBuJukLa0XUR5wYvJTzmCjke0Y/AJ5aoVJdJk14b1jKf7SO w==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="368105825" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368105825" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:17 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="691763177" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="691763177" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 503F0104BA7; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 09/15] x86: Expose untagging mask in /proc/$PID/arch_status Date: Tue, 18 Oct 2022 14:33:52 +0300 Message-Id: <20221018113358.7833-10-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a line in /proc/$PID/arch_status to report untag_mask. It can be used to find out LAM status of the process from the outside. It is useful for debuggers. Signed-off-by: Kirill A. Shutemov Tested-by: Alexander Potapenko Acked-by: Peter Zijlstra (Intel) --- arch/x86/include/asm/mmu_context.h | 10 +++++ arch/x86/kernel/Makefile | 2 + arch/x86/kernel/fpu/xstate.c | 47 ----------------------- arch/x86/kernel/proc.c | 60 ++++++++++++++++++++++++++++++ 4 files changed, 72 insertions(+), 47 deletions(-) create mode 100644 arch/x86/kernel/proc.c diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index 5bd3d46685dc..b0e9ea23758b 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -103,6 +103,11 @@ static inline void dup_lam(struct mm_struct *oldmm, st= ruct mm_struct *mm) mm->context.untag_mask =3D oldmm->context.untag_mask; } =20 +static inline unsigned long mm_untag_mask(struct mm_struct *mm) +{ + return mm->context.untag_mask; +} + static inline void mm_reset_untag_mask(struct mm_struct *mm) { mm->context.untag_mask =3D -1UL; @@ -119,6 +124,11 @@ static inline void dup_lam(struct mm_struct *oldmm, st= ruct mm_struct *mm) { } =20 +static inline unsigned long mm_untag_mask(struct mm_struct *mm) +{ + return -1UL; +} + static inline void mm_reset_untag_mask(struct mm_struct *mm) { } diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index f901658d9f7c..d99fd065aba8 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -143,6 +143,8 @@ obj-$(CONFIG_AMD_MEM_ENCRYPT) +=3D sev.o =20 obj-$(CONFIG_CFI_CLANG) +=3D cfi.o =20 +obj-$(CONFIG_PROC_FS) +=3D proc.o + ### # 64 bit specific files ifeq ($(CONFIG_X86_64),y) diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c index c8340156bfd2..838a6f0627fd 100644 --- a/arch/x86/kernel/fpu/xstate.c +++ b/arch/x86/kernel/fpu/xstate.c @@ -10,8 +10,6 @@ #include #include #include -#include -#include #include =20 #include @@ -1745,48 +1743,3 @@ long fpu_xstate_prctl(int option, unsigned long arg2) return -EINVAL; } } - -#ifdef CONFIG_PROC_PID_ARCH_STATUS -/* - * Report the amount of time elapsed in millisecond since last AVX512 - * use in the task. - */ -static void avx512_status(struct seq_file *m, struct task_struct *task) -{ - unsigned long timestamp =3D READ_ONCE(task->thread.fpu.avx512_timestamp); - long delta; - - if (!timestamp) { - /* - * Report -1 if no AVX512 usage - */ - delta =3D -1; - } else { - delta =3D (long)(jiffies - timestamp); - /* - * Cap to LONG_MAX if time difference > LONG_MAX - */ - if (delta < 0) - delta =3D LONG_MAX; - delta =3D jiffies_to_msecs(delta); - } - - seq_put_decimal_ll(m, "AVX512_elapsed_ms:\t", delta); - seq_putc(m, '\n'); -} - -/* - * Report architecture specific information - */ -int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns, - struct pid *pid, struct task_struct *task) -{ - /* - * Report AVX512 state if the processor and build option supported. - */ - if (cpu_feature_enabled(X86_FEATURE_AVX512F)) - avx512_status(m, task); - - return 0; -} -#endif /* CONFIG_PROC_PID_ARCH_STATUS */ diff --git a/arch/x86/kernel/proc.c b/arch/x86/kernel/proc.c new file mode 100644 index 000000000000..9765b4d05ce4 --- /dev/null +++ b/arch/x86/kernel/proc.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include + +/* + * Report the amount of time elapsed in millisecond since last AVX512 + * use in the task. + */ +static void avx512_status(struct seq_file *m, struct task_struct *task) +{ + unsigned long timestamp =3D READ_ONCE(task->thread.fpu.avx512_timestamp); + long delta; + + if (!timestamp) { + /* + * Report -1 if no AVX512 usage + */ + delta =3D -1; + } else { + delta =3D (long)(jiffies - timestamp); + /* + * Cap to LONG_MAX if time difference > LONG_MAX + */ + if (delta < 0) + delta =3D LONG_MAX; + delta =3D jiffies_to_msecs(delta); + } + + seq_put_decimal_ll(m, "AVX512_elapsed_ms:\t", delta); + seq_putc(m, '\n'); +} + +/* + * Report architecture specific information + */ +int proc_pid_arch_status(struct seq_file *m, struct pid_namespace *ns, + struct pid *pid, struct task_struct *task) +{ + struct mm_struct *mm; + unsigned long untag_mask =3D -1UL; + + /* + * Report AVX512 state if the processor and build option supported. + */ + if (cpu_feature_enabled(X86_FEATURE_AVX512F)) + avx512_status(m, task); + + mm =3D get_task_mm(task); + if (mm) { + untag_mask =3D mm_untag_mask(task->mm); + mmput(mm); + } + + seq_printf(m, "untag_mask:\t%#lx\n", untag_mask); + + return 0; +} --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B42FC4332F for ; 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X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="392382135" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="392382135" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861186" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861186" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 5A2A5104BA8; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, "Kirill A. Shutemov" Subject: [PATCHv10 10/15] x86/mm, iommu/sva: Make LAM and SVM mutually exclusive Date: Tue, 18 Oct 2022 14:33:53 +0300 Message-Id: <20221018113358.7833-11-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" IOMMU and SVM-capable devices know nothing about LAM and only expect canonical addresses. Attempt to pass down tagged pointer will lead to address translation failure. By default do not allow to enable both LAM and use SVM in the same process. The new ARCH_FORCE_TAGGED_SVM arch_prctl() overrides the limitation. By using the arch_prctl() userspace takes responsibility to never pass tagged address to the device. Signed-off-by: Kirill A. Shutemov Reviewed-by: Ashok Raj --- arch/x86/include/asm/mmu.h | 6 ++++-- arch/x86/include/asm/mmu_context.h | 2 ++ arch/x86/include/uapi/asm/prctl.h | 1 + arch/x86/kernel/process_64.c | 13 +++++++++++++ drivers/iommu/iommu-sva-lib.c | 12 ++++++++++++ include/linux/mmu_context.h | 4 ++++ 6 files changed, 36 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h index 2fdb390040b5..cce9b32b0d6d 100644 --- a/arch/x86/include/asm/mmu.h +++ b/arch/x86/include/asm/mmu.h @@ -9,9 +9,11 @@ #include =20 /* Uprobes on this MM assume 32-bit code */ -#define MM_CONTEXT_UPROBE_IA32 BIT(0) +#define MM_CONTEXT_UPROBE_IA32 BIT(0) /* vsyscall page is accessible on this MM */ -#define MM_CONTEXT_HAS_VSYSCALL BIT(1) +#define MM_CONTEXT_HAS_VSYSCALL BIT(1) +/* Allow LAM and SVM coexisting */ +#define MM_CONTEXT_FORCE_TAGGED_SVM BIT(2) =20 /* * x86 has arch-specific MMU state beyond what lives in mm_struct. diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index b0e9ea23758b..6b9ac2c60cec 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -113,6 +113,8 @@ static inline void mm_reset_untag_mask(struct mm_struct= *mm) mm->context.untag_mask =3D -1UL; } =20 +#define arch_pgtable_dma_compat(mm) \ + (!mm_lam_cr3_mask(mm) || (mm->context.flags & MM_CONTEXT_FORCE_TAGGED_SVM= )) #else =20 static inline unsigned long mm_lam_cr3_mask(struct mm_struct *mm) diff --git a/arch/x86/include/uapi/asm/prctl.h b/arch/x86/include/uapi/asm/= prctl.h index a31e27b95b19..7bd22defb558 100644 --- a/arch/x86/include/uapi/asm/prctl.h +++ b/arch/x86/include/uapi/asm/prctl.h @@ -23,5 +23,6 @@ #define ARCH_GET_UNTAG_MASK 0x4001 #define ARCH_ENABLE_TAGGED_ADDR 0x4002 #define ARCH_GET_MAX_TAG_BITS 0x4003 +#define ARCH_FORCE_TAGGED_SVM 0x4004 =20 #endif /* _ASM_X86_PRCTL_H */ diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c index 9952e9f517ec..8faa8774bb93 100644 --- a/arch/x86/kernel/process_64.c +++ b/arch/x86/kernel/process_64.c @@ -783,6 +783,13 @@ static int prctl_enable_tagged_addr(struct mm_struct *= mm, unsigned long nr_bits) goto out; } =20 +#ifdef CONFIG_IOMMU_SVA + if (pasid_valid(mm->pasid) && + !(mm->context.flags & MM_CONTEXT_FORCE_TAGGED_SVM)) { + ret =3D -EBUSY; + goto out; + } +#endif if (!nr_bits) { ret =3D -EINVAL; goto out; @@ -893,6 +900,12 @@ long do_arch_prctl_64(struct task_struct *task, int op= tion, unsigned long arg2) (unsigned long __user *)arg2); case ARCH_ENABLE_TAGGED_ADDR: return prctl_enable_tagged_addr(task->mm, arg2); + case ARCH_FORCE_TAGGED_SVM: + if (mmap_write_lock_killable(task->mm)) + return -EINTR; + task->mm->context.flags |=3D MM_CONTEXT_FORCE_TAGGED_SVM; + mmap_write_unlock(task->mm); + return 0; case ARCH_GET_MAX_TAG_BITS: if (!cpu_feature_enabled(X86_FEATURE_LAM)) return put_user(0, (unsigned long __user *)arg2); diff --git a/drivers/iommu/iommu-sva-lib.c b/drivers/iommu/iommu-sva-lib.c index 106506143896..593ae2472e2c 100644 --- a/drivers/iommu/iommu-sva-lib.c +++ b/drivers/iommu/iommu-sva-lib.c @@ -2,6 +2,8 @@ /* * Helpers for IOMMU drivers implementing SVA */ +#include +#include #include #include =20 @@ -31,6 +33,15 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t= min, ioasid_t max) min =3D=3D 0 || max < min) return -EINVAL; =20 + /* Serialize against address tagging enabling */ + if (mmap_write_lock_killable(mm)) + return -EINTR; + + if (!arch_pgtable_dma_compat(mm)) { + mmap_write_unlock(mm); + return -EBUSY; + } + mutex_lock(&iommu_sva_lock); /* Is a PASID already associated with this mm? */ if (pasid_valid(mm->pasid)) { @@ -46,6 +57,7 @@ int iommu_sva_alloc_pasid(struct mm_struct *mm, ioasid_t = min, ioasid_t max) mm_pasid_set(mm, pasid); out: mutex_unlock(&iommu_sva_lock); + mmap_write_unlock(mm); return ret; } EXPORT_SYMBOL_GPL(iommu_sva_alloc_pasid); diff --git a/include/linux/mmu_context.h b/include/linux/mmu_context.h index b9b970f7ab45..115e2b518079 100644 --- a/include/linux/mmu_context.h +++ b/include/linux/mmu_context.h @@ -28,4 +28,8 @@ static inline void leave_mm(int cpu) { } # define task_cpu_possible(cpu, p) cpumask_test_cpu((cpu), task_cpu_possib= le_mask(p)) #endif =20 +#ifndef arch_pgtable_dma_compat +#define arch_pgtable_dma_compat(mm) true +#endif + #endif --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7AC5C4332F for ; Tue, 18 Oct 2022 11:37:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230297AbiJRLg7 (ORCPT ); Tue, 18 Oct 2022 07:36:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32878 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230281AbiJRLgs (ORCPT ); Tue, 18 Oct 2022 07:36:48 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C868DB9784 for ; Tue, 18 Oct 2022 04:35:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666092948; x=1697628948; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=A07f05+t0KWtt4ghU/0U2MmLVS25K/SAxXIfuDOarp4=; b=mU454881bQqQrDRujxjdiuwOyaTmqIiCp82Bwbfv0To+clvjbUgVoTuv sYVYQhtl9FL1MkKzByDJ++og7EwT7SXvcJJBFXmT652GgtE75RyjKukSn qFSkiY/hqCL7dnC6evyp/QdJoIaEcxwjYnEwP/tQIBhu45Hs6qoPx2RWe MK3O5GpGXPP0kZTiVZalAaksS9U+2Uo1oU5z6qy3KjF++h59r4ad7FCac HpmyWKBV/SOY8ONLsZvHrdozkcpslSEO25W07d4QJtOu4/066Uu3rwdoL uPvzf6SlrSOSANXDczs9F6L5mo2HDW1aig6GyxX5H2i07g3zfsjfdv/3P A==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="368105827" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368105827" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:17 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="691763180" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="691763180" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 654E3104BA9; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Weihong Zhang , "Kirill A . Shutemov" Subject: [PATCHv10 11/15] selftests/x86/lam: Add malloc and tag-bits test cases for linear-address masking Date: Tue, 18 Oct 2022 14:33:54 +0300 Message-Id: <20221018113358.7833-12-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Weihong Zhang LAM is supported only in 64-bit mode and applies only addresses used for da= ta accesses. In 64-bit mode, linear address have 64 bits. LAM is applied to 64= -bit linear address and allow software to use high bits for metadata. LAM supports configurations that differ regarding which pointer bits are ma= sked and can be used for metadata. LAM includes following mode: - LAM_U57, pointer bits in positions 62:57 are masked (LAM width 6), allows bits 62:57 of a user pointer to be used as metadata. There are some arch_prctls: ARCH_ENABLE_TAGGED_ADDR: enable LAM mode, mask high bits of a user pointer. ARCH_GET_UNTAG_MASK: get current untagged mask. ARCH_GET_MAX_TAG_BITS: the maximum tag bits user can request. zero if LAM is not supported. The LAM mode is for pre-process, a process has only one chance to set LAM m= ode. But there is no API to disable LAM mode. So all of test cases are run under child process. Functions of this test: MALLOC - LAM_U57 masks bits 57:62 of a user pointer. Process on user space can dereference such pointers. - Disable LAM, dereference a pointer with metadata above 48 bit or 57 bit lead to trigger SIGSEGV. TAG_BITS - Max tag bits of LAM_U57 is 6. Signed-off-by: Weihong Zhang Signed-off-by: Kirill A. Shutemov --- tools/testing/selftests/x86/Makefile | 2 +- tools/testing/selftests/x86/lam.c | 326 +++++++++++++++++++++++++++ 2 files changed, 327 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/x86/lam.c diff --git a/tools/testing/selftests/x86/Makefile b/tools/testing/selftests= /x86/Makefile index 0388c4d60af0..c1a16a9d4f2f 100644 --- a/tools/testing/selftests/x86/Makefile +++ b/tools/testing/selftests/x86/Makefile @@ -18,7 +18,7 @@ TARGETS_C_32BIT_ONLY :=3D entry_from_vm86 test_syscall_vd= so unwind_vdso \ test_FCMOV test_FCOMI test_FISTTP \ vdso_restorer TARGETS_C_64BIT_ONLY :=3D fsgsbase sysret_rip syscall_numbering \ - corrupt_xstate_header amx + corrupt_xstate_header amx lam # Some selftests require 32bit support enabled also on 64bit systems TARGETS_C_32BIT_NEEDED :=3D ldt_gdt ptrace_syscall =20 diff --git a/tools/testing/selftests/x86/lam.c b/tools/testing/selftests/x8= 6/lam.c new file mode 100644 index 000000000000..900a3a0fb709 --- /dev/null +++ b/tools/testing/selftests/x86/lam.c @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../kselftest.h" + +#ifndef __x86_64__ +# error This test is 64-bit only +#endif + +/* LAM modes, these definitions were copied from kernel code */ +#define LAM_NONE 0 +#define LAM_U57_BITS 6 + +#define LAM_U57_MASK (0x3fULL << 57) +/* arch prctl for LAM */ +#define ARCH_GET_UNTAG_MASK 0x4001 +#define ARCH_ENABLE_TAGGED_ADDR 0x4002 +#define ARCH_GET_MAX_TAG_BITS 0x4003 + +/* Specified test function bits */ +#define FUNC_MALLOC 0x1 +#define FUNC_BITS 0x2 + +#define TEST_MASK 0x3 + +#define MALLOC_LEN 32 + +struct testcases { + unsigned int later; + int expected; /* 2: SIGSEGV Error; 1: other errors */ + unsigned long lam; + uint64_t addr; + int (*test_func)(struct testcases *test); + const char *msg; +}; + +int tests_cnt; +jmp_buf segv_env; + +static void segv_handler(int sig) +{ + ksft_print_msg("Get segmentation fault(%d).", sig); + siglongjmp(segv_env, 1); +} + +static inline int cpu_has_lam(void) +{ + unsigned int cpuinfo[4]; + + __cpuid_count(0x7, 1, cpuinfo[0], cpuinfo[1], cpuinfo[2], cpuinfo[3]); + + return (cpuinfo[0] & (1 << 26)); +} + +/* + * Set tagged address and read back untag mask. + * check if the untagged mask is expected. + * + * @return: + * 0: Set LAM mode successfully + * others: failed to set LAM + */ +static int set_lam(unsigned long lam) +{ + int ret =3D 0; + uint64_t ptr =3D 0; + + if (lam !=3D LAM_U57_BITS && lam !=3D LAM_NONE) + return -1; + + /* Skip check return */ + syscall(SYS_arch_prctl, ARCH_ENABLE_TAGGED_ADDR, lam); + + /* Get untagged mask */ + syscall(SYS_arch_prctl, ARCH_GET_UNTAG_MASK, &ptr); + + /* Check mask returned is expected */ + if (lam =3D=3D LAM_U57_BITS) + ret =3D (ptr !=3D ~(LAM_U57_MASK)); + else if (lam =3D=3D LAM_NONE) + ret =3D (ptr !=3D -1ULL); + + return ret; +} + +static unsigned long get_default_tag_bits(void) +{ + pid_t pid; + int lam =3D LAM_NONE; + int ret =3D 0; + + pid =3D fork(); + if (pid < 0) { + perror("Fork failed."); + } else if (pid =3D=3D 0) { + /* Set LAM mode in child process */ + if (set_lam(LAM_U57_BITS) =3D=3D 0) + lam =3D LAM_U57_BITS; + else + lam =3D LAM_NONE; + exit(lam); + } else { + wait(&ret); + lam =3D WEXITSTATUS(ret); + } + + return lam; +} + +/* According to LAM mode, set metadata in high bits */ +static uint64_t set_metadata(uint64_t src, unsigned long lam) +{ + uint64_t metadata; + + srand(time(NULL)); + /* Get a random value as metadata */ + metadata =3D rand(); + + switch (lam) { + case LAM_U57_BITS: /* Set metadata in bits 62:57 */ + metadata =3D (src & ~(LAM_U57_MASK)) | ((metadata & 0x3f) << 57); + break; + default: + metadata =3D src; + break; + } + + return metadata; +} + +/* + * Set metadata in user pointer, compare new pointer with original pointer. + * both pointers should point to the same address. + * + * @return: + * 0: value on the pointer with metadate and value on original are same + * 1: not same. + */ +static int handle_lam_test(void *src, unsigned int lam) +{ + char *ptr; + + strcpy((char *)src, "USER POINTER"); + + ptr =3D (char *)set_metadata((uint64_t)src, lam); + if (src =3D=3D ptr) + return 0; + + /* Copy a string into the pointer with metadata */ + strcpy((char *)ptr, "METADATA POINTER"); + + return (!!strcmp((char *)src, (char *)ptr)); +} + + +int handle_max_bits(struct testcases *test) +{ + unsigned long exp_bits =3D get_default_tag_bits(); + unsigned long bits =3D 0; + + if (exp_bits !=3D LAM_NONE) + exp_bits =3D LAM_U57_BITS; + + /* Get LAM max tag bits */ + if (syscall(SYS_arch_prctl, ARCH_GET_MAX_TAG_BITS, &bits) =3D=3D -1) + return 1; + + return (exp_bits !=3D bits); +} + +/* + * Test lam feature through dereference pointer get from malloc. + * @return 0: Pass test. 1: Get failure during test 2: Get SIGSEGV + */ +static int handle_malloc(struct testcases *test) +{ + char *ptr =3D NULL; + int ret =3D 0; + + if (test->later =3D=3D 0 && test->lam !=3D 0) + if (set_lam(test->lam) =3D=3D -1) + return 1; + + ptr =3D (char *)malloc(MALLOC_LEN); + if (ptr =3D=3D NULL) { + perror("malloc() failure\n"); + return 1; + } + + /* Set signal handler */ + if (sigsetjmp(segv_env, 1) =3D=3D 0) { + signal(SIGSEGV, segv_handler); + ret =3D handle_lam_test(ptr, test->lam); + } else { + ret =3D 2; + } + + if (test->later !=3D 0 && test->lam !=3D 0) + if (set_lam(test->lam) =3D=3D -1 && ret =3D=3D 0) + ret =3D 1; + + free(ptr); + + return ret; +} + +static int fork_test(struct testcases *test) +{ + int ret, child_ret; + pid_t pid; + + pid =3D fork(); + if (pid < 0) { + perror("Fork failed."); + ret =3D 1; + } else if (pid =3D=3D 0) { + ret =3D test->test_func(test); + exit(ret); + } else { + wait(&child_ret); + ret =3D WEXITSTATUS(child_ret); + } + + return ret; +} + +static void run_test(struct testcases *test, int count) +{ + int i, ret =3D 0; + + for (i =3D 0; i < count; i++) { + struct testcases *t =3D test + i; + + /* fork a process to run test case */ + ret =3D fork_test(t); + if (ret !=3D 0) + ret =3D (t->expected =3D=3D ret); + else + ret =3D !(t->expected); + + tests_cnt++; + ksft_test_result(ret, t->msg); + } +} + +static struct testcases malloc_cases[] =3D { + { + .later =3D 0, + .lam =3D LAM_U57_BITS, + .test_func =3D handle_malloc, + .msg =3D "MALLOC: LAM_U57. Dereferencing pointer with metadata\n", + }, + { + .later =3D 1, + .expected =3D 2, + .lam =3D LAM_U57_BITS, + .test_func =3D handle_malloc, + .msg =3D "MALLOC:[Negative] Disable LAM. Dereferencing pointer with meta= data.\n", + }, +}; + + +static struct testcases bits_cases[] =3D { + { + .test_func =3D handle_max_bits, + .msg =3D "BITS: Check default tag bits\n", + }, +}; + +static void cmd_help(void) +{ + printf("usage: lam [-h] [-t test list]\n"); + printf("\t-t test list: run tests specified in the test list, default:0x%= x\n", TEST_MASK); + printf("\t\t0x1:malloc; 0x2:max_bits;\n"); + printf("\t-h: help\n"); +} + +int main(int argc, char **argv) +{ + int c =3D 0; + unsigned int tests =3D TEST_MASK; + + tests_cnt =3D 0; + + if (!cpu_has_lam()) { + ksft_print_msg("Unsupported LAM feature!\n"); + return -1; + } + + while ((c =3D getopt(argc, argv, "ht:")) !=3D -1) { + switch (c) { + case 't': + tests =3D strtoul(optarg, NULL, 16); + if (!(tests & TEST_MASK)) { + ksft_print_msg("Invalid argument!\n"); + return -1; + } + break; + case 'h': + cmd_help(); + return 0; + default: + ksft_print_msg("Invalid argument\n"); + return -1; + } + } + + if (tests & FUNC_MALLOC) + run_test(malloc_cases, ARRAY_SIZE(malloc_cases)); + + if (tests & FUNC_BITS) + run_test(bits_cases, ARRAY_SIZE(bits_cases)); + + ksft_set_plan(tests_cnt); + + return ksft_exit_pass(); +} --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED805C4332F for ; Tue, 18 Oct 2022 11:37:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230334AbiJRLhL (ORCPT ); Tue, 18 Oct 2022 07:37:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230302AbiJRLgu (ORCPT ); Tue, 18 Oct 2022 07:36:50 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EA6CBA917 for ; Tue, 18 Oct 2022 04:36:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666092976; x=1697628976; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TuBz7tekTf1BWBxAT1QoET0tgEOR4TTS5pMFs+n0/Gc=; b=TGKFz7eRMZcZuJZalzLqmOKHo+U2/SN/Q1uW+JSlXWNy4Zk2qPPuA3td Pt6y6ReNG5c5ElxwRTDu01B2LTO/SKyI9M3dOgQo8uTJqE08yOBcMLtzk 9dro/henHXaR4n7+qkdy0XdWBrj/6VeVwciGVoYYZd63iuoNPYMkqbEFd op9alSU3eOCEReEB6SdMhdE9j7bMiAID0JkAUSpfvrLamDxd/QDXgDK6G huwFOaMh2oELt2XYXNVz0/xTBSf/H/IXD+0yXY0htd8AyMaQr+zBTsxv2 FGMa2wNu0rMfSrTJbl2/4Rr7dKL4qUUGxlk6lp6t5xBcuEgoRkVP38fJj g==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="368105828" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="368105828" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="691763182" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="691763182" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 70434104BAA; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Weihong Zhang , "Kirill A . Shutemov" Subject: [PATCHv10 12/15] selftests/x86/lam: Add mmap and SYSCALL test cases for linear-address masking Date: Tue, 18 Oct 2022 14:33:55 +0300 Message-Id: <20221018113358.7833-13-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Weihong Zhang Add mmap and SYSCALL test cases. SYSCALL test cases: - LAM supports set metadata in high bits 62:57 (LAM_U57) of a user pointer= , pass the pointer to SYSCALL, SYSCALL can dereference the pointer and return c= orrect result. - Disable LAM, pass a pointer with metadata in high bits to SYSCALL, SYSCALL returns -1 (EFAULT). MMAP test cases: - Enable LAM_U57, MMAP with low address (below bits 47), set metadata in high bits of the address, dereference the address should be allowed. - Enable LAM_U57, MMAP with high address (above bits 47), set metadata in high bits of the address, dereference the address should be allowed. Signed-off-by: Weihong Zhang Signed-off-by: Kirill A. Shutemov --- tools/testing/selftests/x86/lam.c | 144 +++++++++++++++++++++++++++++- 1 file changed, 140 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/x86/lam.c b/tools/testing/selftests/x8= 6/lam.c index 900a3a0fb709..cdc6e40e00e0 100644 --- a/tools/testing/selftests/x86/lam.c +++ b/tools/testing/selftests/x86/lam.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include =20 @@ -29,11 +30,18 @@ /* Specified test function bits */ #define FUNC_MALLOC 0x1 #define FUNC_BITS 0x2 +#define FUNC_MMAP 0x4 +#define FUNC_SYSCALL 0x8 =20 -#define TEST_MASK 0x3 +#define TEST_MASK 0xf + +#define LOW_ADDR (0x1UL << 30) +#define HIGH_ADDR (0x3UL << 48) =20 #define MALLOC_LEN 32 =20 +#define PAGE_SIZE (4 << 10) + struct testcases { unsigned int later; int expected; /* 2: SIGSEGV Error; 1: other errors */ @@ -49,6 +57,7 @@ jmp_buf segv_env; static void segv_handler(int sig) { ksft_print_msg("Get segmentation fault(%d).", sig); + siglongjmp(segv_env, 1); } =20 @@ -61,6 +70,16 @@ static inline int cpu_has_lam(void) return (cpuinfo[0] & (1 << 26)); } =20 +/* Check 5-level page table feature in CPUID.(EAX=3D07H, ECX=3D00H):ECX.[b= it 16] */ +static inline int cpu_has_la57(void) +{ + unsigned int cpuinfo[4]; + + __cpuid_count(0x7, 0, cpuinfo[0], cpuinfo[1], cpuinfo[2], cpuinfo[3]); + + return (cpuinfo[2] & (1 << 16)); +} + /* * Set tagged address and read back untag mask. * check if the untagged mask is expected. @@ -213,6 +232,68 @@ static int handle_malloc(struct testcases *test) return ret; } =20 +static int handle_mmap(struct testcases *test) +{ + void *ptr; + unsigned int flags =3D MAP_PRIVATE | MAP_ANONYMOUS | MAP_FIXED; + int ret =3D 0; + + if (test->later =3D=3D 0 && test->lam !=3D 0) + if (set_lam(test->lam) !=3D 0) + return 1; + + ptr =3D mmap((void *)test->addr, PAGE_SIZE, PROT_READ | PROT_WRITE, + flags, -1, 0); + if (ptr =3D=3D MAP_FAILED) { + if (test->addr =3D=3D HIGH_ADDR) + if (!cpu_has_la57()) + return 3; /* unsupport LA57 */ + return 1; + } + + if (test->later !=3D 0 && test->lam !=3D 0) + if (set_lam(test->lam) !=3D 0) + ret =3D 1; + + if (ret =3D=3D 0) { + if (sigsetjmp(segv_env, 1) =3D=3D 0) { + signal(SIGSEGV, segv_handler); + ret =3D handle_lam_test(ptr, test->lam); + } else { + ret =3D 2; + } + } + + munmap(ptr, PAGE_SIZE); + return ret; +} + +static int handle_syscall(struct testcases *test) +{ + struct utsname unme, *pu; + int ret =3D 0; + + if (test->later =3D=3D 0 && test->lam !=3D 0) + if (set_lam(test->lam) !=3D 0) + return 1; + + if (sigsetjmp(segv_env, 1) =3D=3D 0) { + signal(SIGSEGV, segv_handler); + pu =3D (struct utsname *)set_metadata((uint64_t)&unme, test->lam); + ret =3D uname(pu); + if (ret < 0) + ret =3D 1; + } else { + ret =3D 2; + } + + if (test->later !=3D 0 && test->lam !=3D 0) + if (set_lam(test->lam) !=3D -1 && ret =3D=3D 0) + ret =3D 1; + + return ret; +} + static int fork_test(struct testcases *test) { int ret, child_ret; @@ -241,13 +322,20 @@ static void run_test(struct testcases *test, int coun= t) struct testcases *t =3D test + i; =20 /* fork a process to run test case */ + tests_cnt++; ret =3D fork_test(t); + + /* return 3 is not support LA57, the case should be skipped */ + if (ret =3D=3D 3) { + ksft_test_result_skip(t->msg); + continue; + } + if (ret !=3D 0) ret =3D (t->expected =3D=3D ret); else ret =3D !(t->expected); =20 - tests_cnt++; ksft_test_result(ret, t->msg); } } @@ -268,7 +356,6 @@ static struct testcases malloc_cases[] =3D { }, }; =20 - static struct testcases bits_cases[] =3D { { .test_func =3D handle_max_bits, @@ -276,11 +363,54 @@ static struct testcases bits_cases[] =3D { }, }; =20 +static struct testcases syscall_cases[] =3D { + { + .later =3D 0, + .lam =3D LAM_U57_BITS, + .test_func =3D handle_syscall, + .msg =3D "SYSCALL: LAM_U57. syscall with metadata\n", + }, + { + .later =3D 1, + .expected =3D 1, + .lam =3D LAM_U57_BITS, + .test_func =3D handle_syscall, + .msg =3D "SYSCALL:[Negative] Disable LAM. Dereferencing pointer with met= adata.\n", + }, +}; + +static struct testcases mmap_cases[] =3D { + { + .later =3D 1, + .expected =3D 0, + .lam =3D LAM_U57_BITS, + .addr =3D HIGH_ADDR, + .test_func =3D handle_mmap, + .msg =3D "MMAP: First mmap high address, then set LAM_U57.\n", + }, + { + .later =3D 0, + .expected =3D 0, + .lam =3D LAM_U57_BITS, + .addr =3D HIGH_ADDR, + .test_func =3D handle_mmap, + .msg =3D "MMAP: First LAM_U57, then High address.\n", + }, + { + .later =3D 0, + .expected =3D 0, + .lam =3D LAM_U57_BITS, + .addr =3D LOW_ADDR, + .test_func =3D handle_mmap, + .msg =3D "MMAP: First LAM_U57, then Low address.\n", + }, +}; + static void cmd_help(void) { printf("usage: lam [-h] [-t test list]\n"); printf("\t-t test list: run tests specified in the test list, default:0x%= x\n", TEST_MASK); - printf("\t\t0x1:malloc; 0x2:max_bits;\n"); + printf("\t\t0x1:malloc; 0x2:max_bits; 0x4:mmap; 0x8:syscall.\n"); printf("\t-h: help\n"); } =20 @@ -320,6 +450,12 @@ int main(int argc, char **argv) if (tests & FUNC_BITS) run_test(bits_cases, ARRAY_SIZE(bits_cases)); =20 + if (tests & FUNC_MMAP) + run_test(mmap_cases, ARRAY_SIZE(mmap_cases)); + + if (tests & FUNC_SYSCALL) + run_test(syscall_cases, ARRAY_SIZE(syscall_cases)); + ksft_set_plan(tests_cnt); =20 return ksft_exit_pass(); --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8487C433FE for ; Tue, 18 Oct 2022 11:36:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230266AbiJRLgv (ORCPT ); Tue, 18 Oct 2022 07:36:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230201AbiJRLgG (ORCPT ); Tue, 18 Oct 2022 07:36:06 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D9FBDF1D for ; Tue, 18 Oct 2022 04:35:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666092930; x=1697628930; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=br6Om71qzm65KaCJtdGB8t7hbJwdX+JrsLtwnbZitNE=; b=FoST7pHjv1AFgm8LDcEnCkftgOa3DKu95m7XpbxHmBbUlOApNeQA6kLz h4ObLWPhlxPOhF666MPVyaXjC8KF7NNtwIovM59g7cCXUhf7D1E5dWKFd 90jAbMl/0DF4kUNwZPuTVO/qKngjZJUWsNEVoTgA3+yU/tNzjqskeibV9 X/sXCng/DRs9h08Pxs1TdUI/8Fp0efUaKrSMsjWXGZ6qsrtqiHSlPqkCi GHNMVmbkiiDCjrAFwJyta2ACHwvQuDGuPhnK7r28Y0d8KzgzQJNGO1fuV oaiWdBeKX10Dk72TUyGlym2BH+SH9kaJM/rfs8erstqr1p6nNgpIBqxu5 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="392382137" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="392382137" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:18 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861189" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861189" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 7BC29104BAB; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Weihong Zhang , "Kirill A . Shutemov" Subject: [PATCHv10 13/15] selftests/x86/lam: Add io_uring test cases for linear-address masking Date: Tue, 18 Oct 2022 14:33:56 +0300 Message-Id: <20221018113358.7833-14-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Weihong Zhang LAM should be supported in kernel thread, using io_uring to verify LAM feat= ure. The test cases implement read a file through io_uring, the test cases choos= e an iovec array as receiving buffer, which used to receive data, according to L= AM mode, set metadata in high bits of these buffer. io_uring can deal with these buffers that pointed to pointers with the meta= data in high bits. Signed-off-by: Weihong Zhang Signed-off-by: Kirill A. Shutemov --- tools/testing/selftests/x86/lam.c | 341 +++++++++++++++++++++++++++++- 1 file changed, 339 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/x86/lam.c b/tools/testing/selftests/x8= 6/lam.c index cdc6e40e00e0..8ea1fcef4c9f 100644 --- a/tools/testing/selftests/x86/lam.c +++ b/tools/testing/selftests/x86/lam.c @@ -9,8 +9,12 @@ #include #include #include +#include +#include #include =20 +#include +#include #include "../kselftest.h" =20 #ifndef __x86_64__ @@ -32,8 +36,9 @@ #define FUNC_BITS 0x2 #define FUNC_MMAP 0x4 #define FUNC_SYSCALL 0x8 +#define FUNC_URING 0x10 =20 -#define TEST_MASK 0xf +#define TEST_MASK 0x1f =20 #define LOW_ADDR (0x1UL << 30) #define HIGH_ADDR (0x3UL << 48) @@ -42,6 +47,13 @@ =20 #define PAGE_SIZE (4 << 10) =20 +#define barrier() ({ \ + __asm__ __volatile__("" : : : "memory"); \ +}) + +#define URING_QUEUE_SZ 1 +#define URING_BLOCK_SZ 2048 + struct testcases { unsigned int later; int expected; /* 2: SIGSEGV Error; 1: other errors */ @@ -51,6 +63,33 @@ struct testcases { const char *msg; }; =20 +/* Used by CQ of uring, source file handler and file's size */ +struct file_io { + int file_fd; + off_t file_sz; + struct iovec iovecs[]; +}; + +struct io_uring_queue { + unsigned int *head; + unsigned int *tail; + unsigned int *ring_mask; + unsigned int *ring_entries; + unsigned int *flags; + unsigned int *array; + union { + struct io_uring_cqe *cqes; + struct io_uring_sqe *sqes; + } queue; + size_t ring_sz; +}; + +struct io_ring { + int ring_fd; + struct io_uring_queue sq_ring; + struct io_uring_queue cq_ring; +}; + int tests_cnt; jmp_buf segv_env; =20 @@ -294,6 +333,285 @@ static int handle_syscall(struct testcases *test) return ret; } =20 +int sys_uring_setup(unsigned int entries, struct io_uring_params *p) +{ + return (int)syscall(__NR_io_uring_setup, entries, p); +} + +int sys_uring_enter(int fd, unsigned int to, unsigned int min, unsigned in= t flags) +{ + return (int)syscall(__NR_io_uring_enter, fd, to, min, flags, NULL, 0); +} + +/* Init submission queue and completion queue */ +int mmap_io_uring(struct io_uring_params p, struct io_ring *s) +{ + struct io_uring_queue *sring =3D &s->sq_ring; + struct io_uring_queue *cring =3D &s->cq_ring; + + sring->ring_sz =3D p.sq_off.array + p.sq_entries * sizeof(unsigned int); + cring->ring_sz =3D p.cq_off.cqes + p.cq_entries * sizeof(struct io_uring_= cqe); + + if (p.features & IORING_FEAT_SINGLE_MMAP) { + if (cring->ring_sz > sring->ring_sz) + sring->ring_sz =3D cring->ring_sz; + + cring->ring_sz =3D sring->ring_sz; + } + + void *sq_ptr =3D mmap(0, sring->ring_sz, PROT_READ | PROT_WRITE, + MAP_SHARED | MAP_POPULATE, s->ring_fd, + IORING_OFF_SQ_RING); + + if (sq_ptr =3D=3D MAP_FAILED) { + perror("sub-queue!"); + return 1; + } + + void *cq_ptr =3D sq_ptr; + + if (!(p.features & IORING_FEAT_SINGLE_MMAP)) { + cq_ptr =3D mmap(0, cring->ring_sz, PROT_READ | PROT_WRITE, + MAP_SHARED | MAP_POPULATE, s->ring_fd, + IORING_OFF_CQ_RING); + if (cq_ptr =3D=3D MAP_FAILED) { + perror("cpl-queue!"); + munmap(sq_ptr, sring->ring_sz); + return 1; + } + } + + sring->head =3D sq_ptr + p.sq_off.head; + sring->tail =3D sq_ptr + p.sq_off.tail; + sring->ring_mask =3D sq_ptr + p.sq_off.ring_mask; + sring->ring_entries =3D sq_ptr + p.sq_off.ring_entries; + sring->flags =3D sq_ptr + p.sq_off.flags; + sring->array =3D sq_ptr + p.sq_off.array; + + /* Map a queue as mem map */ + s->sq_ring.queue.sqes =3D mmap(0, p.sq_entries * sizeof(struct io_uring_s= qe), + PROT_READ | PROT_WRITE, MAP_SHARED | MAP_POPULATE, + s->ring_fd, IORING_OFF_SQES); + if (s->sq_ring.queue.sqes =3D=3D MAP_FAILED) { + munmap(sq_ptr, sring->ring_sz); + if (sq_ptr !=3D cq_ptr) { + ksft_print_msg("failed to mmap uring queue!"); + munmap(cq_ptr, cring->ring_sz); + return 1; + } + } + + cring->head =3D cq_ptr + p.cq_off.head; + cring->tail =3D cq_ptr + p.cq_off.tail; + cring->ring_mask =3D cq_ptr + p.cq_off.ring_mask; + cring->ring_entries =3D cq_ptr + p.cq_off.ring_entries; + cring->queue.cqes =3D cq_ptr + p.cq_off.cqes; + + return 0; +} + +/* Init io_uring queues */ +int setup_io_uring(struct io_ring *s) +{ + struct io_uring_params para; + + memset(¶, 0, sizeof(para)); + s->ring_fd =3D sys_uring_setup(URING_QUEUE_SZ, ¶); + if (s->ring_fd < 0) + return 1; + + return mmap_io_uring(para, s); +} + +/* + * Get data from completion queue. the data buffer saved the file data + * return 0: success; others: error; + */ +int handle_uring_cq(struct io_ring *s) +{ + struct file_io *fi =3D NULL; + struct io_uring_queue *cring =3D &s->cq_ring; + struct io_uring_cqe *cqe; + unsigned int head; + off_t len =3D 0; + + head =3D *cring->head; + + do { + barrier(); + if (head =3D=3D *cring->tail) + break; + /* Get the entry */ + cqe =3D &cring->queue.cqes[head & *s->cq_ring.ring_mask]; + fi =3D (struct file_io *)cqe->user_data; + if (cqe->res < 0) + break; + + int blocks =3D (int)(fi->file_sz + URING_BLOCK_SZ - 1) / URING_BLOCK_SZ; + + for (int i =3D 0; i < blocks; i++) + len +=3D fi->iovecs[i].iov_len; + + head++; + } while (1); + + *cring->head =3D head; + barrier(); + + return (len !=3D fi->file_sz); +} + +/* + * Submit squeue. specify via IORING_OP_READV. + * the buffer need to be set metadata according to LAM mode + */ +int handle_uring_sq(struct io_ring *ring, struct file_io *fi, unsigned lon= g lam) +{ + int file_fd =3D fi->file_fd; + struct io_uring_queue *sring =3D &ring->sq_ring; + unsigned int index =3D 0, cur_block =3D 0, tail =3D 0, next_tail =3D 0; + struct io_uring_sqe *sqe; + + off_t remain =3D fi->file_sz; + int blocks =3D (int)(remain + URING_BLOCK_SZ - 1) / URING_BLOCK_SZ; + + while (remain) { + off_t bytes =3D remain; + void *buf; + + if (bytes > URING_BLOCK_SZ) + bytes =3D URING_BLOCK_SZ; + + fi->iovecs[cur_block].iov_len =3D bytes; + + if (posix_memalign(&buf, URING_BLOCK_SZ, URING_BLOCK_SZ)) + return 1; + + fi->iovecs[cur_block].iov_base =3D (void *)set_metadata((uint64_t)buf, l= am); + remain -=3D bytes; + cur_block++; + } + + next_tail =3D *sring->tail; + tail =3D next_tail; + next_tail++; + + barrier(); + + index =3D tail & *ring->sq_ring.ring_mask; + + sqe =3D &ring->sq_ring.queue.sqes[index]; + sqe->fd =3D file_fd; + sqe->flags =3D 0; + sqe->opcode =3D IORING_OP_READV; + sqe->addr =3D (unsigned long)fi->iovecs; + sqe->len =3D blocks; + sqe->off =3D 0; + sqe->user_data =3D (uint64_t)fi; + + sring->array[index] =3D index; + tail =3D next_tail; + + if (*sring->tail !=3D tail) { + *sring->tail =3D tail; + barrier(); + } + + if (sys_uring_enter(ring->ring_fd, 1, 1, IORING_ENTER_GETEVENTS) < 0) + return 1; + + return 0; +} + +/* + * Test LAM in async I/O and io_uring, read current binery through io_uring + * Set metadata in pointers to iovecs buffer. + */ +int do_uring(unsigned long lam) +{ + struct io_ring *ring; + struct file_io *fi; + struct stat st; + int ret =3D 1; + char path[PATH_MAX]; + + /* get current process path */ + if (readlink("/proc/self/exe", path, PATH_MAX) <=3D 0) + return 1; + + int file_fd =3D open(path, O_RDONLY); + + if (file_fd < 0) + return 1; + + if (fstat(file_fd, &st) < 0) + return 1; + + off_t file_sz =3D st.st_size; + + int blocks =3D (int)(file_sz + URING_BLOCK_SZ - 1) / URING_BLOCK_SZ; + + fi =3D malloc(sizeof(*fi) + sizeof(struct iovec) * blocks); + if (!fi) + return 1; + + fi->file_sz =3D file_sz; + fi->file_fd =3D file_fd; + + ring =3D malloc(sizeof(*ring)); + if (!ring) + return 1; + + memset(ring, 0, sizeof(struct io_ring)); + + if (setup_io_uring(ring)) + goto out; + + if (handle_uring_sq(ring, fi, lam)) + goto out; + + ret =3D handle_uring_cq(ring); + +out: + free(ring); + + for (int i =3D 0; i < blocks; i++) { + if (fi->iovecs[i].iov_base) { + uint64_t addr =3D ((uint64_t)fi->iovecs[i].iov_base); + + switch (lam) { + case LAM_U57_BITS: /* Clear bits 62:57 */ + addr =3D (addr & ~(0x3fULL << 57)); + break; + } + free((void *)addr); + fi->iovecs[i].iov_base =3D NULL; + } + } + + free(fi); + + return ret; +} + +int handle_uring(struct testcases *test) +{ + int ret =3D 0; + + if (test->later =3D=3D 0 && test->lam !=3D 0) + if (set_lam(test->lam) !=3D 0) + return 1; + + if (sigsetjmp(segv_env, 1) =3D=3D 0) { + signal(SIGSEGV, segv_handler); + ret =3D do_uring(test->lam); + } else { + ret =3D 2; + } + + return ret; +} + static int fork_test(struct testcases *test) { int ret, child_ret; @@ -340,6 +658,22 @@ static void run_test(struct testcases *test, int count) } } =20 +static struct testcases uring_cases[] =3D { + { + .later =3D 0, + .lam =3D LAM_U57_BITS, + .test_func =3D handle_uring, + .msg =3D "URING: LAM_U57. Dereferencing pointer with metadata\n", + }, + { + .later =3D 1, + .expected =3D 1, + .lam =3D LAM_U57_BITS, + .test_func =3D handle_uring, + .msg =3D "URING:[Negative] Disable LAM. Dereferencing pointer with metad= ata.\n", + }, +}; + static struct testcases malloc_cases[] =3D { { .later =3D 0, @@ -410,7 +744,7 @@ static void cmd_help(void) { printf("usage: lam [-h] [-t test list]\n"); printf("\t-t test list: run tests specified in the test list, default:0x%= x\n", TEST_MASK); - printf("\t\t0x1:malloc; 0x2:max_bits; 0x4:mmap; 0x8:syscall.\n"); + printf("\t\t0x1:malloc; 0x2:max_bits; 0x4:mmap; 0x8:syscall; 0x10:io_urin= g.\n"); printf("\t-h: help\n"); } =20 @@ -456,6 +790,9 @@ int main(int argc, char **argv) if (tests & FUNC_SYSCALL) run_test(syscall_cases, ARRAY_SIZE(syscall_cases)); =20 + if (tests & FUNC_URING) + run_test(uring_cases, ARRAY_SIZE(uring_cases)); + ksft_set_plan(tests_cnt); =20 return ksft_exit_pass(); --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FF85C433FE for ; Tue, 18 Oct 2022 11:37:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230314AbiJRLhB (ORCPT ); Tue, 18 Oct 2022 07:37:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230282AbiJRLgs (ORCPT ); Tue, 18 Oct 2022 07:36:48 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E7EDA0266 for ; Tue, 18 Oct 2022 04:35:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666092948; x=1697628948; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2PBgo8dzetbAgvNxQe4E7GoQrbgUDaybtLdJFJyGEss=; b=Fmi0cMfWUggtBEVDTPdQFjGyi4MGNN/kn5RRpLdcKfShxAx0kBovRf1H N1Y4zxmoN3w8sbDPZnsWCwiamdPwmIqnnfwccBuiguLMzP+XbLbw5L586 UAW2daYv5+q5kxaasFPyxyKJRbPlDzGvqIqXpBtKycYbqLdi8XiBIPxDU CzAe6hAkgRERfOgEbHQ4QM5243IEC2ilWDl6CrMfljNzS67YSmmF0CpkS cwqKqUvclOVVOufusB65V6HpXijTbXWImoPlXSypHq/83wHt5bD0z2d3d OpO5LEeY8s4OZuHlzWBXgjib0kPgjAD4r3C7DCgiKm8IFQD90o4Axiiq3 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="392382138" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="392382138" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:19 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10503"; a="661861194" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="661861194" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:13 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 86D21104BAC; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Weihong Zhang , "Kirill A . Shutemov" Subject: [PATCHv10 14/15] selftests/x86/lam: Add inherit test cases for linear-address masking Date: Tue, 18 Oct 2022 14:33:57 +0300 Message-Id: <20221018113358.7833-15-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Weihong Zhang LAM is enabled per-thread and gets inherited on fork(2)/clone(2). exec() reverts LAM status to the default disabled state. There are two test scenarios: - Fork test cases: These cases were used to test the inheritance of LAM for per-thread, Child process generated by fork() should inherit LAM feature from parent process, Child process can get the LAM mode same as parent process. - Execve test cases: Processes generated by execve() are different from processes generated by fork(), these processes revert LAM status to disabled status. Signed-off-by: Weihong Zhang Signed-off-by: Kirill A. Shutemov --- tools/testing/selftests/x86/lam.c | 125 +++++++++++++++++++++++++++++- 1 file changed, 121 insertions(+), 4 deletions(-) diff --git a/tools/testing/selftests/x86/lam.c b/tools/testing/selftests/x8= 6/lam.c index 8ea1fcef4c9f..cfc9073c0262 100644 --- a/tools/testing/selftests/x86/lam.c +++ b/tools/testing/selftests/x86/lam.c @@ -37,8 +37,9 @@ #define FUNC_MMAP 0x4 #define FUNC_SYSCALL 0x8 #define FUNC_URING 0x10 +#define FUNC_INHERITE 0x20 =20 -#define TEST_MASK 0x1f +#define TEST_MASK 0x3f =20 #define LOW_ADDR (0x1UL << 30) #define HIGH_ADDR (0x3UL << 48) @@ -174,6 +175,28 @@ static unsigned long get_default_tag_bits(void) return lam; } =20 +/* + * Set tagged address and read back untag mask. + * check if the untag mask is expected. + */ +static int get_lam(void) +{ + uint64_t ptr =3D 0; + int ret =3D -1; + /* Get untagged mask */ + if (syscall(SYS_arch_prctl, ARCH_GET_UNTAG_MASK, &ptr) =3D=3D -1) + return -1; + + /* Check mask returned is expected */ + if (ptr =3D=3D ~(LAM_U57_MASK)) + ret =3D LAM_U57_BITS; + else if (ptr =3D=3D -1ULL) + ret =3D LAM_NONE; + + + return ret; +} + /* According to LAM mode, set metadata in high bits */ static uint64_t set_metadata(uint64_t src, unsigned long lam) { @@ -581,7 +604,7 @@ int do_uring(unsigned long lam) =20 switch (lam) { case LAM_U57_BITS: /* Clear bits 62:57 */ - addr =3D (addr & ~(0x3fULL << 57)); + addr =3D (addr & ~(LAM_U57_MASK)); break; } free((void *)addr); @@ -632,6 +655,72 @@ static int fork_test(struct testcases *test) return ret; } =20 +static int handle_execve(struct testcases *test) +{ + int ret, child_ret; + int lam =3D test->lam; + pid_t pid; + + pid =3D fork(); + if (pid < 0) { + perror("Fork failed."); + ret =3D 1; + } else if (pid =3D=3D 0) { + char path[PATH_MAX]; + + /* Set LAM mode in parent process */ + if (set_lam(lam) !=3D 0) + return 1; + + /* Get current binary's path and the binary was run by execve */ + if (readlink("/proc/self/exe", path, PATH_MAX) <=3D 0) + exit(-1); + + /* run binary to get LAM mode and return to parent process */ + if (execlp(path, path, "-t 0x0", NULL) < 0) { + perror("error on exec"); + exit(-1); + } + } else { + wait(&child_ret); + ret =3D WEXITSTATUS(child_ret); + if (ret !=3D LAM_NONE) + return 1; + } + + return 0; +} + +static int handle_inheritance(struct testcases *test) +{ + int ret, child_ret; + int lam =3D test->lam; + pid_t pid; + + /* Set LAM mode in parent process */ + if (set_lam(lam) !=3D 0) + return 1; + + pid =3D fork(); + if (pid < 0) { + perror("Fork failed."); + return 1; + } else if (pid =3D=3D 0) { + /* Set LAM mode in parent process */ + int child_lam =3D get_lam(); + + exit(child_lam); + } else { + wait(&child_ret); + ret =3D WEXITSTATUS(child_ret); + + if (lam !=3D ret) + return 1; + } + + return 0; +} + static void run_test(struct testcases *test, int count) { int i, ret =3D 0; @@ -740,11 +829,26 @@ static struct testcases mmap_cases[] =3D { }, }; =20 +static struct testcases inheritance_cases[] =3D { + { + .expected =3D 0, + .lam =3D LAM_U57_BITS, + .test_func =3D handle_inheritance, + .msg =3D "FORK: LAM_U57, child process should get LAM mode same as paren= t\n", + }, + { + .expected =3D 0, + .lam =3D LAM_U57_BITS, + .test_func =3D handle_execve, + .msg =3D "EXECVE: LAM_U57, child process should get disabled LAM mode\n", + }, +}; + static void cmd_help(void) { printf("usage: lam [-h] [-t test list]\n"); printf("\t-t test list: run tests specified in the test list, default:0x%= x\n", TEST_MASK); - printf("\t\t0x1:malloc; 0x2:max_bits; 0x4:mmap; 0x8:syscall; 0x10:io_urin= g.\n"); + printf("\t\t0x1:malloc; 0x2:max_bits; 0x4:mmap; 0x8:syscall; 0x10:io_urin= g; 0x20:inherit;\n"); printf("\t-h: help\n"); } =20 @@ -764,7 +868,7 @@ int main(int argc, char **argv) switch (c) { case 't': tests =3D strtoul(optarg, NULL, 16); - if (!(tests & TEST_MASK)) { + if (tests && !(tests & TEST_MASK)) { ksft_print_msg("Invalid argument!\n"); return -1; } @@ -778,6 +882,16 @@ int main(int argc, char **argv) } } =20 + /* + * When tests is 0, it is not a real test case; + * the option used by test case(execve) to check the lam mode in + * process generated by execve, the process read back lam mode and + * check with lam mode in parent process. + */ + if (!tests) + return (get_lam()); + + /* Run test cases */ if (tests & FUNC_MALLOC) run_test(malloc_cases, ARRAY_SIZE(malloc_cases)); =20 @@ -793,6 +907,9 @@ int main(int argc, char **argv) if (tests & FUNC_URING) run_test(uring_cases, ARRAY_SIZE(uring_cases)); =20 + if (tests & FUNC_INHERITE) + run_test(inheritance_cases, ARRAY_SIZE(inheritance_cases)); + ksft_set_plan(tests_cnt); =20 return ksft_exit_pass(); --=20 2.38.0 From nobody Tue Apr 7 17:34:03 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AA2EC433FE for ; Tue, 18 Oct 2022 11:37:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230324AbiJRLhG (ORCPT ); Tue, 18 Oct 2022 07:37:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230215AbiJRLgt (ORCPT ); Tue, 18 Oct 2022 07:36:49 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B2EC8768E for ; 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a="691763237" X-IronPort-AV: E=Sophos;i="5.95,193,1661842800"; d="scan'208";a="691763237" Received: from vhavel-mobl.ger.corp.intel.com (HELO box.shutemov.name) ([10.252.51.115]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2022 04:34:19 -0700 Received: by box.shutemov.name (Postfix, from userid 1000) id 91A72104BAD; Tue, 18 Oct 2022 14:34:04 +0300 (+03) From: "Kirill A. Shutemov" To: Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: x86@kernel.org, Kostya Serebryany , Andrey Ryabinin , Andrey Konovalov , Alexander Potapenko , Taras Madan , Dmitry Vyukov , "H . J . Lu" , Andi Kleen , Rick Edgecombe , Bharata B Rao , Jacob Pan , Ashok Raj , linux-mm@kvack.org, linux-kernel@vger.kernel.org, Weihong Zhang , "Kirill A . Shutemov" Subject: [PATCHv10 15/15] selftests/x86/lam: Add ARCH_FORCE_TAGGED_SVM test cases for linear-address masking Date: Tue, 18 Oct 2022 14:33:58 +0300 Message-Id: <20221018113358.7833-16-kirill.shutemov@linux.intel.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> References: <20221018113358.7833-1-kirill.shutemov@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Weihong Zhang By default do not allow to enable both LAM and use SVM in the same process. The new ARCH_FORCE_TAGGED_SVM arch_prctl() overrides the limitation. Add new test cases for the new arch_prctl: Defore using ARCH_FORCE_TAGGED_SVM, should not allow to enable LAM/SVM coexisting. the test cases should be negative. The test depands on idxd driver and iommu. before test, need add "intel_iommu=3Don,sm_on" in kernel command line and insmod idxd driver. Signed-off-by: Weihong Zhang Signed-off-by: Kirill A. Shutemov --- tools/testing/selftests/x86/lam.c | 237 +++++++++++++++++++++++++++++- 1 file changed, 235 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/x86/lam.c b/tools/testing/selftests/x8= 6/lam.c index cfc9073c0262..4b9da41de5c8 100644 --- a/tools/testing/selftests/x86/lam.c +++ b/tools/testing/selftests/x86/lam.c @@ -30,6 +30,7 @@ #define ARCH_GET_UNTAG_MASK 0x4001 #define ARCH_ENABLE_TAGGED_ADDR 0x4002 #define ARCH_GET_MAX_TAG_BITS 0x4003 +#define ARCH_FORCE_TAGGED_SVM 0x4004 =20 /* Specified test function bits */ #define FUNC_MALLOC 0x1 @@ -38,8 +39,9 @@ #define FUNC_SYSCALL 0x8 #define FUNC_URING 0x10 #define FUNC_INHERITE 0x20 +#define FUNC_PASID 0x40 =20 -#define TEST_MASK 0x3f +#define TEST_MASK 0x7f =20 #define LOW_ADDR (0x1UL << 30) #define HIGH_ADDR (0x3UL << 48) @@ -55,11 +57,19 @@ #define URING_QUEUE_SZ 1 #define URING_BLOCK_SZ 2048 =20 +/* Pasid test define */ +#define LAM_CMD_BIT 0x1 +#define PAS_CMD_BIT 0x2 +#define SVM_CMD_BIT 0x4 + +#define PAS_CMD(cmd1, cmd2, cmd3) (((cmd3) << 8) | ((cmd2) << 4) | ((cmd1)= << 0)) + struct testcases { unsigned int later; int expected; /* 2: SIGSEGV Error; 1: other errors */ unsigned long lam; uint64_t addr; + uint64_t cmd; int (*test_func)(struct testcases *test); const char *msg; }; @@ -556,7 +566,7 @@ int do_uring(unsigned long lam) struct file_io *fi; struct stat st; int ret =3D 1; - char path[PATH_MAX]; + char path[PATH_MAX] =3D {0}; =20 /* get current process path */ if (readlink("/proc/self/exe", path, PATH_MAX) <=3D 0) @@ -852,6 +862,226 @@ static void cmd_help(void) printf("\t-h: help\n"); } =20 +/* Check for file existence */ +uint8_t file_Exists(const char *fileName) +{ + struct stat buffer; + + uint8_t ret =3D (stat(fileName, &buffer) =3D=3D 0); + + return ret; +} + +/* Sysfs idxd files */ +const char *dsa_configs[] =3D { + "echo 1 > /sys/bus/dsa/devices/dsa0/wq0.1/group_id", + "echo shared > /sys/bus/dsa/devices/dsa0/wq0.1/mode", + "echo 10 > /sys/bus/dsa/devices/dsa0/wq0.1/priority", + "echo 16 > /sys/bus/dsa/devices/dsa0/wq0.1/size", + "echo 15 > /sys/bus/dsa/devices/dsa0/wq0.1/threshold", + "echo user > /sys/bus/dsa/devices/dsa0/wq0.1/type", + "echo MyApp1 > /sys/bus/dsa/devices/dsa0/wq0.1/name", + "echo 1 > /sys/bus/dsa/devices/dsa0/engine0.1/group_id", + "echo dsa0 > /sys/bus/dsa/drivers/idxd/bind", + /* bind files and devices, generated a device file in /dev */ + "echo wq0.1 > /sys/bus/dsa/drivers/user/bind", +}; + +/* DSA device file */ +const char *dsaDeviceFile =3D "/dev/dsa/wq0.1"; +/* file for io*/ +const char *dsaPasidEnable =3D "/sys/bus/dsa/devices/dsa0/pasid_enabled"; + +/* + * DSA depends on kernel cmdline "intel_iommu=3Don,sm_on" + * return pasid_enabled (0: disable 1:enable) + */ +int Check_DSA_Kernel_Setting(void) +{ + char command[256] =3D ""; + char buf[256] =3D ""; + char *ptr; + int rv =3D -1; + + snprintf(command, sizeof(command) - 1, "cat %s", dsaPasidEnable); + + FILE *cmd =3D popen(command, "r"); + + if (cmd) { + while (fgets(buf, sizeof(buf) - 1, cmd) !=3D NULL); + + pclose(cmd); + rv =3D strtol(buf, &ptr, 16); + } + + return rv; +} + +/* + * Config DSA's sysfs files as shared DSA's WQ. + * Generated a device file /dev/dsa/wq0.1 + * Return: 0 OK; 1 Failed; 3 Skip(SVM disabled). + */ +int Dsa_Init_Sysfs(void) +{ + uint len =3D ARRAY_SIZE(dsa_configs); + const char **p =3D dsa_configs; + + if (file_Exists(dsaDeviceFile) =3D=3D 1) + return 0; + + /* check the idxd driver */ + if (file_Exists(dsaPasidEnable) !=3D 1) { + printf("Please make sure idxd driver was loaded\n"); + return 3; + } + + /* Check SVM feature */ + if (Check_DSA_Kernel_Setting() !=3D 1) { + printf("Please enable SVM.(Add intel_iommu=3Don,sm_on in kernel cmdline)= \n"); + return 3; + } + + /* Check the idxd device file on /dev/dsa/ */ + for (int i =3D 0; i < len; i++) { + if (system(p[i])) + return 1; + } + + /* After config, /dev/dsa/wq0.1 should be generated */ + return (file_Exists(dsaDeviceFile) !=3D 1); +} + +/* + * Open DSA device file, triger API: iommu_sva_alloc_pasid + */ +void *allocate_dsa_pasid(void) +{ + int fd; + void *wq; + + fd =3D open(dsaDeviceFile, O_RDWR); + if (fd < 0) { + perror("open"); + return MAP_FAILED; + } + + wq =3D mmap(NULL, 0x1000, PROT_WRITE, + MAP_SHARED | MAP_POPULATE, fd, 0); + if (wq =3D=3D MAP_FAILED) + perror("mmap"); + + return wq; +} + +int set_force_svm(void) +{ + int ret =3D 0; + + ret =3D syscall(SYS_arch_prctl, ARCH_FORCE_TAGGED_SVM); + + return ret; +} + +int handle_pasid(struct testcases *test) +{ + uint tmp =3D test->cmd; + uint runed =3D 0x0; + int ret =3D 0; + void *wq =3D NULL; + + ret =3D Dsa_Init_Sysfs(); + if (ret !=3D 0) + return ret; + + for (int i =3D 0; i < 3; i++) { + int err =3D 0; + + if (tmp & 0x1) { + /* run set lam mode*/ + if ((runed & 0x1) =3D=3D 0) { + err =3D set_lam(LAM_U57_BITS); + runed =3D runed | 0x1; + } else + err =3D 1; + } else if (tmp & 0x4) { + /* run force svm */ + if ((runed & 0x4) =3D=3D 0) { + err =3D set_force_svm(); + runed =3D runed | 0x4; + } else + err =3D 1; + } else if (tmp & 0x2) { + /* run allocate pasid */ + if ((runed & 0x2) =3D=3D 0) { + runed =3D runed | 0x2; + wq =3D allocate_dsa_pasid(); + if (wq =3D=3D MAP_FAILED) + err =3D 1; + } else + err =3D 1; + } + + ret =3D ret + err; + if (ret > 0) + break; + + tmp =3D tmp >> 4; + } + + if (wq !=3D MAP_FAILED && wq !=3D NULL) + if (munmap(wq, 0x1000)) + printf("munmap failed %d\n", errno); + + if (runed !=3D 0x7) + ret =3D 1; + + return (ret !=3D 0); +} + +/* + * Pasid test depends on idxd and SVM, kernel should enable iommu and sm. + * command line(intel_iommu=3Don,sm_on) + */ +static struct testcases pasid_cases[] =3D { + { + .expected =3D 1, + .cmd =3D PAS_CMD(LAM_CMD_BIT, PAS_CMD_BIT, SVM_CMD_BIT), + .test_func =3D handle_pasid, + .msg =3D "PASID: [Negative] Execute LAM, PASID, SVM in sequence\n", + }, + { + .expected =3D 0, + .cmd =3D PAS_CMD(LAM_CMD_BIT, SVM_CMD_BIT, PAS_CMD_BIT), + .test_func =3D handle_pasid, + .msg =3D "PASID: Execute LAM, SVM, PASID in sequence\n", + }, + { + .expected =3D 1, + .cmd =3D PAS_CMD(PAS_CMD_BIT, LAM_CMD_BIT, SVM_CMD_BIT), + .test_func =3D handle_pasid, + .msg =3D "PASID: [Negative] Execute PASID, LAM, SVM in sequence\n", + }, + { + .expected =3D 0, + .cmd =3D PAS_CMD(PAS_CMD_BIT, SVM_CMD_BIT, LAM_CMD_BIT), + .test_func =3D handle_pasid, + .msg =3D "PASID: Execute PASID, SVM, LAM in sequence\n", + }, + { + .expected =3D 0, + .cmd =3D PAS_CMD(SVM_CMD_BIT, LAM_CMD_BIT, PAS_CMD_BIT), + .test_func =3D handle_pasid, + .msg =3D "PASID: Execute SVM, LAM, PASID in sequence\n", + }, + { + .expected =3D 0, + .cmd =3D PAS_CMD(SVM_CMD_BIT, PAS_CMD_BIT, LAM_CMD_BIT), + .test_func =3D handle_pasid, + .msg =3D "PASID: Execute SVM, PASID, LAM in sequence\n", + }, +}; + int main(int argc, char **argv) { int c =3D 0; @@ -910,6 +1140,9 @@ int main(int argc, char **argv) if (tests & FUNC_INHERITE) run_test(inheritance_cases, ARRAY_SIZE(inheritance_cases)); =20 + if (tests & FUNC_PASID) + run_test(pasid_cases, ARRAY_SIZE(pasid_cases)); + ksft_set_plan(tests_cnt); =20 return ksft_exit_pass(); --=20 2.38.0