From nobody Tue Apr 7 15:56:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29124C4332F for ; Tue, 18 Oct 2022 03:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229925AbiJRD5q (ORCPT ); Mon, 17 Oct 2022 23:57:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229898AbiJRD5l (ORCPT ); Mon, 17 Oct 2022 23:57:41 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAF1187095 for ; Mon, 17 Oct 2022 20:57:39 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id b2so12654482plc.7 for ; Mon, 17 Oct 2022 20:57:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/5SY8Nah0OJo40Eqd9ufrxakceznyXcaJJucJXEE6R0=; b=m3Yt3QI6+Z/DrLslxPJ/GzJKEJbJxlIPy8KAYZmEIRcp609iOKz/1AXizo0Chsx+uk ldcx7+d5tpLrsL/TW3piXuuC9bCYwaXfh7MoSV69B5rEG0ycLHN/v2/PNpBvwi03yFqu gFUwj9zrzvuH1GSY26F8RA0v/zQ7eMhlGc7ko= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/5SY8Nah0OJo40Eqd9ufrxakceznyXcaJJucJXEE6R0=; b=IMMok14L1I80y6SRb/0ecYESjVEgQYY7CHgs7iJozm86Ts7nK/6KM8F2zPq8wu9qLa bFoAYF5M0osRJkhW0oW9vHYJEFmunvagQG/OD321Hi7zjEPFvPX4wSg/ByiVQDXw/+HA tH3D7oU1ysEKO9nKKf0lB/pkVY+LTQSNY2CKSwthWuczgssS0ND/nIOrmJi+xSq87mSY fObPsMhPUZ//X9Kj4DOYzpoRuC6UBlIaWgD3s79SISGZTt+f7qepQr9VeoCxCT5TorVH LliaodepI1TzoqX1hltGcncDLvpVRaNZPboBHC1lQBaKsZktcZG5uQ45acsZ/vlV7KGJ Ek1A== X-Gm-Message-State: ACrzQf07CZ9xx8RAvXdR2jbCvw1cqzI07QRWLuUhzzo0gGg3b8tR8MSo MOdMqpu19FUYO8Y7R0n8LUtV/007la5JSg== X-Google-Smtp-Source: AMsMyM6NWclKdvs2x3bS5AOs5cN15w5Ryx1WxcO+ICS16eS1oY7gmJdDCaLLyh3ZZaWCGlKUVoUPWw== X-Received: by 2002:a17:902:8e84:b0:178:71f2:113c with SMTP id bg4-20020a1709028e8400b0017871f2113cmr948888plb.79.1666065459409; Mon, 17 Oct 2022 20:57:39 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:2ac3:f4e2:e908:c393]) by smtp.gmail.com with UTF8SMTPSA id h9-20020aa79f49000000b00537fb1f9f25sm7972272pfr.110.2022.10.17.20.57.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 20:57:38 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris , stable@vger.kernel.org Subject: [PATCH 1/5] mmc: sdhci-of-arasan: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:20 -0700 Message-Id: <20221017205610.1.I29f6a2189e84e35ad89c1833793dca9e36c64297@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but one particular case I hit commonly enough: mmc_suspend() -> mmc_power_off(). Typically we will eventually deactivate CQE (cqhci_suspend() -> cqhci_deactivate()), but that's not guaranteed -- in particular, if we perform a partial (e.g., interrupted) system suspend. The same bug was already found and fixed for two other drivers, in v5.7 and v5.9: 5cf583f1fb9c mmc: sdhci-msm: Deactivate CQE during SDHC reset df57d73276b8 mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-ba= sed controllers The latter is especially prescient, saying "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." So like these other patches, deactivate CQHCI when resetting the controller. Also, move around the DT/caps handling, because sdhci_setup_host() performs resets before we've initialized CQHCI. This is the pattern followed in other SDHCI/CQHCI drivers. Fixes: 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sd= hci-5.1") Cc: Signed-off-by: Brian Norris Reviewed-by: Guenter Roeck --- drivers/mmc/host/sdhci-of-arasan.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of= -arasan.c index 3997cad1f793..1988a703781a 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -366,6 +366,10 @@ static void sdhci_arasan_reset(struct sdhci_host *host= , u8 mask) struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_arasan_data *sdhci_arasan =3D sdhci_pltfm_priv(pltfm_host); =20 + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + sdhci_arasan->has_cqe) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); =20 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { @@ -1521,7 +1525,8 @@ static int sdhci_arasan_register_sdclk(struct sdhci_a= rasan_data *sdhci_arasan, return 0; } =20 -static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan) +static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan, + struct device_node *np) { struct sdhci_host *host =3D sdhci_arasan->host; struct cqhci_host *cq_host; @@ -1549,6 +1554,10 @@ static int sdhci_arasan_add_host(struct sdhci_arasan= _data *sdhci_arasan) if (dma64) cq_host->caps |=3D CQHCI_TASK_DESC_SZ_128; =20 + host->mmc->caps2 |=3D MMC_CAP2_CQE; + if (!of_property_read_bool(np, "disable-cqe-dcmd")) + host->mmc->caps2 |=3D MMC_CAP2_CQE_DCMD; + ret =3D cqhci_init(cq_host, host->mmc, dma64); if (ret) goto cleanup; @@ -1705,13 +1714,9 @@ static int sdhci_arasan_probe(struct platform_device= *pdev) host->mmc_host_ops.start_signal_voltage_switch =3D sdhci_arasan_voltage_switch; sdhci_arasan->has_cqe =3D true; - host->mmc->caps2 |=3D MMC_CAP2_CQE; - - if (!of_property_read_bool(np, "disable-cqe-dcmd")) - host->mmc->caps2 |=3D MMC_CAP2_CQE_DCMD; } =20 - ret =3D sdhci_arasan_add_host(sdhci_arasan); + ret =3D sdhci_arasan_add_host(sdhci_arasan, np); if (ret) goto err_add_host; =20 --=20 2.38.0.413.g74048e4d9e-goog From nobody Tue Apr 7 15:56:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECFDFC433FE for ; Tue, 18 Oct 2022 03:57:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229933AbiJRD5w (ORCPT ); Mon, 17 Oct 2022 23:57:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229935AbiJRD5n (ORCPT ); Mon, 17 Oct 2022 23:57:43 -0400 Received: from mail-pg1-x532.google.com (mail-pg1-x532.google.com [IPv6:2607:f8b0:4864:20::532]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1B9187F99 for ; Mon, 17 Oct 2022 20:57:42 -0700 (PDT) Received: by mail-pg1-x532.google.com with SMTP id q1so12213349pgl.11 for ; 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Mon, 17 Oct 2022 20:57:42 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:2ac3:f4e2:e908:c393]) by smtp.gmail.com with UTF8SMTPSA id r8-20020aa79628000000b0056699fcdf6bsm7127084pfg.84.2022.10.17.20.57.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 20:57:41 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris Subject: [PATCH 2/5] mmc: sdhci-brcmstb: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:21 -0700 Message-Id: <20221017205610.2.I6a715feab6d01f760455865e968ecf0d85036018@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Move around the CQE caps handling, because sdhci_setup_host() performs resets before we've initialized CQHCI. This is the pattern followed in other SDHCI/CQHCI drivers. Fixes: d46ba2d17f90 ("mmc: sdhci-brcmstb: Add support for Command Queuing (= CQE)") Signed-off-by: Brian Norris --- drivers/mmc/host/sdhci-brcmstb.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index aff36a933ebe..7f4bb362b923 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -55,6 +55,10 @@ static void brcmstb_reset(struct sdhci_host *host, u8 ma= sk) struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); =20 + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + (priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE)) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); =20 /* Reset will clear this, so re-enable it */ @@ -209,7 +213,6 @@ static int sdhci_brcmstb_add_host(struct sdhci_host *ho= st, return sdhci_add_host(host); =20 dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); - host->mmc->caps2 |=3D MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; ret =3D sdhci_setup_host(host); if (ret) return ret; @@ -230,6 +233,8 @@ static int sdhci_brcmstb_add_host(struct sdhci_host *ho= st, cq_host->caps |=3D CQHCI_TASK_DESC_SZ_128; } =20 + host->mmc->caps2 |=3D MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; + ret =3D cqhci_init(cq_host, host->mmc, dma64); if (ret) goto cleanup; --=20 2.38.0.413.g74048e4d9e-goog From nobody Tue Apr 7 15:56:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E81E4C433FE for ; Tue, 18 Oct 2022 03:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230099AbiJRD6M (ORCPT ); Mon, 17 Oct 2022 23:58:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229934AbiJRD5r (ORCPT ); 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Mon, 17 Oct 2022 20:57:44 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris Subject: [PATCH 3/5] mms: sdhci-esdhc-imx: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:22 -0700 Message-Id: <20221017205610.3.I7d01f9ad11bacdc9213dee61b7918982aea39115@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Fixes: bb6e358169bf ("mmc: sdhci-esdhc-imx: add CMDQ support") Signed-off-by: Brian Norris --- drivers/mmc/host/sdhci-esdhc-imx.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-es= dhc-imx.c index 55981b0f0b10..222c83929e20 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -1288,6 +1288,13 @@ static void esdhc_set_uhs_signaling(struct sdhci_hos= t *host, unsigned timing) =20 static void esdhc_reset(struct sdhci_host *host, u8 mask) { + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct pltfm_imx_data *imx_data =3D sdhci_pltfm_priv(pltfm_host); + + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + imx_data->socdata->flags & ESDHC_FLAG_CQHCI) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); =20 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); --=20 2.38.0.413.g74048e4d9e-goog From nobody Tue Apr 7 15:56:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57B00C4332F for ; Tue, 18 Oct 2022 03:58:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229914AbiJRD6Z (ORCPT ); Mon, 17 Oct 2022 23:58:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229939AbiJRD5v (ORCPT ); Mon, 17 Oct 2022 23:57:51 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4948A87F99 for ; Mon, 17 Oct 2022 20:57:48 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id y8so12910373pfp.13 for ; Mon, 17 Oct 2022 20:57:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LqIOfq4+r44BDEcAbAIaLunotKmu+d/0VAL/CFG/GZs=; b=UekqlQkGh6UA8fFw7UouK9kSktK5V9gIlB1tDGL6hleXWJrwAzg8cmt1FAgpk8CgWl a3uPfVhIqkx3w5XeROlfWH4A16t0gISqd0MOKefaZXYRf+hQ1/yA6Gu57WPgkCwc3tpv 7V4LoIT4ltSkFehTqR+xHgMgI+oJkDSxXtuqA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LqIOfq4+r44BDEcAbAIaLunotKmu+d/0VAL/CFG/GZs=; b=qs//kOwh29a8J6aPryNoEQjaaSs7sf7rOoUtWhQZsYdB0yc0JQTmgDg3qwWhdGM4Qa aBGYvFfL8s+ujTTS4+d2VhDmUMMBPXFfjVnWhHRkKE7t95kvLqVSiTLSYX0aJxdIng8l +S30SHpPlLx1iaDE5skQe1I9GrLB3eZ6ofjjKXYBAsPf9oPVmKlOPHVqUH1Z6fzKb+3/ M9KOdyFfNnoEd+RLJnciLX9edMc5JqAaJ3fCOMQhV9sZBBuMUXgAPwrfdnUIRi+TAw40 MDn1ccPfqLrZ1F+J/7xNR1q6bY0RV/j+uy/r7Eyn+ouVQOoB5XpwhqMqac90SP9oo8XM 6jdw== X-Gm-Message-State: ACrzQf1BUsmwCs3faAf3FWTi2K2k2/JaLL/K4I2ev9QzGPZ3ijRhX/Ic LNbyi/zV6LJxJAVs0wzPD3jfYw== X-Google-Smtp-Source: AMsMyM6ho3Yw2H44oOTg6yArRKh/f8YfOPn8UWoMF7c3LUoPZjSnRUSD0v76EISvEqYfqFagdhozeg== X-Received: by 2002:a63:f07:0:b0:440:5c6e:5833 with SMTP id e7-20020a630f07000000b004405c6e5833mr972776pgl.375.1666065467479; Mon, 17 Oct 2022 20:57:47 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:2ac3:f4e2:e908:c393]) by smtp.gmail.com with UTF8SMTPSA id y69-20020a62ce48000000b0054124008c14sm7955449pfg.154.2022.10.17.20.57.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 20:57:47 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris Subject: [PATCH 4/5] mmc: sdhci-tegra: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:23 -0700 Message-Id: <20221017205610.4.I418c9eaaf754880fcd2698113e8c3ef821a944d7@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Fixes: 3c4019f97978 ("mmc: tegra: HW Command Queue Support for Tegra SDMMC") Signed-off-by: Brian Norris --- drivers/mmc/host/sdhci-tegra.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2d2d8260c681..d1d1ae9b2a86 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -367,6 +367,10 @@ static void tegra_sdhci_reset(struct sdhci_host *host,= u8 mask) const struct sdhci_tegra_soc_data *soc_data =3D tegra_host->soc_data; u32 misc_ctrl, clk_ctrl, pad_ctrl; =20 + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && + tegra_host->enable_hwcq) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); =20 if (!(mask & SDHCI_RESET_ALL)) --=20 2.38.0.413.g74048e4d9e-goog From nobody Tue Apr 7 15:56:55 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0857C433FE for ; Tue, 18 Oct 2022 03:58:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230170AbiJRD6d (ORCPT ); Mon, 17 Oct 2022 23:58:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230112AbiJRD6Y (ORCPT ); Mon, 17 Oct 2022 23:58:24 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1DCD87FBE for ; Mon, 17 Oct 2022 20:57:51 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id h2so5299665plb.2 for ; Mon, 17 Oct 2022 20:57:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9p3m7T6e0mIj8rcCXtywVHD8sGWIzKCyjF4TP7KLyZQ=; b=F4EZTL9tVgb/GVZL3Pq3dG+YSUlqemGjgd1HKl8uW7Zv3ivDiffA8tbC7/7dWruKax 2LCuvRHAppGUX8X6oBUrN2c9Rq3xqt9/4nqMIWNlL+g8QUFp5AYvLHJji2VTBRoAUEDs 1E5N2J25qZgWy/Rxdk6krea1cWV1M/bcTxVsw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9p3m7T6e0mIj8rcCXtywVHD8sGWIzKCyjF4TP7KLyZQ=; b=2XhVWquw7enCcjsKLqJ6a7pnuOGL5bx05ymQjLW8HCspS27cWeJvawu62rfZ7UGIgE ixUW1VGILe/wcVnTJkfetPeFb+GKYtfY47Zu07WhtlOKmN0+3JxXnFKiAXNemF6GiXcf 8SfEqBLpVUEbhqcCYphkUVQB65BTIpdMQ2eL2JrkeLj5v0GzVlSZjBVN/QW+Y8uVuCIV OlCBcHp8y48QnRzWkboHCdHSG2aNlku+a6LyfPS1V3S1IlnIEcZeZpc5e32KXqA6Q5eb ZAui0m4q6Sx4vZKvlHZJbBy3nVFaAad8hilcK6VJLQB2BEno8xzHR49pKuSguKMHlmVT AN0w== X-Gm-Message-State: ACrzQf1KVFqvPAez18XhtjEyGuge8Y8E/80aO7waZ8LvOgtx6kZRHD82 Z5u82dBb8IXg12FdOv7p+L7tgQ== X-Google-Smtp-Source: AMsMyM4Oi5SI4xxHrO4wJahkDYqAgw2comRgFo0posUVaiivWN51Whl+zPIHJrd+P7q1UiVjJiRzBg== X-Received: by 2002:a17:90b:384f:b0:20d:4761:3394 with SMTP id nl15-20020a17090b384f00b0020d47613394mr1319039pjb.144.1666065470226; Mon, 17 Oct 2022 20:57:50 -0700 (PDT) Received: from localhost ([2620:15c:9d:2:2ac3:f4e2:e908:c393]) by smtp.gmail.com with UTF8SMTPSA id q23-20020a635c17000000b0043a0de69c94sm6805583pgb.14.2022.10.17.20.57.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 20:57:49 -0700 (PDT) From: Brian Norris To: Ulf Hansson Cc: Shawn Lin , Adrian Hunter , Shawn Guo , Fabio Estevam , Faiz Abbas , NXP Linux Team , Haibo Chen , Al Cooper , linux-mmc@vger.kernel.org, Pengutronix Kernel Team , linux-kernel@vger.kernel.org, Florian Fainelli , Sascha Hauer , Thierry Reding , Michal Simek , Jonathan Hunter , Sowjanya Komatineni , linux-arm-kernel@lists.infradead.org, Broadcom internal kernel review list , Brian Norris Subject: [PATCH 5/5] mmc: sdhci_am654: Fix SDHCI_RESET_ALL for CQHCI Date: Mon, 17 Oct 2022 20:57:24 -0700 Message-Id: <20221017205610.5.I35ca9d6220ba48304438b992a76647ca8e5b126f@changeid> X-Mailer: git-send-email 2.38.0.413.g74048e4d9e-goog In-Reply-To: <20221018035724.2061127-1-briannorris@chromium.org> References: <20221018035724.2061127-1-briannorris@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" [[ NOTE: this is completely untested by the author, but included solely because, as noted in commit df57d73276b8 ("mmc: sdhci-pci: Fix SDHCI_RESET_ALL for CQHCI for Intel GLK-based controllers"), "other drivers using CQHCI might benefit from a similar change, if they also have CQHCI reset by SDHCI_RESET_ALL." We've now seen the same bug on at least MSM, Arasan, and Intel hardware. ]] SDHCI_RESET_ALL resets will reset the hardware CQE state, but we aren't tracking that properly in software. When out of sync, we may trigger various timeouts. It's not typical to perform resets while CQE is enabled, but this may occur in some suspend or error recovery scenarios. Fixes: f545702b74f9 ("mmc: sdhci_am654: Add Support for Command Queuing Eng= ine to J721E") Signed-off-by: Brian Norris --- drivers/mmc/host/sdhci_am654.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 8f1023480e12..187a21086791 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -378,6 +378,9 @@ static void sdhci_am654_reset(struct sdhci_host *host, = u8 mask) struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 =3D sdhci_pltfm_priv(pltfm_host); =20 + if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL)) + cqhci_deactivate(host->mmc); + sdhci_reset(host, mask); =20 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { --=20 2.38.0.413.g74048e4d9e-goog