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Wed, 5 Apr 2023 08:25:23 -0400 (EDT) From: Maxime Ripard Date: Tue, 04 Apr 2023 12:11:54 +0200 Subject: [PATCH v3 64/65] ASoC: tlv320aic32x4: div: Switch to determine_rate MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221018-clk-range-checks-fixes-v3-64-9a1358472d52@cerno.tech> References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> In-Reply-To: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech> To: Michael Turquette , Stephen Boyd , =?utf-8?q?Andreas_F=C3=A4rber?= , Manivannan Sadhasivam , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , Max Filippov , Charles Keepax , Richard Fitzgerald , Maxime Coquelin , Alexandre Torgue , Luca Ceresoli , David Lechner , Sekhar Nori , Abel Vesa , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Matthias Brugger , Geert Uytterhoeven , Dinh Nguyen , Peter De Schrijver , Prashant Gaikwad , Thierry Reding , Jonathan Hunter , Ulf Hansson , Linus Walleij , David Airlie , Daniel Vetter , Vinod Koul , Kishon Vijay Abraham I , Alessandro Zummo , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Paul Cercueil , Orson Zhai , Baolin Wang , Chunyan Zhang Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, AngeloGioacchino Del Regno , linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org, patches@opensource.cirrus.com, linux-stm32@st-md-mailman.stormreply.com, linux-mediatek@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-rtc@vger.kernel.org, linux-sunxi@lists.linux.dev, alsa-devel@alsa-project.org, linux-mips@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3125; i=maxime@cerno.tech; h=from:subject:message-id; bh=u+laB/ZyqIG2Q9t0bl1LRyl8JfC/hVk4k6X79EShIfo=; b=owGbwMvMwCX2+D1vfrpE4FHG02pJDCna37f7VDMJ1/zq+H9YZOaDPb8uX7xlnZ3244rZ4U+ftVhN Tyw62VHKwiDGxSArpsgSI2y+JO7UrNedbHzzYOawMoEMYeDiFICJKNozMvQnqvMuEpJyusvU3xvjkz R50wTex4VRV3Z+Vo7+Menh5N+MDNPPFBpsvskt+eIo92PeOgWtzV+Fl8/lKtSNj75ygfOjLQcA X-Developer-Key: i=maxime@cerno.tech; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The tlv320aic32x4 divider clocks implements a mux with a set_parent hook, but doesn't provide a determine_rate implementation. This is a bit odd, since set_parent() is there to, as its name implies, change the parent of a clock. However, the most likely candidate to trigger that parent change is a call to clk_set_rate(), with determine_rate() figuring out which parent is the best suited for a given rate. The other trigger would be a call to clk_set_parent(), but it's far less used, and it doesn't look like there's any obvious user for that clock. So, the set_parent hook is effectively unused, possibly because of an oversight. However, it could also be an explicit decision by the original author to avoid any reparenting but through an explicit call to clk_set_parent(). The driver does implement round_rate() though, which means that we can change the rate of the clock, but we will never get to change the parent. However, It's hard to tell whether it's been done on purpose or not. Since we'll start mandating a determine_rate() implementation, let's convert the round_rate() implementation to a determine_rate(), which will also make the current behavior explicit. And if it was an oversight, the clock behaviour can be adjusted later on. Signed-off-by: Maxime Ripard --- sound/soc/codecs/tlv320aic32x4-clk.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/sound/soc/codecs/tlv320aic32x4-clk.c b/sound/soc/codecs/tlv320= aic32x4-clk.c index d8b8ea3eaa12..707c9951fac0 100644 --- a/sound/soc/codecs/tlv320aic32x4-clk.c +++ b/sound/soc/codecs/tlv320aic32x4-clk.c @@ -333,16 +333,17 @@ static int clk_aic32x4_div_set_rate(struct clk_hw *hw= , unsigned long rate, AIC32X4_DIV_MASK, divisor); } =20 -static long clk_aic32x4_div_round_rate(struct clk_hw *hw, unsigned long ra= te, - unsigned long *parent_rate) +static int clk_aic32x4_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { unsigned long divisor; =20 - divisor =3D DIV_ROUND_UP(*parent_rate, rate); + divisor =3D DIV_ROUND_UP(req->best_parent_rate, req->rate); if (divisor > 128) return -EINVAL; =20 - return DIV_ROUND_UP(*parent_rate, divisor); + req->rate =3D DIV_ROUND_UP(req->best_parent_rate, divisor); + return 0; } =20 static unsigned long clk_aic32x4_div_recalc_rate(struct clk_hw *hw, @@ -361,7 +362,7 @@ static const struct clk_ops aic32x4_div_ops =3D { .prepare =3D clk_aic32x4_div_prepare, .unprepare =3D clk_aic32x4_div_unprepare, .set_rate =3D clk_aic32x4_div_set_rate, - .round_rate =3D clk_aic32x4_div_round_rate, + .determine_rate =3D clk_aic32x4_div_determine_rate, .recalc_rate =3D clk_aic32x4_div_recalc_rate, }; =20 @@ -389,7 +390,7 @@ static const struct clk_ops aic32x4_bdiv_ops =3D { .set_parent =3D clk_aic32x4_bdiv_set_parent, .get_parent =3D clk_aic32x4_bdiv_get_parent, .set_rate =3D clk_aic32x4_div_set_rate, - .round_rate =3D clk_aic32x4_div_round_rate, + .determine_rate =3D clk_aic32x4_div_determine_rate, .recalc_rate =3D clk_aic32x4_div_recalc_rate, }; =20 --=20 2.39.2