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(fttx-pool-217.61.154.127.bambit.de [217.61.154.127]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id 555A34053E; Mon, 17 Oct 2022 10:41:58 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sam Shih , Jieyy Yang Subject: [RFC v1 07/12] arm64: dts: mt7986: add pcie related device nodes Date: Mon, 17 Oct 2022 12:41:36 +0200 Message-Id: <20221017104141.7338-8-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221017104141.7338-1-linux@fw-web.de> References: <20221017104141.7338-1-linux@fw-web.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: 799015bb-29c8-452b-8665-6b48831f56ce Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sam Shih This patch adds PCIe support for MT7986. Signed-off-by: Jieyy Yang Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich --- changes compared to sams original version: - add clock-names to pcie node driver does bulk handling without names, but binding requires 6 clocks and not only 5 we have --- arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 17 ++++++ arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 54 ++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot= /dts/mediatek/mt7986a-rfb.dts index 58f7e6b169bf..c08ca4746014 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -54,7 +54,24 @@ switch: switch@0 { }; }; =20 +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins>; + status =3D "okay"; +}; + +&pcie_phy { + status =3D "okay"; +}; + &pio { + pcie_pins: pcie-pins { + mux { + function =3D "pcie"; + groups =3D "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + spi_flash_pins: spi-flash-pins { mux { function =3D "spi"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dt= s/mediatek/mt7986a.dtsi index e77e8deec4b0..007c1e25a639 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include =20 / { interrupt-parent =3D <&gic>; @@ -246,6 +247,59 @@ uart2: serial@11004000 { status =3D "disabled"; }; =20 + pcie: pcie@11280000 { + compatible =3D "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x00 0x11280000 0x00 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x82000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x10000000>; + clocks =3D <&infracfg CLK_INFRA_PCIE_SEL>, + <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m"; + status =3D "disabled"; + + phys =3D <&pcie_port PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + pcie_phy: t-phy@11c00000 { + compatible =3D "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + status =3D "disabled"; + + pcie_port: pcie-phy@11c00000 { + reg =3D <0 0x11c00000 0 0x20000>; + clocks =3D <&clk40m>; + clock-names =3D "ref"; + #phy-cells =3D <1>; + }; + }; + ethsys: syscon@15000000 { #address-cells =3D <1>; #size-cells =3D <1>; --=20 2.34.1