From nobody Tue Apr 7 14:23:42 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B55A2C433FE for ; Mon, 17 Oct 2022 08:33:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230244AbiJQIc7 (ORCPT ); Mon, 17 Oct 2022 04:32:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230061AbiJQIcn (ORCPT ); Mon, 17 Oct 2022 04:32:43 -0400 Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A0F73FEC9 for ; Mon, 17 Oct 2022 01:32:41 -0700 (PDT) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4MrVc23jfWzHvRq; Mon, 17 Oct 2022 16:32:34 +0800 (CST) Received: from huawei.com (10.44.134.232) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 16:32:07 +0800 From: Yunfeng Ye To: , , , , , CC: Subject: [PATCH 2/5] arm64: mm: Extract the processing of asid_generation Date: Mon, 17 Oct 2022 16:32:00 +0800 Message-ID: <20221017083203.3690346-3-yeyunfeng@huawei.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221017083203.3690346-1-yeyunfeng@huawei.com> References: <20221017083203.3690346-1-yeyunfeng@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.44.134.232] X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" To prepare for supporting ASID isolation feature, extract the processing of asid_generation. it is convenient to modify the asid_generation centrally. By the way, It is clearer to put flush_generation() into flush_context(). Signed-off-by: Yunfeng Ye --- arch/arm64/mm/context.c | 39 ++++++++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 8549b5f30352..380c7b05c36b 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -102,14 +102,40 @@ static void set_reserved_asid_bits(void) bitmap_clear(asid_map, 0, NUM_USER_ASIDS); } =20 -#define asid_gen_match(asid) \ - (!(((asid) ^ atomic64_read(&asid_generation)) >> asid_bits)) +static void asid_generation_init(void) +{ + atomic64_set(&asid_generation, ASID_FIRST_VERSION); +} + +static void flush_generation(void) +{ + /* We're out of ASIDs, so increment the global generation count */ + atomic64_add_return_relaxed(ASID_FIRST_VERSION, + &asid_generation); +} + +static inline u64 asid_read_generation(void) +{ + return atomic64_read(&asid_generation); +} + +static inline bool asid_match(u64 asid, u64 genid) +{ + return (!(((asid) ^ (genid)) >> asid_bits)); +} + +static inline bool asid_gen_match(u64 asid) +{ + return asid_match(asid, asid_read_generation()); +} =20 static void flush_context(void) { int i; u64 asid; =20 + flush_generation(); + /* Update the list of reserved ASIDs and the ASID bitmap. */ set_reserved_asid_bits(); =20 @@ -163,7 +189,7 @@ static u64 new_context(struct mm_struct *mm) { static u32 cur_idx =3D 1; u64 asid =3D atomic64_read(&mm->context.id); - u64 generation =3D atomic64_read(&asid_generation); + u64 generation =3D asid_read_generation(); =20 if (asid !=3D 0) { u64 newasid =3D asid2ctxid(ctxid2asid(asid), generation); @@ -202,14 +228,12 @@ static u64 new_context(struct mm_struct *mm) if (asid !=3D NUM_USER_ASIDS) goto set_asid; =20 - /* We're out of ASIDs, so increment the global generation count */ - generation =3D atomic64_add_return_relaxed(ASID_FIRST_VERSION, - &asid_generation); flush_context(); =20 /* We have more ASIDs than CPUs, so this will always succeed */ asid =3D find_next_zero_bit(asid_map, NUM_USER_ASIDS, 1); =20 + generation =3D asid_read_generation(); set_asid: __set_bit(asid, asid_map); cur_idx =3D asid; @@ -405,7 +429,8 @@ arch_initcall(asids_update_limit); static int asids_init(void) { asid_bits =3D get_cpu_asid_bits(); - atomic64_set(&asid_generation, ASID_FIRST_VERSION); + asid_generation_init(); + asid_map =3D bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); if (!asid_map) panic("Failed to allocate bitmap for %lu ASIDs\n", --=20 2.27.0