From nobody Tue Apr 7 14:09:08 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 566D4C433FE for ; Mon, 17 Oct 2022 08:13:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230216AbiJQINu (ORCPT ); Mon, 17 Oct 2022 04:13:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230168AbiJQINj (ORCPT ); Mon, 17 Oct 2022 04:13:39 -0400 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B4A3A5C377 for ; Mon, 17 Oct 2022 01:13:36 -0700 (PDT) Received: from dggpeml500024.china.huawei.com (unknown [172.30.72.56]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4MrV4h352tz1P7Zm; Mon, 17 Oct 2022 16:08:52 +0800 (CST) Received: from huawei.com (10.44.134.232) by dggpeml500024.china.huawei.com (7.185.36.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 17 Oct 2022 16:13:03 +0800 From: y00318929 To: , , , , , Subject: [PATCH 3/5] arm64: mm: Use cpumask in flush_context() Date: Mon, 17 Oct 2022 16:12:56 +0800 Message-ID: <20221017081258.3678830-4-yeyunfeng@huawei.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20221017081258.3678830-1-yeyunfeng@huawei.com> References: <20221017081258.3678830-1-yeyunfeng@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.44.134.232] X-ClientProxiedBy: dggems701-chm.china.huawei.com (10.3.19.178) To dggpeml500024.china.huawei.com (7.185.36.10) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Yunfeng Ye Currently, all CPUs are selected to flush TLB in flush_context(). In order to prepare for flushing only part of the CPUs TLB, we use asid_housekeeping_mask and use cpumask_or() instead of cpumask_setall(). Signed-off-by: Yunfeng Ye --- arch/arm64/mm/context.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c index 380c7b05c36b..e402997aa1c2 100644 --- a/arch/arm64/mm/context.c +++ b/arch/arm64/mm/context.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include #include @@ -32,6 +33,7 @@ static unsigned long *asid_map; static DEFINE_PER_CPU(atomic64_t, active_asids); static DEFINE_PER_CPU(u64, reserved_asids); static cpumask_t tlb_flush_pending; +static const struct cpumask *asid_housekeeping_mask; =20 static struct asid_bitmap pinned_asid; =20 @@ -129,17 +131,23 @@ static inline bool asid_gen_match(u64 asid) return asid_match(asid, asid_read_generation()); } =20 +static const struct cpumask *flush_cpumask(void) +{ + return asid_housekeeping_mask; +} + static void flush_context(void) { int i; u64 asid; + const struct cpumask *cpumask =3D flush_cpumask(); =20 flush_generation(); =20 /* Update the list of reserved ASIDs and the ASID bitmap. */ set_reserved_asid_bits(); =20 - for_each_possible_cpu(i) { + for_each_cpu(i, cpumask) { asid =3D atomic64_xchg_relaxed(&per_cpu(active_asids, i), 0); /* * If this CPU has already been through a @@ -158,7 +166,7 @@ static void flush_context(void) * Queue a TLB invalidation for each CPU to perform on next * context-switch */ - cpumask_setall(&tlb_flush_pending); + cpumask_or(&tlb_flush_pending, &tlb_flush_pending, cpumask); } =20 static bool check_update_reserved_asid(u64 asid, u64 newasid) @@ -439,6 +447,8 @@ static int asids_init(void) pinned_asid.map =3D bitmap_zalloc(NUM_USER_ASIDS, GFP_KERNEL); pinned_asid.nr =3D 0; =20 + asid_housekeeping_mask =3D cpu_possible_mask; + /* * We cannot call set_reserved_asid_bits() here because CPU * caps are not finalized yet, so it is safer to assume KPTI --=20 2.27.0