From nobody Sat Sep 21 11:52:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B2A7C433FE for ; Mon, 17 Oct 2022 07:09:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230200AbiJQHJa (ORCPT ); Mon, 17 Oct 2022 03:09:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230153AbiJQHJN (ORCPT ); Mon, 17 Oct 2022 03:09:13 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9955257E1F; Mon, 17 Oct 2022 00:09:08 -0700 (PDT) X-UUID: 3389be396c8b4e0eb4bb273337964771-20221017 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=D2S3DQgWXod379+3uCrDiDKGjcHd4CLUQw64HdfRMJ8=; b=g0LCPdX+G3mJQrSAv5fLm3CmiM+Q3zN+UIBdkEa0PNO7WMaYq9PLENxE4fxu+OSX8PMXuqZUV2vEP++ERv2gxMQwlSwZgjNhTcERVf86BRvVKNPML/grF3/W/9vFxmNtTHGg7oTZszcI9MdBIMkb0kCGpg2nedoplAuRXDRpnXo=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:b0d37d92-0f87-4b25-a3b1-d8a139d86fc8,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:a52393db-0379-47b3-a5dd-2ef5001d380a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 3389be396c8b4e0eb4bb273337964771-20221017 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1120094907; Mon, 17 Oct 2022 15:09:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 17 Oct 2022 15:09:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 17 Oct 2022 15:09:00 +0800 From: Tinghan Shen To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , TingHan Shen Subject: [PATCH v1 1/3] dt-bindings: PCI: mediatek-gen3: Add iommu and power-domain support Date: Mon, 17 Oct 2022 15:08:56 +0800 Message-ID: <20221017070858.13902-2-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221017070858.13902-1-tinghan.shen@mediatek.com> References: <20221017070858.13902-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jianjun Wang Add iommu and power-domain support, and add examples for MT8195, which has two PCIe ports with different clocks and phys. Signed-off-by: Jianjun Wang Signed-off-by: TingHan Shen --- .../bindings/pci/mediatek-pcie-gen3.yaml | 115 ++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml = b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index c00be39af64e..089074b5fa95 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -70,6 +70,12 @@ properties: minItems: 1 maxItems: 8 =20 + iommu-map: + maxItems: 1 + + iommu-map-mask: + maxItems: 1 + resets: minItems: 1 maxItems: 2 @@ -107,6 +113,9 @@ properties: items: - const: pcie-phy =20 + power-domains: + maxItems: 1 + '#interrupt-cells': const: 1 =20 @@ -191,3 +200,109 @@ examples: }; }; }; + + - | + #include + #include + #include + #include + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie0: pcie@112f0000 { + compatible =3D "mediatek,mt8195-pcie", "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x00 0x112f0000 0x00 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x200000>, + <0x82000000 0x00 0x20200000 0x00 + 0x20200000 0x00 0x3e00000>; + + iommu-map =3D <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; + iommu-map-mask =3D <0x0>; + + clocks =3D <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks =3D <&topckgen CLK_TOP_TL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy"; + + power-domains =3D <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + pcie_intc0: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@112f8000 { + compatible =3D "mediatek,mt8195-pcie", "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0x00 0x112f8000 0x00 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0x00 0x24000000 0x00 + 0x24000000 0x00 0x200000>, + <0x82000000 0x00 0x24200000 0x00 + 0x24200000 0x00 0x3e00000>; + + iommu-map =3D <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; + iommu-map-mask =3D <0x0>; + + clocks =3D <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + /* Designer has connect pcie1 with peri_mem_p0 clock = */ + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks =3D <&topckgen CLK_TOP_TL_P1>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys =3D <&u3port1 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + + power-domains =3D <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + pcie_intc1: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; --=20 2.18.0 From nobody Sat Sep 21 11:52:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A4A7C4332F for ; Mon, 17 Oct 2022 07:09:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230179AbiJQHJZ (ORCPT ); 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Mon, 17 Oct 2022 15:09:02 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Mon, 17 Oct 2022 15:09:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 17 Oct 2022 15:09:00 +0800 From: Tinghan Shen To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Tinghan Shen Subject: [PATCH v1 2/3] arm64: dts: mt8195: Add pcie and pcie phy nodes Date: Mon, 17 Oct 2022 15:08:57 +0800 Message-ID: <20221017070858.13902-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221017070858.13902-1-tinghan.shen@mediatek.com> References: <20221017070858.13902-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pcie and pcie phy nodes for mt8195. Signed-off-by: Jianjun Wang Signed-off-by: Tinghan Shen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 143 +++++++++++++++++++++++ 1 file changed, 143 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index d03f0c2b8233..903e92d6156f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1182,6 +1182,104 @@ status =3D "disabled"; }; =20 + pcie0: pcie@112f0000 { + compatible =3D "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0 0x112f0000 0 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x20000000 + 0x0 0x20000000 0 0x200000>, + <0x82000000 0 0x20200000 + 0x0 0x20200000 0 0x3e00000>; + + iommu-map =3D <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; + iommu-map-mask =3D <0x0>; + + clocks =3D <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks =3D <&topckgen CLK_TOP_TL>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy"; + + power-domains =3D <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + status =3D "disabled"; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + + pcie1: pcie@112f8000 { + compatible =3D "mediatek,mt8195-pcie", + "mediatek,mt8192-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + reg =3D <0 0x112f8000 0 0x4000>; + reg-names =3D "pcie-mac"; + interrupts =3D ; + bus-range =3D <0x00 0xff>; + ranges =3D <0x81000000 0 0x24000000 + 0x0 0x24000000 0 0x200000>, + <0x82000000 0 0x24200000 + 0x0 0x24200000 0 0x3e00000>; + + iommu-map =3D <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; + iommu-map-mask =3D <0x0>; + + clocks =3D <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, + <&clk26m>, + <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, + /* Designer has connect pcie1 with peri_mem_p0 clock */ + <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; + clock-names =3D "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "peri_mem"; + assigned-clocks =3D <&topckgen CLK_TOP_TL_P1>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D4_D4>; + + phys =3D <&u3port1 PHY_TYPE_PCIE>; + phy-names =3D "pcie-phy"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie_intc1 0>, + <0 0 0 2 &pcie_intc1 1>, + <0 0 0 3 &pcie_intc1 2>, + <0 0 0 4 &pcie_intc1 3>; + status =3D "disabled"; + + pcie_intc1: interrupt-controller { + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; + }; + nor_flash: spi@1132c000 { compatible =3D "mediatek,mt8195-nor", "mediatek,mt8173-nor"; @@ -1241,6 +1339,34 @@ reg =3D <0x189 0x2>; bits =3D <7 5>; }; + pciephy_rx_ln1: pciephy-rx-ln1@190 { + reg =3D <0x190 0x1>; + bits =3D <0 4>; + }; + pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190 { + reg =3D <0x190 0x1>; + bits =3D <4 4>; + }; + pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191 { + reg =3D <0x191 0x1>; + bits =3D <0 4>; + }; + pciephy_rx_ln0: pciephy-rx-ln0@191 { + reg =3D <0x191 0x1>; + bits =3D <4 4>; + }; + pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192 { + reg =3D <0x192 0x1>; + bits =3D <0 4>; + }; + pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192 { + reg =3D <0x192 0x1>; + bits =3D <4 4>; + }; + pciephy_glb_intr: pciephy-glb-intr@193 { + reg =3D <0x193 0x1>; + bits =3D <0 4>; + }; }; =20 u3phy2: t-phy@11c40000 { @@ -1461,6 +1587,23 @@ }; }; =20 + pciephy: phy@11e80000 { + compatible =3D "mediatek,mt8195-pcie-phy"; + reg =3D <0 0x11e80000 0 0x10000>; + reg-names =3D "sif"; + nvmem-cells =3D <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, + <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, + <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, + <&pciephy_rx_ln1>; + nvmem-cell-names =3D "glb_intr", "tx_ln0_pmos", + "tx_ln0_nmos", "rx_ln0", + "tx_ln1_pmos", "tx_ln1_nmos", + "rx_ln1"; + power-domains =3D <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; + #phy-cells =3D <0>; + status =3D "disabled"; + }; + ufsphy: ufs-phy@11fa0000 { compatible =3D "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; reg =3D <0 0x11fa0000 0 0xc000>; --=20 2.18.0 From nobody Sat Sep 21 11:52:31 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66AAEC4332F for ; Mon, 17 Oct 2022 07:09:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230183AbiJQHJU (ORCPT ); Mon, 17 Oct 2022 03:09:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230123AbiJQHJM (ORCPT ); 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Mon, 17 Oct 2022 15:09:01 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.194) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 17 Oct 2022 15:09:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Mon, 17 Oct 2022 15:09:00 +0800 From: Tinghan Shen To: Ryder Lee , Jianjun Wang , Bjorn Helgaas , Rob Herring , Krzysztof Kozlowski , Matthias Brugger CC: , , , , , , Tinghan Shen , Irui Wang Subject: [PATCH v1 3/3] arm64: dts: mt8195: Add venc node Date: Mon, 17 Oct 2022 15:08:58 +0800 Message-ID: <20221017070858.13902-4-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221017070858.13902-1-tinghan.shen@mediatek.com> References: <20221017070858.13902-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add venc node for mt8195 SoC. Signed-off-by: Irui Wang Signed-off-by: Tinghan Shen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 903e92d6156f..7cf2f7ef4ec6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2163,6 +2163,30 @@ power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC>; }; =20 + venc: venc@1a020000 { + compatible =3D "mediatek,mt8195-vcodec-enc"; + reg =3D <0 0x1a020000 0 0x10000>; + iommus =3D <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, + <&iommu_vdo M4U_PORT_L19_VENC_REC>, + <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, + <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, + <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; + interrupts =3D ; + mediatek,scp =3D <&scp>; + clocks =3D <&vencsys CLK_VENC_VENC>; + clock-names =3D "venc_sel"; + assigned-clocks =3D <&topckgen CLK_TOP_VENC>; + assigned-clock-parents =3D <&topckgen CLK_TOP_UNIVPLL_D4>; + power-domains =3D <&spm MT8195_POWER_DOMAIN_VENC>; + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + }; + vencsys_core1: clock-controller@1b000000 { compatible =3D "mediatek,mt8195-vencsys_core1"; reg =3D <0 0x1b000000 0 0x1000>; --=20 2.18.0