From nobody Tue Apr 7 14:26:56 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5DE1C4332F for ; Mon, 17 Oct 2022 03:41:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232562AbiJQDlt (ORCPT ); Sun, 16 Oct 2022 23:41:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232559AbiJQDlo (ORCPT ); Sun, 16 Oct 2022 23:41:44 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8290E50051 for ; Sun, 16 Oct 2022 20:41:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 40EE5B80D4B for ; Mon, 17 Oct 2022 03:41:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B7CEC433D7; Mon, 17 Oct 2022 03:41:39 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 1/4] irqchip/loongson-htvec: Add suspend/resume support Date: Mon, 17 Oct 2022 11:39:01 +0800 Message-Id: <20221017033904.2421723-2-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017033904.2421723-1-chenhuacai@loongson.cn> References: <20221017033904.2421723-1-chenhuacai@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add suspend/resume support for HTVEC irqchip, which is needed for upcoming suspend/hibernation. Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-htvec.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loo= ngson-htvec.c index 1bb414ec6e78..cd4f1a0a1ea8 100644 --- a/drivers/irqchip/irq-loongson-htvec.c +++ b/drivers/irqchip/irq-loongson-htvec.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 /* Registers */ #define HTVEC_EN_OFF 0x20 @@ -29,6 +30,7 @@ struct htvec { void __iomem *base; struct irq_domain *htvec_domain; raw_spinlock_t htvec_lock; + u32 saved_vec_en[HTVEC_MAX_PARENT_IRQ]; }; =20 static struct htvec *htvec_priv; @@ -156,6 +158,29 @@ static void htvec_reset(struct htvec *priv) } } =20 +static int htvec_suspend(void) +{ + int i; + + for (i =3D 0; i < htvec_priv->num_parents; i++) + htvec_priv->saved_vec_en[i] =3D readl(htvec_priv->base + HTVEC_EN_OFF + = 4 * i); + + return 0; +} + +static void htvec_resume(void) +{ + int i; + + for (i =3D 0; i < htvec_priv->num_parents; i++) + writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 = * i); +} + +static struct syscore_ops htvec_syscore_ops =3D { + .suspend =3D htvec_suspend, + .resume =3D htvec_resume, +}; + static int htvec_init(phys_addr_t addr, unsigned long size, int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) { @@ -188,6 +213,8 @@ static int htvec_init(phys_addr_t addr, unsigned long s= ize, =20 htvec_priv =3D priv; =20 + register_syscore_ops(&htvec_syscore_ops); + return 0; =20 iounmap_base: --=20 2.31.1