From nobody Tue Apr 7 12:57:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5DE1C4332F for ; Mon, 17 Oct 2022 03:41:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232562AbiJQDlt (ORCPT ); Sun, 16 Oct 2022 23:41:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232559AbiJQDlo (ORCPT ); Sun, 16 Oct 2022 23:41:44 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8290E50051 for ; Sun, 16 Oct 2022 20:41:43 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 40EE5B80D4B for ; Mon, 17 Oct 2022 03:41:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3B7CEC433D7; Mon, 17 Oct 2022 03:41:39 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 1/4] irqchip/loongson-htvec: Add suspend/resume support Date: Mon, 17 Oct 2022 11:39:01 +0800 Message-Id: <20221017033904.2421723-2-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017033904.2421723-1-chenhuacai@loongson.cn> References: <20221017033904.2421723-1-chenhuacai@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add suspend/resume support for HTVEC irqchip, which is needed for upcoming suspend/hibernation. Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-htvec.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/irqchip/irq-loongson-htvec.c b/drivers/irqchip/irq-loo= ngson-htvec.c index 1bb414ec6e78..cd4f1a0a1ea8 100644 --- a/drivers/irqchip/irq-loongson-htvec.c +++ b/drivers/irqchip/irq-loongson-htvec.c @@ -16,6 +16,7 @@ #include #include #include +#include =20 /* Registers */ #define HTVEC_EN_OFF 0x20 @@ -29,6 +30,7 @@ struct htvec { void __iomem *base; struct irq_domain *htvec_domain; raw_spinlock_t htvec_lock; + u32 saved_vec_en[HTVEC_MAX_PARENT_IRQ]; }; =20 static struct htvec *htvec_priv; @@ -156,6 +158,29 @@ static void htvec_reset(struct htvec *priv) } } =20 +static int htvec_suspend(void) +{ + int i; + + for (i =3D 0; i < htvec_priv->num_parents; i++) + htvec_priv->saved_vec_en[i] =3D readl(htvec_priv->base + HTVEC_EN_OFF + = 4 * i); + + return 0; +} + +static void htvec_resume(void) +{ + int i; + + for (i =3D 0; i < htvec_priv->num_parents; i++) + writel(htvec_priv->saved_vec_en[i], htvec_priv->base + HTVEC_EN_OFF + 4 = * i); +} + +static struct syscore_ops htvec_syscore_ops =3D { + .suspend =3D htvec_suspend, + .resume =3D htvec_resume, +}; + static int htvec_init(phys_addr_t addr, unsigned long size, int num_parents, int parent_irq[], struct fwnode_handle *domain_handle) { @@ -188,6 +213,8 @@ static int htvec_init(phys_addr_t addr, unsigned long s= ize, =20 htvec_priv =3D priv; =20 + register_syscore_ops(&htvec_syscore_ops); + return 0; =20 iounmap_base: --=20 2.31.1 From nobody Tue Apr 7 12:57:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3768AC433FE for ; Mon, 17 Oct 2022 03:42:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232597AbiJQDm3 (ORCPT ); Sun, 16 Oct 2022 23:42:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232590AbiJQDm0 (ORCPT ); Sun, 16 Oct 2022 23:42:26 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF86C50072 for ; Sun, 16 Oct 2022 20:42:25 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4C7E460F1A for ; Mon, 17 Oct 2022 03:42:25 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DEBB6C433C1; Mon, 17 Oct 2022 03:42:22 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 2/4] irqchip/loongson-eiointc: Add suspend/resume support Date: Mon, 17 Oct 2022 11:39:02 +0800 Message-Id: <20221017033904.2421723-3-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017033904.2421723-1-chenhuacai@loongson.cn> References: <20221017033904.2421723-1-chenhuacai@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add suspend/resume support for EIOINTC irqchip, which is needed for upcoming suspend/hibernation. Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-eiointc.c | 31 ++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-l= oongson-eiointc.c index 16e9af8d8b1e..c68f8de3ae09 100644 --- a/drivers/irqchip/irq-loongson-eiointc.c +++ b/drivers/irqchip/irq-loongson-eiointc.c @@ -17,6 +17,7 @@ #include #include #include +#include =20 #define EIOINTC_REG_NODEMAP 0x14a0 #define EIOINTC_REG_IPMAP 0x14c0 @@ -301,6 +302,35 @@ static struct irq_domain *acpi_get_vec_parent(int node= , struct acpi_vector_group return NULL; } =20 +static int eiointc_suspend(void) +{ + return 0; +} + +static void eiointc_resume(void) +{ + int i, j; + struct irq_desc *desc; + struct irq_data *irq_data; + + eiointc_router_init(0); + + for (i =3D 0; i < nr_pics; i++) { + for (j =3D 0; j < VEC_COUNT; j++) { + desc =3D irq_resolve_mapping(eiointc_priv[i]->eiointc_domain, j); + if (desc && desc->handle_irq && desc->handle_irq !=3D handle_bad_irq) { + irq_data =3D &desc->irq_data; + eiointc_set_irq_affinity(irq_data, irq_data->common->affinity, 0); + } + } + } +} + +static struct syscore_ops eiointc_syscore_ops =3D { + .suspend =3D eiointc_suspend, + .resume =3D eiointc_resume, +}; + static int __init pch_pic_parse_madt(union acpi_subtable_headers *header, const unsigned long end) @@ -380,6 +410,7 @@ int __init eiointc_acpi_init(struct irq_domain *parent, parent_irq =3D irq_create_mapping(parent, acpi_eiointc->cascade); irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv); =20 + register_syscore_ops(&eiointc_syscore_ops); cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING, "irqchip/loongarch/intc:starting", eiointc_router_init, NULL); --=20 2.31.1 From nobody Tue Apr 7 12:57:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC4F3C4332F for ; Mon, 17 Oct 2022 03:43:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232622AbiJQDnM (ORCPT ); Sun, 16 Oct 2022 23:43:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232615AbiJQDnJ (ORCPT ); Sun, 16 Oct 2022 23:43:09 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7D5850197 for ; Sun, 16 Oct 2022 20:43:07 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 94066B80CC2 for ; Mon, 17 Oct 2022 03:43:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86C06C433C1; Mon, 17 Oct 2022 03:43:03 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 3/4] irqchip/loongson-pch-pic: Add suspend/resume support Date: Mon, 17 Oct 2022 11:39:03 +0800 Message-Id: <20221017033904.2421723-4-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017033904.2421723-1-chenhuacai@loongson.cn> References: <20221017033904.2421723-1-chenhuacai@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add suspend/resume support for PCH-PIC irqchip, which is needed for upcoming suspend/hibernation. Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-pch-pic.c | 47 ++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/irqchip/irq-loongson-pch-pic.c b/drivers/irqchip/irq-l= oongson-pch-pic.c index c01b9c257005..217513d74664 100644 --- a/drivers/irqchip/irq-loongson-pch-pic.c +++ b/drivers/irqchip/irq-loongson-pch-pic.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 /* Registers */ #define PCH_PIC_MASK 0x20 @@ -42,6 +43,9 @@ struct pch_pic { raw_spinlock_t pic_lock; u32 vec_count; u32 gsi_base; + u32 saved_vec_en[PIC_REG_COUNT]; + u32 saved_vec_pol[PIC_REG_COUNT]; + u32 saved_vec_edge[PIC_REG_COUNT]; }; =20 static struct pch_pic *pch_pic_priv[MAX_IO_PICS]; @@ -145,6 +149,7 @@ static struct irq_chip pch_pic_irq_chip =3D { .irq_ack =3D pch_pic_ack_irq, .irq_set_affinity =3D irq_chip_set_affinity_parent, .irq_set_type =3D pch_pic_set_type, + .flags =3D IRQCHIP_SKIP_SET_WAKE, }; =20 static int pch_pic_domain_translate(struct irq_domain *d, @@ -228,6 +233,46 @@ static void pch_pic_reset(struct pch_pic *priv) } } =20 +static int pch_pic_suspend(void) +{ + int i, j; + + for (i =3D 0; i < nr_pics; i++) { + for (j =3D 0; j < PIC_REG_COUNT; j++) { + pch_pic_priv[i]->saved_vec_pol[j] =3D + readl(pch_pic_priv[i]->base + PCH_PIC_POL + 4 * j); + pch_pic_priv[i]->saved_vec_edge[j] =3D + readl(pch_pic_priv[i]->base + PCH_PIC_EDGE + 4 * j); + pch_pic_priv[i]->saved_vec_en[j] =3D + readl(pch_pic_priv[i]->base + PCH_PIC_MASK + 4 * j); + } + } + + return 0; +} + +static void pch_pic_resume(void) +{ + int i, j; + + for (i =3D 0; i < nr_pics; i++) { + pch_pic_reset(pch_pic_priv[i]); + for (j =3D 0; j < PIC_REG_COUNT; j++) { + writel(pch_pic_priv[i]->saved_vec_pol[j], + pch_pic_priv[i]->base + PCH_PIC_POL + 4 * j); + writel(pch_pic_priv[i]->saved_vec_edge[j], + pch_pic_priv[i]->base + PCH_PIC_EDGE + 4 * j); + writel(pch_pic_priv[i]->saved_vec_en[j], + pch_pic_priv[i]->base + PCH_PIC_MASK + 4 * j); + } + } +} + +static struct syscore_ops pch_pic_syscore_ops =3D { + .suspend =3D pch_pic_suspend, + .resume =3D pch_pic_resume, +}; + static int pch_pic_init(phys_addr_t addr, unsigned long size, int vec_base, struct irq_domain *parent_domain, struct fwnode_handle *domain_handle, u32 gsi_base) @@ -260,6 +305,8 @@ static int pch_pic_init(phys_addr_t addr, unsigned long= size, int vec_base, pch_pic_handle[nr_pics] =3D domain_handle; pch_pic_priv[nr_pics++] =3D priv; =20 + register_syscore_ops(&pch_pic_syscore_ops); + return 0; =20 iounmap_base: --=20 2.31.1 From nobody Tue Apr 7 12:57:28 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CC5FC433FE for ; Mon, 17 Oct 2022 03:43:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232635AbiJQDny (ORCPT ); Sun, 16 Oct 2022 23:43:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48732 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232627AbiJQDnl (ORCPT ); Sun, 16 Oct 2022 23:43:41 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F8E95050F for ; Sun, 16 Oct 2022 20:43:40 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 45042B80CC2 for ; Mon, 17 Oct 2022 03:43:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 26BEAC433B5; Mon, 17 Oct 2022 03:43:35 +0000 (UTC) From: Huacai Chen To: Thomas Gleixner , Marc Zyngier Cc: linux-kernel@vger.kernel.org, Xuefeng Li , Huacai Chen , Jiaxun Yang , Huacai Chen Subject: [PATCH 4/4] irqchip/loongson-pch-lpc: Add suspend/resume support Date: Mon, 17 Oct 2022 11:39:04 +0800 Message-Id: <20221017033904.2421723-5-chenhuacai@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20221017033904.2421723-1-chenhuacai@loongson.cn> References: <20221017033904.2421723-1-chenhuacai@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add suspend/resume support for PCH-LPC irqchip, which is needed for upcoming suspend/hibernation. Signed-off-by: Huacai Chen --- drivers/irqchip/irq-loongson-pch-lpc.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/irqchip/irq-loongson-pch-lpc.c b/drivers/irqchip/irq-l= oongson-pch-lpc.c index bf2324910a75..9b35492fb6be 100644 --- a/drivers/irqchip/irq-loongson-pch-lpc.c +++ b/drivers/irqchip/irq-loongson-pch-lpc.c @@ -13,6 +13,7 @@ #include #include #include +#include =20 /* Registers */ #define LPC_INT_CTL 0x00 @@ -34,6 +35,7 @@ struct pch_lpc { u32 saved_reg_pol; }; =20 +static struct pch_lpc *pch_lpc_priv; struct fwnode_handle *pch_lpc_handle; =20 static void lpc_irq_ack(struct irq_data *d) @@ -147,6 +149,26 @@ static int pch_lpc_disabled(struct pch_lpc *priv) (readl(priv->base + LPC_INT_STS) =3D=3D 0xffffffff); } =20 +static int pch_lpc_suspend(void) +{ + pch_lpc_priv->saved_reg_ctl =3D readl(pch_lpc_priv->base + LPC_INT_CTL); + pch_lpc_priv->saved_reg_ena =3D readl(pch_lpc_priv->base + LPC_INT_ENA); + pch_lpc_priv->saved_reg_pol =3D readl(pch_lpc_priv->base + LPC_INT_POL); + return 0; +} + +static void pch_lpc_resume(void) +{ + writel(pch_lpc_priv->saved_reg_ctl, pch_lpc_priv->base + LPC_INT_CTL); + writel(pch_lpc_priv->saved_reg_ena, pch_lpc_priv->base + LPC_INT_ENA); + writel(pch_lpc_priv->saved_reg_pol, pch_lpc_priv->base + LPC_INT_POL); +} + +static struct syscore_ops pch_lpc_syscore_ops =3D { + .suspend =3D pch_lpc_suspend, + .resume =3D pch_lpc_resume, +}; + int __init pch_lpc_acpi_init(struct irq_domain *parent, struct acpi_madt_lpc_pic *acpi_pchlpc) { @@ -191,7 +213,10 @@ int __init pch_lpc_acpi_init(struct irq_domain *parent, parent_irq =3D irq_create_fwspec_mapping(&fwspec); irq_set_chained_handler_and_data(parent_irq, lpc_irq_dispatch, priv); =20 + pch_lpc_priv =3D priv; pch_lpc_handle =3D irq_handle; + register_syscore_ops(&pch_lpc_syscore_ops); + return 0; =20 free_irq_handle: --=20 2.31.1