From nobody Tue Apr 7 07:55:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D4A1C4332F for ; Thu, 13 Oct 2022 20:23:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229892AbiJMUXv (ORCPT ); Thu, 13 Oct 2022 16:23:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229793AbiJMUXb (ORCPT ); Thu, 13 Oct 2022 16:23:31 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 88B67159D4B for ; Thu, 13 Oct 2022 13:23:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665692610; x=1697228610; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8RCzjNFiyTPAxja/GnLMgLgcV2ZImlmdTYbAFnTLKSI=; b=T2jo2jPYSGKBo149pgoWpiFM20creK0j/M1nT1o7lNOG0g3x3+RQVtMG ya0V45VnvkCAcqtWQXRMeP2wvaMjAcKM1eyaWxrn9FEl05vsp9PT3kUvV WaK9ssyed3dsWGOyl7/cnar3LkqYLrDTxJLTGg9HRfPClj7zXmoOpscoG cMXj7kqpnBDa8ycoMa3GPqg80ImsBYl0ao+eOdSdoJR5zCqxlNpgSWV4Z 0hVO/qtBuB+vcl46rrJ9lBwxTyi0Z6Lh+qjdyfJswr6Ym3lnIJbH7Wuoi OBqXMEwpTZL1ZZR+tmJ/Dt7TeTgjiuCh45eSSn5vCvxtM6ZatxKdzAUhf w==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="302808955" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="302808955" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 13:23:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="690271039" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="690271039" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:27 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 1/6] x86/cpufeature: add cpu feature bit for LKGS Date: Thu, 13 Oct 2022 13:01:29 -0700 Message-Id: <20221013200134.1487-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "H. Peter Anvin (Intel)" Add the CPU feature bit for LKGS (Load "Kernel" GS). LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specificaton https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment=E2=80=99s descriptor cache, which is exactly what Linux kernel does to load a user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Chang S. Bae Signed-off-by: Xin Li Link: https://lkml.org/lkml/2022/10/11/1139 --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index b71f4f2ecdd5..3dc1a48c2796 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index ef4775c6db01..9d45071d1730 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ --=20 2.34.1 From nobody Tue Apr 7 07:55:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F0F0C4332F for ; Thu, 13 Oct 2022 20:23:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229866AbiJMUXn (ORCPT ); Thu, 13 Oct 2022 16:23:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229755AbiJMUXa (ORCPT ); Thu, 13 Oct 2022 16:23:30 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 44160159D51 for ; Thu, 13 Oct 2022 13:23:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665692610; x=1697228610; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LPkLGLb6ct3NaqkfE/fcmAkN388PX6Fn1d7MFn2Rg6I=; b=AKsPAOgkoT9uYH8ql73lDu8lsHfzzmqrJPwNvZfTfyPJTJ9Vpq5AQS8c ymDogrT/rbUPs8046tfSwqEcSRSbDMgswO95fJ0agkD4/IuvCeS+WDYv3 q6leno4kVs+9QgYx/HgZ7qqBO8I4FYkLlMrcEntArrPd1XtbUoztATvn5 C3GjjIMuBEL8ghykc0DCuQyzQgkIOTkBjmHx4pHqWjX8Tm3JtUUsPGj2B mp2SrTTYnH8inVeMNt4PIzYF6OrIQaSiSRxxADa4K+AayzVJudKuCiJFz FcKdpC50vMvP0cYbNfZEn0mwXz3PXgX+7e7RXUqATVyZWyUS7C5hDCJPm w==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="302808952" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="302808952" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 13:23:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="690271043" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="690271043" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:27 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 2/6] x86/opcode: add LKGS instruction to x86-opcode-map Date: Thu, 13 Oct 2022 13:01:30 -0700 Message-Id: <20221013200134.1487-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Add the instruction opcode used by LKGS. Opcode number is per public FRED draft spec v3.0 https://cdrdv2.intel.com/v1/dl/getContent/678938. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.= txt index d12d1358f96d..5168ee0360b2 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable =20 GrpTable: Grp7 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86= -opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable =20 GrpTable: Grp7 --=20 2.34.1 From nobody Tue Apr 7 07:55:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F3E6C433FE for ; Thu, 13 Oct 2022 20:23:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229874AbiJMUXq (ORCPT ); Thu, 13 Oct 2022 16:23:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55236 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229803AbiJMUXb (ORCPT ); Thu, 13 Oct 2022 16:23:31 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD363159D53 for ; Thu, 13 Oct 2022 13:23:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665692610; x=1697228610; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1YbzoiUXSvQWzBUraiDzjfmE9NvY0qFctz1F+7sN7Sw=; b=c6YHXMAqeciH2NJdcryUrWnbiMKBXQt92+ALdUDlWYIdpMULcBKyClZE dcvUTWyPXA6e3Gp1sskBm4PpTVY6d17SnSbYCXAAQRIlPANamFSkM3THA oqVg3Wp3nZOsM49WbKguCnFD3G8i+JOm+q9fjeKcoGRGt7ZFESv9+Yj82 eRy71gmT5hcp7XKdneo8eJ3X2k5Cl4RuYdQ6tN1oiAM6Qi3rrgehjtfq7 FS4K5eawMWnIbxL8kYBBvxbg8aYWm6VjGAY28z/SYjASNxPKvpoFEo7UV HcDjmLFK7+JKIHtSeb37A8zpxNMc3KN1m5Fkf2UPJYVnivUlNr9DnXUeJ A==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="302808960" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="302808960" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 13:23:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="690271046" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="690271046" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:27 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 3/6] x86/gsseg: make asm_load_gs_index() take an u16 Date: Thu, 13 Oct 2022 13:01:31 -0700 Message-Id: <20221013200134.1487-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..e0c48998d2fb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -779,7 +779,7 @@ _ASM_NOKPROBE(common_interrupt_return) =20 /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } =20 -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); =20 static inline void native_load_gs_index(unsigned int selector) { --=20 2.34.1 From nobody Tue Apr 7 07:55:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36862C4332F for ; Thu, 13 Oct 2022 20:24:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229745AbiJMUYA (ORCPT ); Thu, 13 Oct 2022 16:24:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229844AbiJMUXc (ORCPT ); Thu, 13 Oct 2022 16:23:32 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 875C4159D56 for ; Thu, 13 Oct 2022 13:23:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665692611; x=1697228611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UaC8ceQnideTemOSR0AnD9gGv296yv6KtEQKYgHeIg4=; b=JXX3Y2FFoP7rZrS57moacsUWRCz3WxJ7dE23q0R56fqYpT9jGyGh+udN wKz60Q3om83n0nhW1FGu1qG5PyIDiq5r1B8yH17zb9WCoKMZdwEugDKQp 9swTWY7eDf3u8tHNzTGNbWVqLHLrMkKJ3xbhuxaXyu/WhjeFw1sS1WAVm +NY+eoPI2Z8QhSyAWDj0mSyXpyMB2TGUN5EI8ysjlPkLqzMTqHw9Ww66O ulDbfyQc12nUhf0/N0vBilzzretaj+eFFGd3zHb0Bc9PXgikH7qS4ndML i5kaYoTJiNgbzGmvGzYhGOWMlsMgNShiY12U9tefnNouA4EuADT7j8etR g==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="302808968" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="302808968" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 13:23:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="690271049" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="690271049" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:27 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 4/6] x86/gsseg: move local_irq_save/restore() into asm_load_gs_index() Date: Thu, 13 Oct 2022 13:01:32 -0700 Message-Id: <20221013200134.1487-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" The need to disable/enable interrupts around asm_load_gs_index() is a consequence of the implementation. Prepare for using the LKGS instruction, which is locally atomic and therefore doesn't need interrupts disabled. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 26 +++++++++++++++++++++----- arch/x86/include/asm/special_insns.h | 4 ---- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index e0c48998d2fb..cc6ba6672418 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -778,19 +778,35 @@ SYM_CODE_END(common_interrupt_return) _ASM_NOKPROBE(common_interrupt_return) =20 /* - * Reload gs selector with exception handling + * Reload gs selector with exception handling. This is used only on + * native, so using swapgs, pushf, popf, cli, sti, ... directly is fine. + * * di: new selector + * rax: scratch register * * Is in entry.text as it shouldn't be instrumented. + * + * Note: popf is slow, so use pushf to read IF and then execute cli/sti + * if necessary. */ SYM_FUNC_START(asm_load_gs_index) FRAME_BEGIN + pushf + pop %rax + andl $X86_EFLAGS_IF, %eax /* Interrupts enabled? */ + jz 1f + cli +1: swapgs .Lgs_change: ANNOTATE_NOENDBR // error_entry movl %edi, %gs 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE swapgs + testl %eax, %eax + jz 3f + sti +3: FRAME_END RET =20 @@ -799,12 +815,12 @@ SYM_FUNC_START(asm_load_gs_index) swapgs /* switch back to user gs */ .macro ZAP_GS /* This can't be a string because the preprocessor needs to see it. */ - movl $__USER_DS, %eax - movl %eax, %gs + movl $__USER_DS, %edi + movl %edi, %gs .endm ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG - xorl %eax, %eax - movl %eax, %gs + xorl %edi, %edi + movl %edi, %gs jmp 2b =20 _ASM_EXTABLE(.Lgs_change, .Lbad_gs) diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index a71d0e8d4684..6de00dec6564 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -124,11 +124,7 @@ extern asmlinkage void asm_load_gs_index(u16 selector); =20 static inline void native_load_gs_index(unsigned int selector) { - unsigned long flags; - - local_irq_save(flags); asm_load_gs_index(selector); - local_irq_restore(flags); } =20 static inline unsigned long __read_cr4(void) --=20 2.34.1 From nobody Tue Apr 7 07:55:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B92E4C433FE for ; Thu, 13 Oct 2022 20:23:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229924AbiJMUXy (ORCPT ); Thu, 13 Oct 2022 16:23:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229831AbiJMUXc (ORCPT ); Thu, 13 Oct 2022 16:23:32 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F905159D51 for ; Thu, 13 Oct 2022 13:23:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665692611; x=1697228611; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=juR16UITaT3MxswvlHsDaympRivW8hA0yaAGOHpwels=; b=AIgriEcAIKcaPZQ9w+sCBIVNwWtdvVmxgPbSm6YZejMgp383TsY9q3ms nDOwxkaO25BSZIdyr08va/vlBv7K0Vf4VGpSu8VQQ1nsT/p996EKL2ouz QoHSFVLWE+KJVJ8MOt1oSg6VcyCcEHcXej4xfzKYSguf1wEd2y/xfKvKQ K/HbzUMyONCtHXCrFBuqSOkghZ9SwPAkWPOrpATVKwlBQvCcL5qtpM3d6 SXXEST7KgnXiT3+4xBSTry9pSzWgpR/0W1zCHOh8IBPcisXZksvYtSFht TrLtJ4BoLX9hqIxtYhpLNve3Yl61a60tINmNuQcKBIPDR/cR9PS3uvHkp g==; X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="302808963" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="302808963" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2022 13:23:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="690271051" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="690271051" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:28 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 5/6] x86/gsseg: move load_gs_index() to its own header file Date: Thu, 13 Oct 2022 13:01:33 -0700 Message-Id: <20221013200134.1487-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" depends on , so in order to be able to use alternatives in native_load_gs_index(), factor it out into a separate header file. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/gsseg.h | 32 ++++++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 17 --------------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + 6 files changed, 36 insertions(+), 17 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index c9c3859322fa..14c739303099 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -34,6 +34,7 @@ #include #include #include +#include =20 static inline void reload_segments(struct sigcontext_32 *sc) { diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h new file mode 100644 index 000000000000..5e3b56a17098 --- /dev/null +++ b/arch/x86/include/asm/gsseg.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_GSSEG_H +#define _ASM_X86_GSSEG_H + +#include +#include + +#ifdef CONFIG_X86_64 + +extern asmlinkage void asm_load_gs_index(u16 selector); + +static inline void native_load_gs_index(unsigned int selector) +{ + asm_load_gs_index(selector); +} + +#endif /* CONFIG_X86_64 */ + +#ifndef CONFIG_PARAVIRT_XXL + +static inline void load_gs_index(unsigned int selector) +{ +#ifdef CONFIG_X86_64 + native_load_gs_index(selector); +#else + loadsegment(gs, selector); +#endif +} + +#endif /* CONFIG_PARAVIRT_XXL */ + +#endif /* _ASM_X86_GSSEG_H */ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index b8d40ddeab00..e01aa74a6de7 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -12,6 +12,7 @@ #include #include #include +#include =20 extern atomic64_t last_mm_ctx_id; =20 diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index 6de00dec6564..cfd9499b617c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,13 +120,6 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } =20 -extern asmlinkage void asm_load_gs_index(u16 selector); - -static inline void native_load_gs_index(unsigned int selector) -{ - asm_load_gs_index(selector); -} - static inline unsigned long __read_cr4(void) { return native_read_cr4(); @@ -180,16 +173,6 @@ static inline void wbinvd(void) native_wbinvd(); } =20 - -static inline void load_gs_index(unsigned int selector) -{ -#ifdef CONFIG_X86_64 - native_load_gs_index(selector); -#else - loadsegment(gs, selector); -#endif -} - #endif /* CONFIG_PARAVIRT_XXL */ =20 static inline void clflush(volatile void *__p) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 7ca2d46c08cc..00f6a92551d2 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -32,6 +32,7 @@ #include #include #include +#include =20 /* * nop stub, which must not clobber anything *including the stack* to diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 3c883e064242..3ffbab0081f4 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #include "tls.h" =20 --=20 2.34.1 From nobody Tue Apr 7 07:55:58 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BFB3C433FE for ; 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([172.25.112.68]) by fmsmga008.fm.intel.com with ESMTP; 13 Oct 2022 13:23:28 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org, brgerst@gmail.com, chang.seok.bae@intel.com Subject: [PATCH v3 6/6] x86/gsseg: use the LKGS instruction if available for load_gs_index() Date: Thu, 13 Oct 2022 13:01:34 -0700 Message-Id: <20221013200134.1487-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com> References: <20221013200134.1487-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Brian Gerst Signed-off-by: Xin Li link: https://lkml.org/lkml/2022/10/7/352 link: https://lkml.org/lkml/2022/10/7/373 link: https://lkml.org/lkml/2022/10/10/1286 --- arch/x86/include/asm/gsseg.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h index 5e3b56a17098..7463ac65ef56 100644 --- a/arch/x86/include/asm/gsseg.h +++ b/arch/x86/include/asm/gsseg.h @@ -3,15 +3,39 @@ #define _ASM_X86_GSSEG_H =20 #include + +#include +#include +#include #include +#include =20 #ifdef CONFIG_X86_64 =20 extern asmlinkage void asm_load_gs_index(u16 selector); =20 +/* Replace with "lkgs %di" once binutils support LKGS instruction */ +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7) + static inline void native_load_gs_index(unsigned int selector) { - asm_load_gs_index(selector); + u16 sel =3D selector; + + /* + * Note: the fixup is used for the LKGS instruction, but + * it needs to be attached to the primary instruction sequence + * as it isn't something that gets patched. + * + * %rax is provided to the assembly routine as a scratch + * register. + */ + asm_inline volatile("1:\n" + ALTERNATIVE("call asm_load_gs_index\n", + _ASM_BYTES(0x3e) LKGS_DI, + X86_FEATURE_LKGS) + _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel]) + : ASM_OUTPUT2([sel] "+D" (sel), ASM_CALL_CONSTRAINT) + : : _ASM_AX); } =20 #endif /* CONFIG_X86_64 */ --=20 2.34.1