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[82.149.19.102]) by smtp.gmail.com with ESMTPSA id ku15-20020a170907788f00b0078b551d2fa3sm211109ejc.103.2022.10.13.11.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 11:12:50 -0700 (PDT) From: Jernej Skrabec To: maxime@cerno.tech, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, wens@csie.org, samuel@sholland.org Cc: iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 5/5] iommu/sun50i: Invalidate iova at map and unmap Date: Thu, 13 Oct 2022 20:12:20 +0200 Message-Id: <20221013181221.3247429-6-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221013181221.3247429-1-jernej.skrabec@gmail.com> References: <20221013181221.3247429-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Mapped and unmapped iova addresses needs to be invalidated immediately or otherwise they might or might not work when used by master device. This was discovered when running video decoder conformity test with Cedrus. Some videos were now and then decoded incorrectly and generated page faults. Fixes: 4100b8c229b3 ("iommu: Add Allwinner H6 IOMMU driver") Signed-off-by: Jernej Skrabec --- drivers/iommu/sun50i-iommu.c | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/drivers/iommu/sun50i-iommu.c b/drivers/iommu/sun50i-iommu.c index 7c3b2ac552da..21e47ce6946a 100644 --- a/drivers/iommu/sun50i-iommu.c +++ b/drivers/iommu/sun50i-iommu.c @@ -518,6 +518,53 @@ static u32 *sun50i_dte_get_page_table(struct sun50i_io= mmu_domain *sun50i_domain, return page_table; } =20 +static void sun50i_iommu_zap_iova(struct sun50i_iommu *iommu, unsigned lon= g iova) +{ + unsigned long flags; + u32 reg; + int ret; + + spin_lock_irqsave(&iommu->iommu_lock, flags); + + iommu_write(iommu, IOMMU_AUTO_GATING_REG, 0); + + iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_REG, iova); + iommu_write(iommu, IOMMU_TLB_IVLD_ADDR_MASK_REG, GENMASK(11, 0)); + iommu_write(iommu, IOMMU_TLB_IVLD_ENABLE_REG, IOMMU_TLB_IVLD_ENABLE_ENABL= E); + + ret =3D readl_poll_timeout_atomic(iommu->base + IOMMU_TLB_IVLD_ENABLE_REG, + reg, !reg, 1, 2000); + if (ret) + dev_warn(iommu->dev, "TLB invalidation timed out!\n"); + + iommu_write(iommu, IOMMU_AUTO_GATING_REG, IOMMU_AUTO_GATING_ENABLE); + + spin_unlock_irqrestore(&iommu->iommu_lock, flags); +} + +static void sun50i_iommu_zap_ptw_cache(struct sun50i_iommu *iommu, unsigne= d long iova) +{ + unsigned long flags; + u32 reg; + int ret; + + spin_lock_irqsave(&iommu->iommu_lock, flags); + + iommu_write(iommu, IOMMU_AUTO_GATING_REG, 0); + + iommu_write(iommu, IOMMU_PC_IVLD_ADDR_REG, iova); + iommu_write(iommu, IOMMU_PC_IVLD_ENABLE_REG, IOMMU_PC_IVLD_ENABLE_ENABLE); + + ret =3D readl_poll_timeout_atomic(iommu->base + IOMMU_PC_IVLD_ENABLE_REG, + reg, !reg, 1, 2000); + if (ret) + dev_warn(iommu->dev, "PTW cache invalidation timed out!\n"); + + iommu_write(iommu, IOMMU_AUTO_GATING_REG, IOMMU_AUTO_GATING_ENABLE); + + spin_unlock_irqrestore(&iommu->iommu_lock, flags); +} + static int sun50i_iommu_map(struct iommu_domain *domain, unsigned long iov= a, phys_addr_t paddr, size_t size, int prot, gfp_t gfp) { @@ -546,6 +593,8 @@ static int sun50i_iommu_map(struct iommu_domain *domain= , unsigned long iova, =20 *pte_addr =3D sun50i_mk_pte(paddr, prot); sun50i_table_flush(sun50i_domain, pte_addr, 1); + sun50i_iommu_zap_iova(iommu, iova); + sun50i_iommu_zap_ptw_cache(iommu, iova); =20 out: return ret; @@ -571,6 +620,8 @@ static size_t sun50i_iommu_unmap(struct iommu_domain *d= omain, unsigned long iova =20 memset(pte_addr, 0, sizeof(*pte_addr)); sun50i_table_flush(sun50i_domain, pte_addr, 1); + sun50i_iommu_zap_iova(sun50i_domain->iommu, iova); + sun50i_iommu_zap_ptw_cache(sun50i_domain->iommu, iova); =20 return SZ_4K; } --=20 2.38.0