From nobody Tue Apr 7 05:00:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D16EC433FE for ; Tue, 11 Oct 2022 19:07:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229955AbiJKTHM (ORCPT ); Tue, 11 Oct 2022 15:07:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229487AbiJKTHB (ORCPT ); Tue, 11 Oct 2022 15:07:01 -0400 Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2698962F4 for ; Tue, 11 Oct 2022 12:06:59 -0700 (PDT) Received: by mail-lj1-x233.google.com with SMTP id c20so5558453ljj.7 for ; Tue, 11 Oct 2022 12:06:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u3yCxlgQB512X9ob5aJS/z0CokvR7tPgP4XCG40BHqE=; b=Hz36Pc5KPd9FTHiuSAXPnPa3/eFQVuyM9GeEa90R53eVcseTvHuPbOsBKKY2jUOQ2z xjbHYQRypmucWn1AcYXTJA7u7IWIC/Uf18oN4cnq6mU8DwYXLRlBnHYfZ4RWmtOK0rK4 nn2z28HzuEZm5pJhaK+Lz/4H4+GT1TRpEnXDu9HGdPdPANN+zEUJGDZQRvyI0Nh3rd3D RrOFMu+0sHHMolnNZ+wtvs//D6WPM7xZlYkiE7q7Mz8AMmu4mj6+n4pYxvsVDDpi2JoF kffq3o1pLxhnVXSodjNJiCbGmC8sZ+zWnR2eNFcYRzb9HkSF4VyyPpEIMSBy6BGAlNzl 8kqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u3yCxlgQB512X9ob5aJS/z0CokvR7tPgP4XCG40BHqE=; b=Mn3Ta2BvQYit/BbEB+UMIqBH3HLqlQc9JE97LLRMSFkoytK8R0QA7+01pARxbMBWQw 4CtXa4K7R4Fhr3XTBlHKq4gFz+2hcXApGj+C4++3zUWyHUrnXMQYS5A1unLkOFEwLjGc 56ZgfTm7tipbhmRldyAAynRcABZNx5iesEP8PqGehwgu8WwwdZv/FibA0sfTqvBHcg3z 2MeN3bbv10GpyLsVtjEOl3x8tnCxwacaePFS4qLH4zYNmp2OKhkBXYqklsJrn2TH1kmm BUmMLEEo7cx/cZmEqk95S96QYRk+yPItZXLfFzbgLD8Jrz0pIBPMFLqy4dnCfrlgu5y+ KM6Q== X-Gm-Message-State: ACrzQf1wlcjU8pISGllWQfyOVf1L8C6+M1JYRJjYTGuywZqFxUqv0djj iRHXtjedf88bn6cFoNHADCu3mA== X-Google-Smtp-Source: AMsMyM5rMdNrdEkjLsPITCScXjidoHrYDycUXDd2xiQwlIigWhBpGQo0kf2L/k9iTiLNR8KxRsWIyw== X-Received: by 2002:a05:651c:b23:b0:26f:b2b9:6976 with SMTP id b35-20020a05651c0b2300b0026fb2b96976mr3175606ljr.85.1665515217340; Tue, 11 Oct 2022 12:06:57 -0700 (PDT) Received: from michal-H370M-DS3H.office.semihalf.net ([83.142.187.84]) by smtp.googlemail.com with ESMTPSA id p9-20020a2eb7c9000000b00262fae1ffe6sm2270477ljo.110.2022.10.11.12.06.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 12:06:57 -0700 (PDT) From: =?UTF-8?q?Micha=C5=82=20Grzelak?= To: devicetree@vger.kernel.org Cc: mw@semihalf.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@semihalf.com, =?UTF-8?q?Micha=C5=82=20Grzelak?= Subject: [PATCH v3 1/3] dt-bindings: net: marvell,pp2: convert to json-schema Date: Tue, 11 Oct 2022 21:06:11 +0200 Message-Id: <20221011190613.13008-2-mig@semihalf.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011190613.13008-1-mig@semihalf.com> References: <20221011190613.13008-1-mig@semihalf.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Convert the marvell,pp2 bindings from text to proper schema. Move 'marvell,system-controller' and 'dma-coherent' properties from port up to the controller node, to match what is actually done in DT. Signed-off-by: Micha=C5=82 Grzelak --- .../devicetree/bindings/net/marvell,pp2.yaml | 286 ++++++++++++++++++ .../devicetree/bindings/net/marvell-pp2.txt | 141 --------- MAINTAINERS | 2 +- 3 files changed, 287 insertions(+), 142 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/marvell,pp2.yaml delete mode 100644 Documentation/devicetree/bindings/net/marvell-pp2.txt diff --git a/Documentation/devicetree/bindings/net/marvell,pp2.yaml b/Docum= entation/devicetree/bindings/net/marvell,pp2.yaml new file mode 100644 index 000000000000..24c6aeb46814 --- /dev/null +++ b/Documentation/devicetree/bindings/net/marvell,pp2.yaml @@ -0,0 +1,286 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/marvell,pp2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell CN913X / Marvell Armada 375, 7K, 8K Ethernet Controller + +maintainers: + - Marcin Wojtas + - Russell King + +description: | + Marvell Armada 375 Ethernet Controller (PPv2.1) + Marvell Armada 7K/8K Ethernet Controller (PPv2.2) + Marvell CN913X Ethernet Controller (PPv2.3) + +properties: + compatible: + enum: + - marvell,armada-375-pp2 + - marvell,armada-7k-pp22 + + reg: + minItems: 3 + maxItems: 4 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + minItems: 2 + items: + - description: main controller clock + - description: GOP clock + - description: MG clock + - description: MG Core clock + - description: AXI clock + + clock-names: + minItems: 2 + items: + - const: pp_clk + - const: gop_clk + - const: mg_clk + - const: mg_core_clk + - const: axi_clk + + dma-coherent: true + + marvell,system-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to the system controller. + +patternProperties: + '^(ethernet-)?port@[0-9]+$': + type: object + description: subnode for each ethernet port. + + properties: + interrupts: + minItems: 1 + maxItems: 10 + description: interrupt(s) for the port + + interrupt-names: + minItems: 1 + items: + - const: hif0 + - const: hif1 + - const: hif2 + - const: hif3 + - const: hif4 + - const: hif5 + - const: hif6 + - const: hif7 + - const: hif8 + - const: link + + description: > + if more than a single interrupt for is given, must be the + name associated to the interrupts listed. Valid names are: + "hifX", with X in [0..8], and "link". The names "tx-cpu0", + "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported + for backward compatibility but shouldn't be used for new + additions. + + reg: + description: ID of the port from the MAC point of view. + + port-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + ID of the port from the MAC point of view. + Legacy binding for backward compatibility. + + phy: + $ref: /schemas/types.yaml#/definitions/phandle + description: > + a phandle to a phy node defining the PHY address + (as the reg property, a single integer). + + phy-mode: + $ref: ethernet-controller.yaml#/properties/phy-mode + + marvell,loopback: + $ref: /schemas/types.yaml#/definitions/flag + description: port is loopback mode. + + gop-port-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + only for marvell,armada-7k-pp22, ID of the port from the + GOP (Group Of Ports) point of view. This ID is used to index the + per-port registers in the second register area. + + required: + - interrupts + - port-id + - phy-mode + - reg + +required: + - compatible + - reg + - clocks + - clock-names + +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + const: marvell,armada-7k-pp22 + then: + properties: + reg: + items: + - description: Packet Processor registers + - description: Networking interfaces registers + - description: CM3 address space used for TX Flow Control + + clocks: + minItems: 5 + + clock-names: + minItems: 5 + + patternProperties: + '^(ethernet-)?port@[0-9]+$': + required: + - gop-port-id + + required: + - marvell,system-controller + else: + properties: + reg: + items: + - description: Packet Processor registers + - description: LMS registers + - description: Register area per eth0 + - description: Register area per eth1 + + clocks: + maxItems: 2 + + clock-names: + maxItems: 2 + + patternProperties: + '^(ethernet-)?port@[0-9]+$': + properties: + gop-port-id: false + +unevaluatedProperties: false + +examples: + - | + // For Armada 375 variant + #include + #include + + ethernet@f0000 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,armada-375-pp2"; + reg =3D <0xf0000 0xa000>, + <0xc0000 0x3060>, + <0xc4000 0x100>, + <0xc5000 0x100>; + clocks =3D <&gateclk 3>, <&gateclk 19>; + clock-names =3D "pp_clk", "gop_clk"; + + ethernet-port@0 { + interrupts =3D ; + reg =3D <0>; + port-id =3D <0>; /* For backward compatibility. */ + phy =3D <&phy0>; + phy-mode =3D "rgmii-id"; + }; + + ethernet-port@1 { + interrupts =3D ; + reg =3D <1>; + port-id =3D <1>; /* For backward compatibility. */ + phy =3D <&phy3>; + phy-mode =3D "gmii"; + }; + }; + + - | + // For Armada 7k/8k and Cn913x variants + #include + #include + + ethernet@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "marvell,armada-7k-pp22"; + reg =3D <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; + clocks =3D <&cp0_clk 1 3>, <&cp0_clk 1 9>, + <&cp0_clk 1 5>, <&cp0_clk 1 6>, <&cp0_clk 1 18>; + clock-names =3D "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_c= lk"; + marvell,system-controller =3D <&cp0_syscon0>; + + ethernet-port@0 { + interrupts =3D , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", + "hif5", "hif6", "hif7", "hif8", "link"; + phy-mode =3D "10gbase-r"; + reg =3D <0>; + port-id =3D <0>; /* For backward compatibility. */ + gop-port-id =3D <0>; + }; + + ethernet-port@1 { + interrupts =3D , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", + "hif5", "hif6", "hif7", "hif8", "link"; + phy-mode =3D "rgmii-id"; + reg =3D <1>; + port-id =3D <1>; /* For backward compatibility. */ + gop-port-id =3D <2>; + }; + + ethernet-port@2 { + interrupts =3D , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", + "hif5", "hif6", "hif7", "hif8", "link"; + phy-mode =3D "gmii"; + reg =3D <2>; + port-id =3D <2>; /* For backward compatibility. */ + gop-port-id =3D <3>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/marvell-pp2.txt b/Docume= ntation/devicetree/bindings/net/marvell-pp2.txt deleted file mode 100644 index ce15c173f43f..000000000000 --- a/Documentation/devicetree/bindings/net/marvell-pp2.txt +++ /dev/null @@ -1,141 +0,0 @@ -* Marvell Armada 375 Ethernet Controller (PPv2.1) - Marvell Armada 7K/8K Ethernet Controller (PPv2.2) - Marvell CN913X Ethernet Controller (PPv2.3) - -Required properties: - -- compatible: should be one of: - "marvell,armada-375-pp2" - "marvell,armada-7k-pp2" -- reg: addresses and length of the register sets for the device. - For "marvell,armada-375-pp2", must contain the following register - sets: - - common controller registers - - LMS registers - - one register area per Ethernet port - For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the f= ollowing register - sets: - - packet processor registers - - networking interfaces registers - - CM3 address space used for TX Flow Control - -- clocks: pointers to the reference clocks for this device, consequently: - - main controller clock (for both armada-375-pp2 and armada-7k-pp2) - - GOP clock (for both armada-375-pp2 and armada-7k-pp2) - - MG clock (only for armada-7k-pp2) - - MG Core clock (only for armada-7k-pp2) - - AXI clock (only for armada-7k-pp2) -- clock-names: names of used clocks, must be "pp_clk", "gop_clk", "mg_clk", - "mg_core_clk" and "axi_clk" (the 3 latter only for armada-7k-pp2). - -The ethernet ports are represented by subnodes. At least one port is -required. - -Required properties (port): - -- interrupts: interrupt(s) for the port -- port-id: ID of the port from the MAC point of view -- gop-port-id: only for marvell,armada-7k-pp2, ID of the port from the - GOP (Group Of Ports) point of view. This ID is used to index the - per-port registers in the second register area. -- phy-mode: See ethernet.txt file in the same directory - -Optional properties (port): - -- marvell,loopback: port is loopback mode -- phy: a phandle to a phy node defining the PHY address (as the reg - property, a single integer). -- interrupt-names: if more than a single interrupt for is given, must be t= he - name associated to the interrupts listed. Valid names a= re: - "hifX", with X in [0..8], and "link". The names "tx-cpu= 0", - "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are sup= ported - for backward compatibility but shouldn't be used for new - additions. -- marvell,system-controller: a phandle to the system controller. - -Example for marvell,armada-375-pp2: - -ethernet@f0000 { - compatible =3D "marvell,armada-375-pp2"; - reg =3D <0xf0000 0xa000>, - <0xc0000 0x3060>, - <0xc4000 0x100>, - <0xc5000 0x100>; - clocks =3D <&gateclk 3>, <&gateclk 19>; - clock-names =3D "pp_clk", "gop_clk"; - - eth0: eth0@c4000 { - interrupts =3D ; - port-id =3D <0>; - phy =3D <&phy0>; - phy-mode =3D "gmii"; - }; - - eth1: eth1@c5000 { - interrupts =3D ; - port-id =3D <1>; - phy =3D <&phy3>; - phy-mode =3D "gmii"; - }; -}; - -Example for marvell,armada-7k-pp2: - -cpm_ethernet: ethernet@0 { - compatible =3D "marvell,armada-7k-pp22"; - reg =3D <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; - clocks =3D <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, - <&cpm_syscon0 1 5>, <&cpm_syscon0 1 6>, <&cpm_syscon0 1 18>; - clock-names =3D "pp_clk", "gop_clk", "mg_clk", "mg_core_clk", "axi_clk"; - - eth0: eth0 { - interrupts =3D , - , - , - , - , - , - , - , - , - ; - interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", - "hif5", "hif6", "hif7", "hif8", "link"; - port-id =3D <0>; - gop-port-id =3D <0>; - }; - - eth1: eth1 { - interrupts =3D , - , - , - , - , - , - , - , - , - ; - interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", - "hif5", "hif6", "hif7", "hif8", "link"; - port-id =3D <1>; - gop-port-id =3D <2>; - }; - - eth2: eth2 { - interrupts =3D , - , - , - , - , - , - , - , - , - ; - interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", - "hif5", "hif6", "hif7", "hif8", "link"; - port-id =3D <2>; - gop-port-id =3D <3>; - }; -}; diff --git a/MAINTAINERS b/MAINTAINERS index e68a0804394d..51da1b56d87e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12292,7 +12292,7 @@ M: Marcin Wojtas M: Russell King L: netdev@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/net/marvell-pp2.txt +F: Documentation/devicetree/bindings/net/marvell,pp2.yaml F: drivers/net/ethernet/marvell/mvpp2/ =20 MARVELL MWIFIEX WIRELESS DRIVER --=20 2.25.1 From nobody Tue Apr 7 05:00:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76051C433FE for ; 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Tue, 11 Oct 2022 12:06:57 -0700 (PDT) From: =?UTF-8?q?Micha=C5=82=20Grzelak?= To: devicetree@vger.kernel.org Cc: mw@semihalf.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@semihalf.com Subject: [PATCH v3 2/3] arm64: dts: marvell: Update network description to match schema Date: Tue, 11 Oct 2022 21:06:12 +0200 Message-Id: <20221011190613.13008-3-mig@semihalf.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011190613.13008-1-mig@semihalf.com> References: <20221011190613.13008-1-mig@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Marcin Wojtas Update the PP2 ethernet ports subnodes' names to match schema enforced by the marvell,pp2.yaml contents. Add new required properties ('reg') which contains information about the port ID, keeping 'port-id' ones for backward compatibility. Signed-off-by: Marcin Wojtas --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boo= t/dts/marvell/armada-cp11x.dtsi index d6c0990a267d..7d0043824f2a 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -58,6 +58,8 @@ config-space@CP11X_BASE { ranges =3D <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>; =20 CP11X_LABEL(ethernet): ethernet@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; compatible =3D "marvell,armada-7k-pp22"; reg =3D <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>; clocks =3D <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>, @@ -69,7 +71,7 @@ CP11X_LABEL(ethernet): ethernet@0 { status =3D "disabled"; dma-coherent; =20 - CP11X_LABEL(eth0): eth0 { + CP11X_LABEL(eth0): ethernet-port@0 { interrupts =3D <39 IRQ_TYPE_LEVEL_HIGH>, <43 IRQ_TYPE_LEVEL_HIGH>, <47 IRQ_TYPE_LEVEL_HIGH>, @@ -83,12 +85,13 @@ CP11X_LABEL(eth0): eth0 { interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", "hif5", "hif6", "hif7", "hif8", "link"; - port-id =3D <0>; + reg =3D <0>; + port-id =3D <0>; /* For backward compatibility. */ gop-port-id =3D <0>; status =3D "disabled"; }; =20 - CP11X_LABEL(eth1): eth1 { + CP11X_LABEL(eth1): ethernet-port@1 { interrupts =3D <40 IRQ_TYPE_LEVEL_HIGH>, <44 IRQ_TYPE_LEVEL_HIGH>, <48 IRQ_TYPE_LEVEL_HIGH>, @@ -102,12 +105,13 @@ CP11X_LABEL(eth1): eth1 { interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", "hif5", "hif6", "hif7", "hif8", "link"; - port-id =3D <1>; + reg =3D <1>; + port-id =3D <1>; /* For backward compatibility. */ gop-port-id =3D <2>; status =3D "disabled"; }; =20 - CP11X_LABEL(eth2): eth2 { + CP11X_LABEL(eth2): ethernet-port@2 { interrupts =3D <41 IRQ_TYPE_LEVEL_HIGH>, <45 IRQ_TYPE_LEVEL_HIGH>, <49 IRQ_TYPE_LEVEL_HIGH>, @@ -121,7 +125,8 @@ CP11X_LABEL(eth2): eth2 { interrupt-names =3D "hif0", "hif1", "hif2", "hif3", "hif4", "hif5", "hif6", "hif7", "hif8", "link"; - port-id =3D <2>; + reg =3D <2>; + port-id =3D <2>; /* For backward compatibility. */ gop-port-id =3D <3>; status =3D "disabled"; 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Tue, 11 Oct 2022 12:06:59 -0700 (PDT) Received: from michal-H370M-DS3H.office.semihalf.net ([83.142.187.84]) by smtp.googlemail.com with ESMTPSA id p9-20020a2eb7c9000000b00262fae1ffe6sm2270477ljo.110.2022.10.11.12.06.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Oct 2022 12:06:58 -0700 (PDT) From: =?UTF-8?q?Micha=C5=82=20Grzelak?= To: devicetree@vger.kernel.org Cc: mw@semihalf.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, upstream@semihalf.com Subject: [PATCH v3 3/3] ARM: dts: armada-375: Update network description to match schema Date: Tue, 11 Oct 2022 21:06:13 +0200 Message-Id: <20221011190613.13008-4-mig@semihalf.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221011190613.13008-1-mig@semihalf.com> References: <20221011190613.13008-1-mig@semihalf.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Marcin Wojtas Update the PP2 ethernet ports subnodes' names to match schema enforced by the marvell,pp2.yaml contents. Add new required properties ('reg') which contains information about the port ID, keeping 'port-id' ones for backward compatibility. Signed-off-by: Marcin Wojtas --- arch/arm/boot/dts/armada-375.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-3= 75.dtsi index 929deaf312a5..9fbe0cfec48f 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -178,6 +178,8 @@ mdio: mdio@c0054 { =20 /* Network controller */ ethernet: ethernet@f0000 { + #address-cells =3D <1>; + #size-cells =3D <0>; compatible =3D "marvell,armada-375-pp2"; reg =3D <0xf0000 0xa000>, /* Packet Processor regs */ <0xc0000 0x3060>, /* LMS regs */ @@ -187,15 +189,17 @@ ethernet: ethernet@f0000 { clock-names =3D "pp_clk", "gop_clk"; status =3D "disabled"; =20 - eth0: eth0 { + eth0: ethernet-port@0 { interrupts =3D ; - port-id =3D <0>; + reg =3D <0>; + port-id =3D <0>; /* For backward compatibility. */ status =3D "disabled"; }; =20 - eth1: eth1 { + eth1: ethernet-port@1 { interrupts =3D ; - port-id =3D <1>; + reg =3D <1>; + port-id =3D <1>; /* For backward compatibility. */ status =3D "disabled"; }; }; --=20 2.25.1