From nobody Tue Apr 7 03:29:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37E26C433FE for ; Mon, 10 Oct 2022 19:24:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229821AbiJJTYB (ORCPT ); Mon, 10 Oct 2022 15:24:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229446AbiJJTXw (ORCPT ); Mon, 10 Oct 2022 15:23:52 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9779760693 for ; Mon, 10 Oct 2022 12:23:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665429831; x=1696965831; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UDzg+9uANYdDBV+Ra3lQotFnvAmXOEkeoHs76rgla5s=; b=hpn3hKrQYc9pddwQOHPLGXhPHPQ2LwXEy0isutX4XzT34GSAX3cRTLzQ /idZjgPD2njUNXCWmkNIWvZbRdHJmTxFQe3/1pHiEFs/R2Dd+XnEwamLy wRlci3Ok4kE6nMs9RCzX2IJEbLBqc71TnAOhCsdOcW3325BK1Qivx1B23 rJ09ohX5541HChrH5qBXZslN64UESSoZTlGrqCWTXX8jpSCAlOEwduAuM 4nBpa7negTaJY2YpB+B4M1i64eGyxxy21SDAon+9mqAfMWTZKvFSxyLlY Zy7ITTwMuINW0BlVsEgCEtnNeruFTsURbTbKMmhDV3LJXVa2J0yGtb3mW Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="284044528" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="284044528" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 12:23:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="694762688" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="694762688" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga004.fm.intel.com with ESMTP; 10 Oct 2022 12:23:49 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org Subject: [PATCH v2 1/6] x86/cpufeature: add cpu feature bit for LKGS Date: Mon, 10 Oct 2022 12:01:54 -0700 Message-Id: <20221010190159.11920-2-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221010190159.11920-1-xin3.li@intel.com> References: <20221010190159.11920-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: "H. Peter Anvin (Intel)" Add the CPU feature bit for LKGS (Load "Kernel" GS). LKGS instruction is introduced with Intel FRED (flexible return and event delivery) specificaton https://cdrdv2.intel.com/v1/dl/getContent/678938. LKGS behaves like the MOV to GS instruction except that it loads the base address into the IA32_KERNEL_GS_BASE MSR instead of the GS segment=E2=80=99s descriptor cache, which is exactly what Linux kernel does to load a user level GS base. Thus, with LKGS, there is no need to SWAPGS away from the kernel GS base. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/include/asm/cpufeatures.h | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index ef4775c6db01..459fb0c21dd4 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +#define X86_FEATURE_LKGS (12*32+ 18) /* Load "kernel" (userspace) gs */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index ef4775c6db01..459fb0c21dd4 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -308,6 +308,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ #define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instruction= s */ +#define X86_FEATURE_LKGS (12*32+ 18) /* Load "kernel" (userspace) gs */ =20 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */ #define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */ --=20 2.34.1 From nobody Tue Apr 7 03:29:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C1EFAC433FE for ; Mon, 10 Oct 2022 19:24:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229770AbiJJTX6 (ORCPT ); Mon, 10 Oct 2022 15:23:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229480AbiJJTXw (ORCPT ); Mon, 10 Oct 2022 15:23:52 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A84EF61119 for ; Mon, 10 Oct 2022 12:23:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665429831; x=1696965831; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LPkLGLb6ct3NaqkfE/fcmAkN388PX6Fn1d7MFn2Rg6I=; b=gcFt76w5TSVOZdxW5BMyTsQGTWLYvuu0C+Ffs4Y1EPTQJ6VGy8k1yzeJ 6MTDJMbFmXUQU9EcCAG2TgH/vV6IlKyYyAYxwQdkaYa26FV61EojR0zjH uh06TYdNUVFqO95kGKebH/TaozytCN+pTvk/V4zcb2hdM10Jya1Y0ay+6 bqnm81bSTpwsqN8L5dmjbtlZ7g4V7MfjLNaoZCIU7WwIURQKQglYUo0AB n+0MOoJl3pbWYQlDKjxTbQ57gc8xN9i66NlJtHUlIdEnk96E0achIeuP6 faHEk3OZzInymOVUDI4l7XBV41VBjW9YJWdkWi2dHRqgMhJToJznO3Dul g==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="284044531" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="284044531" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 12:23:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="694762689" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="694762689" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga004.fm.intel.com with ESMTP; 10 Oct 2022 12:23:50 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org Subject: [PATCH v2 2/6] x86/opcode: add LKGS instruction to x86-opcode-map Date: Mon, 10 Oct 2022 12:01:55 -0700 Message-Id: <20221010190159.11920-3-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221010190159.11920-1-xin3.li@intel.com> References: <20221010190159.11920-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Add the instruction opcode used by LKGS. Opcode number is per public FRED draft spec v3.0 https://cdrdv2.intel.com/v1/dl/getContent/678938. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/lib/x86-opcode-map.txt | 1 + tools/arch/x86/lib/x86-opcode-map.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.= txt index d12d1358f96d..5168ee0360b2 100644 --- a/arch/x86/lib/x86-opcode-map.txt +++ b/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable =20 GrpTable: Grp7 diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86= -opcode-map.txt index d12d1358f96d..5168ee0360b2 100644 --- a/tools/arch/x86/lib/x86-opcode-map.txt +++ b/tools/arch/x86/lib/x86-opcode-map.txt @@ -1047,6 +1047,7 @@ GrpTable: Grp6 3: LTR Ew 4: VERR Ew 5: VERW Ew +6: LKGS Ew (F2) EndTable =20 GrpTable: Grp7 --=20 2.34.1 From nobody Tue Apr 7 03:29:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72722C433F5 for ; Mon, 10 Oct 2022 19:24:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229963AbiJJTYI (ORCPT ); Mon, 10 Oct 2022 15:24:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229597AbiJJTXw (ORCPT ); Mon, 10 Oct 2022 15:23:52 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FA7161122 for ; Mon, 10 Oct 2022 12:23:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665429832; x=1696965832; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1YbzoiUXSvQWzBUraiDzjfmE9NvY0qFctz1F+7sN7Sw=; b=KF/BsLxVUqNcvSh9O6XYW+Dwq9eCiyKu3WSMqda1hQ1eUjSLMCi5pO24 M7i3KBkGscKVtwEmKGP2nLu65MNHABFxxMh0RSqk1g0TENsOHKzx7Tpga Ygyfo2ioNJn/WzcWoxTpPtKAd8mRSGhRXYUwmd+va7eDi3z2VhBoCdnpi lPdMszg+NMZt36HSHt2+EPfEn44TgNbvPPIRn/FI2y792rKDYlzl8ZMh/ UsCBuhqNzfYjwbvl/WrR3NbT2y1AjcOYWFpQvdgdpGhTYuEXK0DGR+ntx LvSTgF+VwogvvpsJG7M2pz158Rippc658EgXQ24iTiMIZh4jIJMjTP5bt Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="284044533" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="284044533" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 12:23:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="694762692" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="694762692" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga004.fm.intel.com with ESMTP; 10 Oct 2022 12:23:50 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org Subject: [PATCH v2 3/6] x86/gsseg: make asm_load_gs_index() take an u16 Date: Mon, 10 Oct 2022 12:01:56 -0700 Message-Id: <20221010190159.11920-4-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221010190159.11920-1-xin3.li@intel.com> References: <20221010190159.11920-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" Let gcc know that only the low 16 bits of load_gs_index() argument actually matter. It might allow it to create slightly better code. However, do not propagate this into the prototypes of functions that end up being paravirtualized, to avoid unnecessary changes. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 2 +- arch/x86/include/asm/special_insns.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 9953d966d124..e0c48998d2fb 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -779,7 +779,7 @@ _ASM_NOKPROBE(common_interrupt_return) =20 /* * Reload gs selector with exception handling - * edi: new selector + * di: new selector * * Is in entry.text as it shouldn't be instrumented. */ diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index 35f709f619fb..a71d0e8d4684 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,7 +120,7 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } =20 -extern asmlinkage void asm_load_gs_index(unsigned int selector); +extern asmlinkage void asm_load_gs_index(u16 selector); =20 static inline void native_load_gs_index(unsigned int selector) { --=20 2.34.1 From nobody Tue Apr 7 03:29:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E74B6C433F5 for ; Mon, 10 Oct 2022 19:24:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229920AbiJJTYE (ORCPT ); Mon, 10 Oct 2022 15:24:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229599AbiJJTXw (ORCPT ); Mon, 10 Oct 2022 15:23:52 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3381461125 for ; Mon, 10 Oct 2022 12:23:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665429832; x=1696965832; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UaC8ceQnideTemOSR0AnD9gGv296yv6KtEQKYgHeIg4=; b=HdZxdCa72mJ9+89bCrCRus/m7l1iMNJtH8Zin1ZkXStPWY7xN1WVsKjA x7djjMaJJfyxW8lJs0DwJsYjx/7koELcSQMMp+eTMZko44lPhPskdIx4N IKMj1h3C3EL2kwkMfha/+ZwM9+o2Wp+5b+Mk8aptS43e3RwpRtJLWcMRo pQe3YjxN2mvN5ae3qNF15CT0u8eB8nNq7rU2U0LStPBYrNEH0KseiZckH MfsMIcvjfQaQX0BQWvZcNhHTKLSBh4ALt4SxCrX7m9iS9t/Qy8J21/YI9 y1Pal/Vju3P8LgMvgU1gPZJ3Bmzz4Hkb9eNAAYaA+CESX6FuYTuTF+a5o g==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="284044536" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="284044536" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 12:23:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="694762693" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="694762693" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga004.fm.intel.com with ESMTP; 10 Oct 2022 12:23:50 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org Subject: [PATCH v2 4/6] x86/gsseg: move local_irq_save/restore() into asm_load_gs_index() Date: Mon, 10 Oct 2022 12:01:57 -0700 Message-Id: <20221010190159.11920-5-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221010190159.11920-1-xin3.li@intel.com> References: <20221010190159.11920-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" The need to disable/enable interrupts around asm_load_gs_index() is a consequence of the implementation. Prepare for using the LKGS instruction, which is locally atomic and therefore doesn't need interrupts disabled. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/entry/entry_64.S | 26 +++++++++++++++++++++----- arch/x86/include/asm/special_insns.h | 4 ---- 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index e0c48998d2fb..cc6ba6672418 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -778,19 +778,35 @@ SYM_CODE_END(common_interrupt_return) _ASM_NOKPROBE(common_interrupt_return) =20 /* - * Reload gs selector with exception handling + * Reload gs selector with exception handling. This is used only on + * native, so using swapgs, pushf, popf, cli, sti, ... directly is fine. + * * di: new selector + * rax: scratch register * * Is in entry.text as it shouldn't be instrumented. + * + * Note: popf is slow, so use pushf to read IF and then execute cli/sti + * if necessary. */ SYM_FUNC_START(asm_load_gs_index) FRAME_BEGIN + pushf + pop %rax + andl $X86_EFLAGS_IF, %eax /* Interrupts enabled? */ + jz 1f + cli +1: swapgs .Lgs_change: ANNOTATE_NOENDBR // error_entry movl %edi, %gs 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE swapgs + testl %eax, %eax + jz 3f + sti +3: FRAME_END RET =20 @@ -799,12 +815,12 @@ SYM_FUNC_START(asm_load_gs_index) swapgs /* switch back to user gs */ .macro ZAP_GS /* This can't be a string because the preprocessor needs to see it. */ - movl $__USER_DS, %eax - movl %eax, %gs + movl $__USER_DS, %edi + movl %edi, %gs .endm ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG - xorl %eax, %eax - movl %eax, %gs + xorl %edi, %edi + movl %edi, %gs jmp 2b =20 _ASM_EXTABLE(.Lgs_change, .Lbad_gs) diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index a71d0e8d4684..6de00dec6564 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -124,11 +124,7 @@ extern asmlinkage void asm_load_gs_index(u16 selector); =20 static inline void native_load_gs_index(unsigned int selector) { - unsigned long flags; - - local_irq_save(flags); asm_load_gs_index(selector); - local_irq_restore(flags); } =20 static inline unsigned long __read_cr4(void) --=20 2.34.1 From nobody Tue Apr 7 03:29:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9B72CC4332F for ; Mon, 10 Oct 2022 19:24:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229624AbiJJTYO (ORCPT ); Mon, 10 Oct 2022 15:24:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229689AbiJJTXx (ORCPT ); Mon, 10 Oct 2022 15:23:53 -0400 Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D187960693 for ; Mon, 10 Oct 2022 12:23:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665429832; x=1696965832; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=juR16UITaT3MxswvlHsDaympRivW8hA0yaAGOHpwels=; b=g8nrM80n4dYW4Xcs2GjTUl2gOZLoypFdfa98gjmbkKdJgsPrSE9M0m93 mqdzUX+tGksW+YfTu+cDJR34PgyxiENf/Re8e+9btioczxCRcvIzq1CpK uU7zCnc/43oZYxZfQwBWdqolyR3CKWmHQzJWPYemoWnmtyF63ZlHKr4uV jkjGp/Uuk9+G9QkZS1q6wwwgheRuDxDG5bHcwDpagQgNxgxj8zaKVZ8xZ yaQzkUOi0iGuIY4IqIur5U/EWjEMPIG8Az11pe30L7JDBNzg11/5NqoPv iVWKFITQTip3wO5gcf5D5xb1MQwEwkuBsnWdmRFV4CSQ+ZwTXVmnmRbb6 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="284044538" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="284044538" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 12:23:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="694762695" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="694762695" Received: from unknown (HELO fred..) ([172.25.112.68]) by fmsmga004.fm.intel.com with ESMTP; 10 Oct 2022 12:23:50 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org Subject: [PATCH v2 5/6] x86/gsseg: move load_gs_index() to its own header file Date: Mon, 10 Oct 2022 12:01:58 -0700 Message-Id: <20221010190159.11920-6-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221010190159.11920-1-xin3.li@intel.com> References: <20221010190159.11920-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" depends on , so in order to be able to use alternatives in native_load_gs_index(), factor it out into a separate header file. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Xin Li --- arch/x86/ia32/ia32_signal.c | 1 + arch/x86/include/asm/gsseg.h | 32 ++++++++++++++++++++++++++++ arch/x86/include/asm/mmu_context.h | 1 + arch/x86/include/asm/special_insns.h | 17 --------------- arch/x86/kernel/paravirt.c | 1 + arch/x86/kernel/tls.c | 1 + 6 files changed, 36 insertions(+), 17 deletions(-) create mode 100644 arch/x86/include/asm/gsseg.h diff --git a/arch/x86/ia32/ia32_signal.c b/arch/x86/ia32/ia32_signal.c index c9c3859322fa..14c739303099 100644 --- a/arch/x86/ia32/ia32_signal.c +++ b/arch/x86/ia32/ia32_signal.c @@ -34,6 +34,7 @@ #include #include #include +#include =20 static inline void reload_segments(struct sigcontext_32 *sc) { diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h new file mode 100644 index 000000000000..5e3b56a17098 --- /dev/null +++ b/arch/x86/include/asm/gsseg.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_X86_GSSEG_H +#define _ASM_X86_GSSEG_H + +#include +#include + +#ifdef CONFIG_X86_64 + +extern asmlinkage void asm_load_gs_index(u16 selector); + +static inline void native_load_gs_index(unsigned int selector) +{ + asm_load_gs_index(selector); +} + +#endif /* CONFIG_X86_64 */ + +#ifndef CONFIG_PARAVIRT_XXL + +static inline void load_gs_index(unsigned int selector) +{ +#ifdef CONFIG_X86_64 + native_load_gs_index(selector); +#else + loadsegment(gs, selector); +#endif +} + +#endif /* CONFIG_PARAVIRT_XXL */ + +#endif /* _ASM_X86_GSSEG_H */ diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_= context.h index b8d40ddeab00..e01aa74a6de7 100644 --- a/arch/x86/include/asm/mmu_context.h +++ b/arch/x86/include/asm/mmu_context.h @@ -12,6 +12,7 @@ #include #include #include +#include =20 extern atomic64_t last_mm_ctx_id; =20 diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/sp= ecial_insns.h index 6de00dec6564..cfd9499b617c 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -120,13 +120,6 @@ static inline void native_wbinvd(void) asm volatile("wbinvd": : :"memory"); } =20 -extern asmlinkage void asm_load_gs_index(u16 selector); - -static inline void native_load_gs_index(unsigned int selector) -{ - asm_load_gs_index(selector); -} - static inline unsigned long __read_cr4(void) { return native_read_cr4(); @@ -180,16 +173,6 @@ static inline void wbinvd(void) native_wbinvd(); } =20 - -static inline void load_gs_index(unsigned int selector) -{ -#ifdef CONFIG_X86_64 - native_load_gs_index(selector); -#else - loadsegment(gs, selector); -#endif -} - #endif /* CONFIG_PARAVIRT_XXL */ =20 static inline void clflush(volatile void *__p) diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c index 7ca2d46c08cc..00f6a92551d2 100644 --- a/arch/x86/kernel/paravirt.c +++ b/arch/x86/kernel/paravirt.c @@ -32,6 +32,7 @@ #include #include #include +#include =20 /* * nop stub, which must not clobber anything *including the stack* to diff --git a/arch/x86/kernel/tls.c b/arch/x86/kernel/tls.c index 3c883e064242..3ffbab0081f4 100644 --- a/arch/x86/kernel/tls.c +++ b/arch/x86/kernel/tls.c @@ -12,6 +12,7 @@ #include #include #include +#include =20 #include "tls.h" =20 --=20 2.34.1 From nobody Tue Apr 7 03:29:41 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E70C2C433F5 for ; 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([172.25.112.68]) by fmsmga004.fm.intel.com with ESMTP; 10 Oct 2022 12:23:50 -0700 From: Xin Li To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org Subject: [PATCH v2 6/6] x86/gsseg: use the LKGS instruction if available for load_gs_index() Date: Mon, 10 Oct 2022 12:01:59 -0700 Message-Id: <20221010190159.11920-7-xin3.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221010190159.11920-1-xin3.li@intel.com> References: <20221010190159.11920-1-xin3.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "H. Peter Anvin (Intel)" The LKGS instruction atomically loads a segment descriptor into the %gs descriptor registers, *except* that %gs.base is unchanged, and the base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly what we want this function to do. Signed-off-by: H. Peter Anvin (Intel) Signed-off-by: Peter Zijlstra (Intel) Signed-off-by: Xin Li link: https://lkml.org/lkml/2022/10/7/352 link: https://lkml.org/lkml/2022/10/7/373 --- arch/x86/include/asm/gsseg.h | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h index 5e3b56a17098..4aaef7a1d68f 100644 --- a/arch/x86/include/asm/gsseg.h +++ b/arch/x86/include/asm/gsseg.h @@ -3,15 +3,40 @@ #define _ASM_X86_GSSEG_H =20 #include + +#include +#include +#include #include +#include =20 #ifdef CONFIG_X86_64 =20 extern asmlinkage void asm_load_gs_index(u16 selector); =20 +/* Replace with "lkgs %di" once binutils support LKGS instruction */ +#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7) + static inline void native_load_gs_index(unsigned int selector) { - asm_load_gs_index(selector); + u16 sel =3D selector; + + /* + * Note: the fixup is used for the LKGS instruction, but + * it needs to be attached to the primary instruction sequence + * as it isn't something that gets patched. + * + * %rax is provided to the assembly routine as a scratch + * register. + */ + asm_inline volatile("1:\n" + ALTERNATIVE("call asm_load_gs_index\n", + _ASM_BYTES(0x3e) LKGS_DI, + X86_FEATURE_LKGS) + _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel]) + : ASM_CALL_CONSTRAINT + : [sel] "D" (sel) + : "memory", _ASM_AX); } =20 #endif /* CONFIG_X86_64 */ --=20 2.34.1