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(fttx-pool-217.61.149.60.bambit.de [217.61.149.60]) by mxbox2.masterlogin.de (Postfix) with ESMTPSA id 3B9F310042C; Sat, 8 Oct 2022 16:48:09 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Sam Shih , Sean Wang , Linus Walleij , Matthias Brugger , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Frank Wunderlich Subject: [PATCH] pinctrl: mediatek: allow configuring uart rx/tx and rts/cts separately Date: Sat, 8 Oct 2022 18:48:06 +0200 Message-Id: <20221008164807.113590-1-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mail-ID: 9c542c94-e206-4f0b-99de-2c03d23c5142 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Sam Shih Some mt7986 boards use uart rts/cts pins as gpio, This patch allows to change rts/cts to gpio mode, but keep rx/tx as UART function. Signed-off-by: Frank Wunderlich Signed-off-by: Sam Shih --- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 32 ++++++++++++++++++----- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/me= diatek/pinctrl-mt7986.c index f26869f1a367..95f32e62e02f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -675,11 +675,17 @@ static int mt7986_uart1_1_funcs[] =3D { 4, 4, 4, 4, }; static int mt7986_spi1_2_pins[] =3D { 29, 30, 31, 32, }; static int mt7986_spi1_2_funcs[] =3D { 1, 1, 1, 1, }; =20 -static int mt7986_uart1_2_pins[] =3D { 29, 30, 31, 32, }; -static int mt7986_uart1_2_funcs[] =3D { 3, 3, 3, 3, }; +static int mt7986_uart1_2_rx_tx_pins[] =3D { 29, 30, }; +static int mt7986_uart1_2_rx_tx_funcs[] =3D { 3, 3, }; =20 -static int mt7986_uart2_0_pins[] =3D { 29, 30, 31, 32, }; -static int mt7986_uart2_0_funcs[] =3D { 4, 4, 4, 4, }; +static int mt7986_uart1_2_cts_rts_pins[] =3D { 31, 32, }; +static int mt7986_uart1_2_cts_rts_funcs[] =3D { 3, 3, }; + +static int mt7986_uart2_0_rx_tx_pins[] =3D { 29, 30, }; +static int mt7986_uart2_0_rx_tx_funcs[] =3D { 4, 4, }; + +static int mt7986_uart2_0_cts_rts_pins[] =3D { 31, 32, }; +static int mt7986_uart2_0_cts_rts_funcs[] =3D { 4, 4, }; =20 static int mt7986_spi0_pins[] =3D { 33, 34, 35, 36, }; static int mt7986_spi0_funcs[] =3D { 1, 1, 1, 1, }; @@ -708,6 +714,12 @@ static int mt7986_pcie_reset_funcs[] =3D { 1, }; static int mt7986_uart1_pins[] =3D { 42, 43, 44, 45, }; static int mt7986_uart1_funcs[] =3D { 1, 1, 1, 1, }; =20 +static int mt7986_uart1_rx_tx_pins[] =3D { 42, 43, }; +static int mt7986_uart1_rx_tx_funcs[] =3D { 1, 1, }; + +static int mt7986_uart1_cts_rts_pins[] =3D { 44, 45, }; +static int mt7986_uart1_cts_rts_funcs[] =3D { 1, 1, }; + static int mt7986_uart2_pins[] =3D { 46, 47, 48, 49, }; static int mt7986_uart2_funcs[] =3D { 1, 1, 1, 1, }; =20 @@ -749,6 +761,8 @@ static const struct group_desc mt7986_groups[] =3D { PINCTRL_PIN_GROUP("wifi_led", mt7986_wifi_led), PINCTRL_PIN_GROUP("i2c", mt7986_i2c), PINCTRL_PIN_GROUP("uart1_0", mt7986_uart1_0), + PINCTRL_PIN_GROUP("uart1_rx_tx", mt7986_uart1_rx_tx), + PINCTRL_PIN_GROUP("uart1_cts_rts", mt7986_uart1_cts_rts), PINCTRL_PIN_GROUP("pcie_clk", mt7986_pcie_clk), PINCTRL_PIN_GROUP("pcie_wake", mt7986_pcie_wake), PINCTRL_PIN_GROUP("spi1_0", mt7986_spi1_0), @@ -760,8 +774,10 @@ static const struct group_desc mt7986_groups[] =3D { PINCTRL_PIN_GROUP("spi1_1", mt7986_spi1_1), PINCTRL_PIN_GROUP("uart1_1", mt7986_uart1_1), PINCTRL_PIN_GROUP("spi1_2", mt7986_spi1_2), - PINCTRL_PIN_GROUP("uart1_2", mt7986_uart1_2), - PINCTRL_PIN_GROUP("uart2_0", mt7986_uart2_0), + PINCTRL_PIN_GROUP("uart1_2_rx_tx", mt7986_uart1_2_rx_tx), + PINCTRL_PIN_GROUP("uart1_2_cts_rts", mt7986_uart1_2_cts_rts), + PINCTRL_PIN_GROUP("uart2_0_rx_tx", mt7986_uart2_0_rx_tx), + PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7986_uart2_0_cts_rts), PINCTRL_PIN_GROUP("spi0", mt7986_spi0), PINCTRL_PIN_GROUP("spi0_wp_hold", mt7986_spi0_wp_hold), PINCTRL_PIN_GROUP("uart2_1", mt7986_uart2_1), @@ -800,7 +816,9 @@ static const char *mt7986_pwm_groups[] =3D { "pwm0", "p= wm1_0", "pwm1_1", }; static const char *mt7986_spi_groups[] =3D { "spi0", "spi0_wp_hold", "spi1_0", "spi1_1", "spi1_2", "spi1_3", }; static const char *mt7986_uart_groups[] =3D { - "uart1_0", "uart1_1", "uart1_2", "uart1_3_rx_tx", "uart1_3_cts_rts", + "uart1_0", "uart1_1", "uart1_rx_tx", "uart1_cts_rts", + "uart1_2_rx_tx", "uart1_2_cts_rts", + "uart1_3_rx_tx", "uart1_3_cts_rts", "uart2_0_rx_tx", "uart2_0_cts_rts", "uart2_0", "uart2_1", "uart0", "uart1", "uart2", }; static const char *mt7986_wdt_groups[] =3D { "watchdog", }; --=20 2.34.1