From nobody Sat Sep 21 14:26:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBADCC433FE for ; Fri, 7 Oct 2022 09:35:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229955AbiJGJfP (ORCPT ); Fri, 7 Oct 2022 05:35:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229884AbiJGJey (ORCPT ); Fri, 7 Oct 2022 05:34:54 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2FFB222530; Fri, 7 Oct 2022 02:34:51 -0700 (PDT) X-UUID: 8f552dee2242493c942757e4e1616358-20221007 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=IPdq1wqpZgXQbq4SylhQEuMywjQXA6uP4TcffdIhE2A=; b=ha4JbFFj/GyFucmGHsWhGqTkrEtnftA06kROQr5fqruGpoOSs64psLH/8WE5THJnOA5yF43v44bVUW6Bg+ssvC9eDxY701qMQru6nUSRpFDIBa1QbKTcX3b7w2YOMborYz03dbS5QMaGbdJhiFHcXOk9PGP8fAgNkObLCl5Yj6c=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:6042a522-4ddd-4dba-804e-7081721857cf,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:95 X-CID-INFO: VERSION:1.1.11,REQID:6042a522-4ddd-4dba-804e-7081721857cf,IP:0,URL :0,TC:0,Content:-5,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:95 X-CID-META: VersionHash:39a5ff1,CLOUDID:91d039e1-2948-402a-a6e4-b5d31fe11eb7,B ulkID:2210071734478VZT1X3B,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil, COL:0 X-UUID: 8f552dee2242493c942757e4e1616358-20221007 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1147147979; Fri, 07 Oct 2022 17:34:45 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Fri, 7 Oct 2022 17:34:44 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Fri, 7 Oct 2022 17:34:44 +0800 From: Allen-KH Cheng To: Wim Van Sebroeck , Guenter Roeck , Krzysztof Kozlowski , Matthias Brugger , Rob Herring , CC: , , , , , , Allen-KH Cheng Subject: [PATCH v2 7/8] watchdog: mtk_wdt: Add support for MT6795 Helio X10 watchdog and toprgu Date: Fri, 7 Oct 2022 17:34:36 +0800 Message-ID: <20221007093437.12228-8-allen-kh.cheng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20221007093437.12228-1-allen-kh.cheng@mediatek.com> References: <20221007093437.12228-1-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: AngeloGioacchino Del Regno Add support for the toprgu reset controller and watchdog for the MediaTek MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno Co-developed-by: Allen-KH Cheng Signed-off-by: Allen-KH Cheng Reviewed-by: Guenter Roeck --- drivers/watchdog/mtk_wdt.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c index e97787536792..5fa42b7d4b4d 100644 --- a/drivers/watchdog/mtk_wdt.c +++ b/drivers/watchdog/mtk_wdt.c @@ -10,6 +10,7 @@ */ =20 #include +#include #include #include #include @@ -78,6 +79,10 @@ static const struct mtk_wdt_data mt2712_data =3D { .toprgu_sw_rst_num =3D MT2712_TOPRGU_SW_RST_NUM, }; =20 +static const struct mtk_wdt_data mt6795_data =3D { + .toprgu_sw_rst_num =3D MT6795_TOPRGU_SW_RST_NUM, +}; + static const struct mtk_wdt_data mt7986_data =3D { .toprgu_sw_rst_num =3D MT7986_TOPRGU_SW_RST_NUM, }; @@ -426,6 +431,7 @@ static int mtk_wdt_resume(struct device *dev) static const struct of_device_id mtk_wdt_dt_ids[] =3D { { .compatible =3D "mediatek,mt2712-wdt", .data =3D &mt2712_data }, { .compatible =3D "mediatek,mt6589-wdt" }, + { .compatible =3D "mediatek,mt6795-wdt", .data =3D &mt6795_data }, { .compatible =3D "mediatek,mt7986-wdt", .data =3D &mt7986_data }, { .compatible =3D "mediatek,mt8183-wdt", .data =3D &mt8183_data }, { .compatible =3D "mediatek,mt8186-wdt", .data =3D &mt8186_data }, --=20 2.18.0