From nobody Mon Apr 6 19:36:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF2F9C433FE for ; Thu, 6 Oct 2022 07:18:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230134AbiJFHR7 (ORCPT ); Thu, 6 Oct 2022 03:17:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229987AbiJFHRx (ORCPT ); Thu, 6 Oct 2022 03:17:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 184C14B986 for ; Thu, 6 Oct 2022 00:17:53 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A3B2461861 for ; Thu, 6 Oct 2022 07:17:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E9DEEC433D7; Thu, 6 Oct 2022 07:17:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665040672; bh=w9W7UBpVdspzCyp6qUSPQAQAXbvMYaSbMRYZmTO4oSM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=t1HVQJNxlNTNOXW0QK/oloZXr/BfPEYQmtRgt+XfD5WPHOtKRssM2aR3KVYJfEzOV xzRBv2NPcusfEyme5F8TuA/xyELvb7joEpSGuNMo7PnsUqt+FJSbL3vQpwrr7RJfjy jsw6d94M7lhEHj6hnuIHHx3EoFnt+qmIblM12CxDeGXF9vrPIBGJdKy9Fdnk/R2ep2 8hUX+H7r1d/zw91NxlqKgChRu0h+uPqmRy62YhYLIofwiCdFCrHeoxc371xNNFGqkS Mfurgm+G/9HtR55C3+E4BEQIHBMuiACaB5dMsWfEPelLDVpAUC4pwlYNULWa6cTXqo IQLqY9Y21g1TQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/8] riscv: move riscv_noncoherent_supported() out of ZICBOM probe Date: Thu, 6 Oct 2022 15:08:11 +0800 Message-Id: <20221006070818.3616-2-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" It's a bit wired to call riscv_noncoherent_supported() once when insmod a module. Move the calling out of feature patch func. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 7 +------ arch/riscv/kernel/setup.c | 4 ++++ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3b5583db9d80..03611b3ef45e 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -272,12 +272,7 @@ static bool __init_or_module cpufeature_probe_zicbom(u= nsigned int stage) case RISCV_ALTERNATIVES_EARLY_BOOT: return false; default: - if (riscv_isa_extension_available(NULL, ZICBOM)) { - riscv_noncoherent_supported(); - return true; - } else { - return false; - } + return riscv_isa_extension_available(NULL, ZICBOM); } #endif =20 diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 2dfc463b86bb..1a055c3f5d9d 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -299,6 +299,10 @@ void __init setup_arch(char **cmdline_p) riscv_init_cbom_blocksize(); riscv_fill_hwcap(); apply_boot_alternatives(); +#ifdef CONFIG_RISCV_DMA_NONCOHERENT + if (riscv_isa_extension_available(NULL, ZICBOM)) + riscv_noncoherent_supported(); +#endif } =20 static int __init topology_init(void) --=20 2.37.2 From nobody Mon Apr 6 19:36:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53DD6C433F5 for ; Thu, 6 Oct 2022 07:18:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230262AbiJFHSG (ORCPT ); Thu, 6 Oct 2022 03:18:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230242AbiJFHR5 (ORCPT ); Thu, 6 Oct 2022 03:17:57 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [IPv6:2604:1380:4601:e00::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B810A6555E for ; Thu, 6 Oct 2022 00:17:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id CC0FDB82008 for ; Thu, 6 Oct 2022 07:17:54 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7645EC433D6; Thu, 6 Oct 2022 07:17:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665040673; bh=9fBsPwhvJZRdf+CU1/201DO08wpjks0kDIv6Vzm4XOo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DGhOU5BPOIuEr1AMhM3o0TySAQYnb7GXc/yNE8oGUnCzKZosX2CbfRpmOPVzPYaG8 xg7ukolKlHrHpfr5BY8AIY8hyQRRKlWxPDyipTKxyxW4937An4t67v3yDNJzGaXBEF dqIj3O30QH4l+RH0XZJodmkxqZXW8m3ANj34sfkrH4qDEz0whtO5iCzHnUCJon9a3R QrNpZJRbTKTa8ItDbbyG+3Z+5NJYd7uwIxn4007RdIUDkMcn1qDAZqXsl89Jh7iyIQ iYeDoURySIx+mbLiveX1VEaJI1sIyrUUkwTNSMN6/ryEIs7WjbKX8qJ+r1TMwLHkvK 0AOYxi88PT0qg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/8] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier Date: Thu, 6 Oct 2022 15:08:12 +0800 Message-Id: <20221006070818.3616-3-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now, the riscv_cpufeature_patch_func() do nothing in the stage of RISCV_ALTERNATIVES_EARLY_BOOT. We can move the detection of "early boot" stage earlier. In following patch, we will make riscv_cpufeature_patch_func() scans all ISA extensions. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner --- arch/riscv/kernel/cpufeature.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 03611b3ef45e..afa54635c180 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -307,6 +307,9 @@ void __init_or_module riscv_cpufeature_patch_func(struc= t alt_entry *begin, struct alt_entry *alt; u32 tmp; =20 + if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) + return; + for (alt =3D begin; alt < end; alt++) { if (alt->vendor_id !=3D 0) continue; --=20 2.37.2 From nobody Mon Apr 6 19:36:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BAD0C4332F for ; Thu, 6 Oct 2022 07:18:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230254AbiJFHSC (ORCPT ); Thu, 6 Oct 2022 03:18:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230236AbiJFHR5 (ORCPT ); Thu, 6 Oct 2022 03:17:57 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 51D1B43307 for ; Thu, 6 Oct 2022 00:17:56 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id A87DB61840 for ; Thu, 6 Oct 2022 07:17:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0314EC433D7; Thu, 6 Oct 2022 07:17:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665040675; bh=8Lz5QrNESG5omW8wbab7hELS/76piojMbUm54X300LI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KMsgMjntB8QBpKSj/OwpDvzeZC0oQuw2e186kJD8lDrw2bUsLph94Bw2iP6w9t/p5 vfCG2PZaKRoA3hi1nXZGVUYxLxTMnBw4TdL3s/2vVe9XOHeXMlagj5MJ8sjjgoYqiT u/iSC7qUW9ePnYTIiMCEaKpAysyiX1jeDj0uKzmKmBpuSRvsGsCzoIYZ+MiURkaOGp TYlY35eLWx3AdaihEDRt1vP1YAMBQ1fsltXWyG4oBQYo3r5hlic2fVKaeL+Ntz4wfz cQdh/g8iB3S9PJIYWmmDb7SA1z5dfNCTTah5z6N61moxkEiiMTLEHhnCxoTFqhATCO JlGn9ksW+3jlQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/8] riscv: hwcap: make ISA extension ids can be used in asm Date: Thu, 6 Oct 2022 15:08:13 +0800 Message-Id: <20221006070818.3616-4-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" We will make use of ISA extension in asm files, so make the multi-letter RISC-V ISA extension IDs macros rather than enums and move them and those base ISA extension IDs to suitable place. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner --- arch/riscv/include/asm/hwcap.h | 45 +++++++++++++++++----------------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6f59ec64175e..6cf445653911 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -12,20 +12,6 @@ #include #include =20 -#ifndef __ASSEMBLY__ -#include -/* - * This yields a mask that user programs can use to figure out what - * instruction set this cpu supports. - */ -#define ELF_HWCAP (elf_hwcap) - -enum { - CAP_HWCAP =3D 1, -}; - -extern unsigned long elf_hwcap; - #define RISCV_ISA_EXT_a ('a' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') @@ -46,21 +32,36 @@ extern unsigned long elf_hwcap; #define RISCV_ISA_EXT_BASE 26 =20 /* - * This enum represent the logical ID for each multi-letter RISC-V ISA ext= ension. + * These macros represent the logical ID for each multi-letter RISC-V ISA = extension. * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter * extensions while all the multi-letter extensions should define the next * available logical extension id. */ -enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF =3D RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, - RISCV_ISA_EXT_ZIHINTPAUSE, - RISCV_ISA_EXT_SSTC, - RISCV_ISA_EXT_ID_MAX =3D RISCV_ISA_EXT_MAX, +#define RISCV_ISA_EXT_SSCOFPMF 26 +#define RISCV_ISA_EXT_SVPBMT 27 +#define RISCV_ISA_EXT_ZICBOM 28 +#define RISCV_ISA_EXT_ZIHINTPAUSE 29 +#define RISCV_ISA_EXT_SSTC 30 + +#define RISCV_ISA_EXT_ID_MAX RISCV_ISA_EXT_MAX + + +#ifndef __ASSEMBLY__ +#include +/* + * This yields a mask that user programs can use to figure out what + * instruction set this cpu supports. + */ +#define ELF_HWCAP (elf_hwcap) + +enum { + CAP_HWCAP =3D 1, }; =20 +extern unsigned long elf_hwcap; + + /* * This enum represents the logical ID for each RISC-V ISA extension static * keys. We can use static key to optimize code path if some ISA extensions --=20 2.37.2 From nobody Mon Apr 6 19:36:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E0CAC4332F for ; Thu, 6 Oct 2022 07:18:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230125AbiJFHSJ (ORCPT ); Thu, 6 Oct 2022 03:18:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230247AbiJFHSA (ORCPT ); Thu, 6 Oct 2022 03:18:00 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67E0480EAC for ; Thu, 6 Oct 2022 00:17:59 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id D84B3B81FFA for ; Thu, 6 Oct 2022 07:17:57 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 852A2C433D6; Thu, 6 Oct 2022 07:17:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665040676; bh=gPmW8EclUiiWXqJPul8/K3RZNdAIO+8mmu462RCD6hY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UI28jwcZ1mTmqfPjRQxXCWoP0Y7AhxDRQTJgObHiu5kwUvMHB87OI7mg7CRkJsOid 5FsT04SQWYfDPjQE6hP2aCUt+BlJoc04booDabLIfHa1SoCoHBOKxTg2+tYxBNjY+2 I3YLoBvWkUoh4NpZRfK/fkF7f7tn+cfhjCegFxZR/X/vNeKOT5DJ9i7iaAK92Kpw0C AIA4MH00rRu9E2OWRsoHCj/FymcrFi1gYKPsLcn9V67JJtTp8PjcpSucjwHr9iR3C/ YRIIktXxmxmbyz4XqXQjQqWHk8KfKBQR63EqPLPmVFC4Ipb4EwhHSrLamUGdIECpDV nu/RCOyLqEWRQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/8] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions Date: Thu, 6 Oct 2022 15:08:14 +0800 Message-Id: <20221006070818.3616-5-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" make the riscv_cpufeature_patch_func() scan all ISA extensions rather than limited feature macros. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner --- arch/riscv/include/asm/errata_list.h | 9 ++-- arch/riscv/kernel/cpufeature.c | 61 +++------------------------- 2 files changed, 9 insertions(+), 61 deletions(-) diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 19a771085781..722525f4fc96 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -6,6 +6,7 @@ #define ASM_ERRATA_LIST_H =20 #include +#include #include =20 #ifdef CONFIG_ERRATA_SIFIVE @@ -20,10 +21,6 @@ #define ERRATA_THEAD_NUMBER 2 #endif =20 -#define CPUFEATURE_SVPBMT 0 -#define CPUFEATURE_ZICBOM 1 -#define CPUFEATURE_NUMBER 2 - #ifdef __ASSEMBLY__ =20 #define ALT_INSN_FAULT(x) \ @@ -53,7 +50,7 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VEN= DOR_ID, \ #define ALT_SVPBMT(_val, prot) \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ "li %0, %1\t\nslli %0,%0,%3", 0, \ - CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ + RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ : "=3Dr"(_val) \ @@ -127,7 +124,7 @@ asm volatile(ALTERNATIVE_2( \ "add a0, a0, %0\n\t" \ "2:\n\t" \ "bltu a0, %2, 3b\n\t" \ - "nop", 0, CPUFEATURE_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ + "nop", 0, RISCV_ISA_EXT_ZICBOM, CONFIG_RISCV_ISA_ZICBOM, \ "mv a0, %1\n\t" \ "j 2f\n\t" \ "3:\n\t" \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index afa54635c180..2b1f18f97253 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -251,61 +251,11 @@ void __init riscv_fill_hwcap(void) } =20 #ifdef CONFIG_RISCV_ALTERNATIVE -static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage) -{ -#ifdef CONFIG_RISCV_ISA_SVPBMT - switch (stage) { - case RISCV_ALTERNATIVES_EARLY_BOOT: - return false; - default: - return riscv_isa_extension_available(NULL, SVPBMT); - } -#endif - - return false; -} - -static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) -{ -#ifdef CONFIG_RISCV_ISA_ZICBOM - switch (stage) { - case RISCV_ALTERNATIVES_EARLY_BOOT: - return false; - default: - return riscv_isa_extension_available(NULL, ZICBOM); - } -#endif - - return false; -} - -/* - * Probe presence of individual extensions. - * - * This code may also be executed before kernel relocation, so we cannot u= se - * addresses generated by the address-of operator as they won't be valid in - * this context. - */ -static u32 __init_or_module cpufeature_probe(unsigned int stage) -{ - u32 cpu_req_feature =3D 0; - - if (cpufeature_probe_svpbmt(stage)) - cpu_req_feature |=3D (1U << CPUFEATURE_SVPBMT); - - if (cpufeature_probe_zicbom(stage)) - cpu_req_feature |=3D (1U << CPUFEATURE_ZICBOM); - - return cpu_req_feature; -} - void __init_or_module riscv_cpufeature_patch_func(struct alt_entry *begin, struct alt_entry *end, unsigned int stage) { - u32 cpu_req_feature =3D cpufeature_probe(stage); struct alt_entry *alt; - u32 tmp; =20 if (stage =3D=3D RISCV_ALTERNATIVES_EARLY_BOOT) return; @@ -313,15 +263,16 @@ void __init_or_module riscv_cpufeature_patch_func(str= uct alt_entry *begin, for (alt =3D begin; alt < end; alt++) { if (alt->vendor_id !=3D 0) continue; - if (alt->errata_id >=3D CPUFEATURE_NUMBER) { - WARN(1, "This feature id:%d is not in kernel cpufeature list", + if (alt->errata_id >=3D RISCV_ISA_EXT_ID_MAX) { + WARN(1, "This extension id:%d is not in ISA extension list", alt->errata_id); continue; } =20 - tmp =3D (1U << alt->errata_id); - if (cpu_req_feature & tmp) - patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); + if (!test_bit(alt->errata_id, riscv_isa)) + continue; + + patch_text_nosync(alt->old_ptr, alt->alt_ptr, alt->alt_len); } } #endif --=20 2.37.2 From nobody Mon Apr 6 19:36:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAEABC4332F for ; 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s=k20201202; t=1665040678; bh=0j/uuX0hnVENvwf8/IPzguN2vBgRWGMshLwXisXEuao=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EcfDM7HVjDRRV6VbrW8vYAwGnIPsyte3CG2IQOLs0wY4UNhARRoIfVWQW/QXvRR3z a3tPVfmxBb8fjZZUF20KHJ82JjQYsMJPUss/fBNRqyalsCbfURLJ6b5iSylrkhGx6A 8UtZxOiX3vZSnuEN92MULOSnNebAW6vemFZreS6MsyBQYMzdSdKaUSwquulALJP7MR M8LMKzorcWgq4LcxThpvLOR9wULt3GiqgVqJIgEFYt17xiIClKu5I00F0UwKK+aXWB 4lvgPQIqyFh8VTR6VEP1j1w3rnV1x2hajobGh4qSFWYNrzpycw77USB05daXBWh8S/ WOVok9jU7FUVw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/8] riscv: introduce riscv_has_extension_[un]likely() Date: Thu, 6 Oct 2022 15:08:15 +0800 Message-Id: <20221006070818.3616-6-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Generally, riscv ISA extensions are fixed for any specific hardware platform, that's to say, the hart features won't change any more after booting, this chacteristic make it straightforward to use static branch to check one specific ISA extension is supported or not to optimize performance. However, some ISA extensions such as SVPBMT and ZICBOM are handled via. the alternative sequences. Basically, for ease of maintenance, we prefer to use static branches in C code, but recently, Samuel found that the static branch usage in cpu_relax() breaks building with CONFIG_CC_OPTIMIZE_FOR_SIZE[1]. As Samuel pointed out, "Having a static branch in cpu_relax() is problematic because that function is widely inlined, including in some quite complex functions like in the VDSO. A quick measurement shows this static branch is responsible by itself for around 40% of the jump table." Samuel's findings pointed out one of a few downsides of static branches usage in C code to handle ISA extensions detected at boot time: static branch's metadata in the __jump_table section, which is not discarded after ISA extensions are finalized, wastes some space. I want to try to solve the issue for all possible dynamic handling of ISA extensions at boot time. Inspired by Mark[2], this patch introduces riscv_has_extension_*() helpers, which work like static branches but are patched using alternatives, thus the metadata can be freed after patching. [1]https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholla= nd.org/ [2]https://lore.kernel.org/linux-arm-kernel/20220912162210.3626215-8-mark.r= utland@arm.com/ Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwcap.h | 37 ++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 6cf445653911..54b88ee6cae1 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -8,6 +8,7 @@ #ifndef _ASM_RISCV_HWCAP_H #define _ASM_RISCV_HWCAP_H =20 +#include #include #include #include @@ -96,6 +97,42 @@ static __always_inline int riscv_isa_ext2key(int num) } } =20 +static __always_inline bool +riscv_has_extension_likely(const unsigned long ext) +{ + compiletime_assert(ext < RISCV_ISA_EXT_ID_MAX, + "ext must be < RISCV_ISA_EXT_ID_MAX"); + + asm_volatile_goto( + ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1) + : + : [ext] "i" (ext) + : + : l_no); + + return true; +l_no: + return false; +} + +static __always_inline bool +riscv_has_extension_unlikely(const unsigned long ext) +{ + compiletime_assert(ext < RISCV_ISA_EXT_ID_MAX, + "ext must be < RISCV_ISA_EXT_ID_MAX"); + + asm_volatile_goto( + ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1) + : + : [ext] "i" (ext) + : + : l_yes); + + return false; +l_yes: + return true; +} + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); =20 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) --=20 2.37.2 From nobody Mon Apr 6 19:36:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7B48C433FE for ; Thu, 6 Oct 2022 07:18:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230303AbiJFHS0 (ORCPT ); Thu, 6 Oct 2022 03:18:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32964 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbiJFHSE (ORCPT ); Thu, 6 Oct 2022 03:18:04 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 088C38D0E5 for ; Thu, 6 Oct 2022 00:18:02 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id EE2D1B81FFA for ; Thu, 6 Oct 2022 07:18:00 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 93245C433D7; Thu, 6 Oct 2022 07:17:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1665040679; bh=wKFyYNU904w6QY4gfev3PhC66aVWe3d7fSVd7HA6A2M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IvMQNMjl1RwUtGXd+y5DYWQhXF6ovFT1F9gbwYQ9DUCLT/AtW/CpJgEXa6vk/X3rz Hy4AjhLiTYg87LgHGthWRUv5nkOzRHVh0apTdwnVAYaAvLNNB8gR6+Y0KFaMV6ApEc o3fiSCtse9GuAINnXZtMlapzjG/p6XgboIl3mKYEe5U4qJACybcCESPr8PIE0Yxnp0 UXpk/y8lEZchG+YtvXgEqSrW/9lIgTNW4hLARQ2VGAZD8VTOd0Ikalby6ndQCFDkNO jgYP+FLhBhHHhwy/KxZoX5AG+P2ngIa6NVh38OTlpb0dnKCy9ZlsDKg4V4KGEgrFOF BIHSryCmYiPdA== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/8] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() Date: Thu, 6 Oct 2022 15:08:16 +0800 Message-Id: <20221006070818.3616-7-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch has_fpu() from statich branch to the new helper riscv_has_extension_likely(). Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner --- arch/riscv/include/asm/switch_to.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index 11463489fec6..60f8ca01d36e 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -59,7 +59,8 @@ static inline void __switch_to_aux(struct task_struct *pr= ev, =20 static __always_inline bool has_fpu(void) { - return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_FPU]); + return riscv_has_extension_likely(RISCV_ISA_EXT_f) || + riscv_has_extension_likely(RISCV_ISA_EXT_d); } #else static __always_inline bool has_fpu(void) { return false; } --=20 2.37.2 From nobody Mon Apr 6 19:36:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 424E3C433F5 for ; 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s=k20201202; t=1665040681; bh=q1P6JOc4LZgqnbSMLMvIBMsGeHNZHYmP6JQftBlIGdc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G9qkS9oNbnmHmAddKCyn+luppCnBMsmL1peXa0hNrUrrp6gMtETjSsdVjD8LkwKM9 seG1/vliubyojeyCrHIj1oDAyiIbGcohZo67HvIRdaTzJWwmaIff+aZ4vzUGf3dfGQ 1ATQu1DgnElg89SQK+CPYMOhlu8wT/0k+3049yXeozFcY0XKU3B4w2TXRI0yH6KNx2 RM/JO+iX0MfhF29pI25yE/osiZZE49Qq8JVsqxeiMO/cUcdJTYmmbAjgOyd2NWQVbS QaWUeqbBQNfVW8p//s9t1MxLzxWgzABSZ4tfwrfw0Q+EC02YZ/X90yypP4JOlueCKN mtwyzZNypWTjw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/8] riscv: cpu_relax: switch to riscv_has_extension_likely() Date: Thu, 6 Oct 2022 15:08:17 +0800 Message-Id: <20221006070818.3616-8-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Switch cpu_relax() from statich branch to the new helper riscv_has_extension_likely() Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner --- arch/riscv/include/asm/vdso/processor.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/a= sm/vdso/processor.h index 1e4f8b4aef79..fb30480f36a0 100644 --- a/arch/riscv/include/asm/vdso/processor.h +++ b/arch/riscv/include/asm/vdso/processor.h @@ -10,7 +10,7 @@ =20 static inline void cpu_relax(void) { - if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAU= SE])) { + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZIHINTPAUSE)) { #ifdef __riscv_muldiv int dummy; /* In lieu of a halt instruction, induce a long-latency stall. */ --=20 2.37.2 From nobody Mon Apr 6 19:36:40 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6DA88C4332F for ; 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s=k20201202; t=1665040682; bh=CDY3LOHif93dA/5GcjxLOgr3s2+BMCkMTymaYNZuiyA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qRm9LVZBrunvLnYytd4pxa3rFq57nHfJ9HsOwpVTeWPTZL9sFAJFrYSAejIdUkx2+ +YWVA9Eo3yES9EQw9vR36Re1DZf8dhjtceMd03N6u3RCK+4X2qLONGZEcfnYBLpDKL hwPWSOWrkWM9W32TBw54oRrYC8Dk0URo+cdsVvMIqxw3t3RKe5+AQWn+M4rwwHOyS9 LCNF+pVn+aEpOcKXGNhIhkrtPk6VZs8B8J/PSxyZ/1pv4uwg9411eHxebQnt0XrWbb yGu+Tcq7FLQy8KgWezDl4mFSASslMOxJxrPovxMLCwChU97FyjTPIc0grP8kx8o+cM BxDCWLzehBhzQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 8/8] riscv: remove riscv_isa_ext_keys[] array and related usage Date: Thu, 6 Oct 2022 15:08:18 +0800 Message-Id: <20221006070818.3616-9-jszhang@kernel.org> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20221006070818.3616-1-jszhang@kernel.org> References: <20221006070818.3616-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" All users have switched to riscv_has_extension_*, removed unused definitions, vars and related setting code. Signed-off-by: Jisheng Zhang Reviewed-by: Andrew Jones Reviewed-by: Heiko Stuebner --- arch/riscv/include/asm/hwcap.h | 28 ---------------------------- arch/riscv/kernel/cpufeature.c | 9 --------- 2 files changed, 37 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 54b88ee6cae1..f52fbc121ebe 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -62,18 +62,6 @@ enum { =20 extern unsigned long elf_hwcap; =20 - -/* - * This enum represents the logical ID for each RISC-V ISA extension static - * keys. We can use static key to optimize code path if some ISA extensions - * are available. - */ -enum riscv_isa_ext_key { - RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */ - RISCV_ISA_EXT_KEY_ZIHINTPAUSE, - RISCV_ISA_EXT_KEY_MAX, -}; - struct riscv_isa_ext_data { /* Name of the extension displayed to userspace via /proc/cpuinfo */ char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; @@ -81,22 +69,6 @@ struct riscv_isa_ext_data { unsigned int isa_ext_id; }; =20 -extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX]; - -static __always_inline int riscv_isa_ext2key(int num) -{ - switch (num) { - case RISCV_ISA_EXT_f: - return RISCV_ISA_EXT_KEY_FPU; - case RISCV_ISA_EXT_d: - return RISCV_ISA_EXT_KEY_FPU; - case RISCV_ISA_EXT_ZIHINTPAUSE: - return RISCV_ISA_EXT_KEY_ZIHINTPAUSE; - default: - return -EINVAL; - } -} - static __always_inline bool riscv_has_extension_likely(const unsigned long ext) { diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 2b1f18f97253..6bc3fb749274 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -28,9 +28,6 @@ unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; =20 -DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX); -EXPORT_SYMBOL(riscv_isa_ext_keys); - /** * riscv_isa_extension_base() - Get base extension word * @@ -242,12 +239,6 @@ void __init riscv_fill_hwcap(void) if (elf_hwcap & BIT_MASK(i)) print_str[j++] =3D (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); - - for_each_set_bit(i, riscv_isa, RISCV_ISA_EXT_MAX) { - j =3D riscv_isa_ext2key(i); - if (j >=3D 0) - static_branch_enable(&riscv_isa_ext_keys[j]); - } } =20 #ifdef CONFIG_RISCV_ALTERNATIVE --=20 2.37.2