From nobody Mon Apr 6 19:24:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABD40C433FE for ; Thu, 6 Oct 2022 05:05:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230101AbiJFFFP (ORCPT ); Thu, 6 Oct 2022 01:05:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230080AbiJFFFM (ORCPT ); Thu, 6 Oct 2022 01:05:12 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 290F61758D; Wed, 5 Oct 2022 22:05:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1665032708; x=1696568708; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/RVgDAix4hRDbTOVoBEsgxdvhxOVT171OOwhxnBVyRo=; b=WC3FY9t8WyBtm81YOvsaT/Mu1g0G5MI488l7BVn8+3yZy730CB111FM1 Lu9bbgnAi476KXZ/EhURxbxishR0ULEguZeF4wk7zZx/Nyq0xnX7cDT/I 2kTS2kUylPYaIUmsF4uMQCDA+PhwVCqfYJIm8vZP1OD2nvZFfyh2yiUQy Mum/1Zrncd3rYa/7n97aoxhv4+JLvLd8RU/STdRcH4G7fmusGbyaNL5eK ky9CcRfnGSxfWQw+FpE3WEOxiYoSTWBK+8TjmWRrXqvxhGyaFLqlD2aHk h8Kg00aNHR8NIlL2ORPT0LNhSS1H5O6443kRFyfCIBVBqcT/mID+2DfBG g==; X-IronPort-AV: E=Sophos;i="5.95,163,1661842800"; d="scan'208";a="177283752" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Oct 2022 22:05:07 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 5 Oct 2022 22:05:06 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 5 Oct 2022 22:05:05 -0700 From: Tharun Kumar P To: CC: , , Subject: [PATCH v2 SPI for-next 1/2] spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switch Date: Thu, 6 Oct 2022 10:35:13 +0530 Message-ID: <20221006050514.115564-2-tharunkumar.pasumarthi@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006050514.115564-1-tharunkumar.pasumarthi@microchip.com> References: <20221006050514.115564-1-tharunkumar.pasumarthi@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Microchip pci1xxxx is a PCIe switch with a multi-function endpoint on one o= f its downstream ports. SPI is one of the functions in the multi-function endpoin= t. This function has 2 SPI masters, operates at a maximum frequency of 30 MHz and s= upports 7 client devices per master. This patch adds complete functionality to the = SPI function except for suspend and resume. Signed-off-by: Tharun Kumar P --- drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-pci1xxxx.c | 397 +++++++++++++++++++++++++++++++++++++ 3 files changed, 407 insertions(+) create mode 100644 drivers/spi/spi-pci1xxxx.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 9987c3f2bd1c..08ca811440f9 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -701,6 +701,15 @@ config SPI_ORION This enables using the SPI master controller on the Orion and MVEBU chips. =20 +config SPI_PCI1XXXX + tristate "PCI1XXXX SPI Bus support" + depends on PCI + help + Say "yes" to Enable the SPI Bus support for the PCI1xxxx card + This is a PCI to SPI Bus driver + This driver can be built as module. If so, the module will be + called as spi-pci1xxxx. + config SPI_PIC32 tristate "Microchip PIC32 series SPI" depends on MACH_PIC32 || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 15d2f3835e45..b75fa3988f96 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -93,6 +93,7 @@ obj-$(CONFIG_SPI_OMAP_100K) +=3D spi-omap-100k.o obj-$(CONFIG_SPI_OMAP24XX) +=3D spi-omap2-mcspi.o obj-$(CONFIG_SPI_TI_QSPI) +=3D spi-ti-qspi.o obj-$(CONFIG_SPI_ORION) +=3D spi-orion.o +obj-$(CONFIG_SPI_PCI1XXXX) +=3D spi-pci1xxxx.o obj-$(CONFIG_SPI_PIC32) +=3D spi-pic32.o obj-$(CONFIG_SPI_PIC32_SQI) +=3D spi-pic32-sqi.o obj-$(CONFIG_SPI_PL022) +=3D spi-pl022.o diff --git a/drivers/spi/spi-pci1xxxx.c b/drivers/spi/spi-pci1xxxx.c new file mode 100644 index 000000000000..958503a4d911 --- /dev/null +++ b/drivers/spi/spi-pci1xxxx.c @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: GPL-2.0 +// PCI1xxxx SPI driver +// Copyright (C) 2022 Microchip Technology Inc. +// Authors: Tharun Kumar P +// Kumaravel Thiagarajan + + +#include +#include +#include +#include + +#define DRV_NAME "spi-pci1xxxx" + +#define SYS_FREQ_DEFAULT (62500000) + +#define PCI1XXXX_SPI_MAX_CLOCK_HZ (30000000) +#define PCI1XXXX_SPI_CLK_20MHZ (20000000) +#define PCI1XXXX_SPI_CLK_15MHZ (15000000) +#define PCI1XXXX_SPI_CLK_12MHZ (12000000) +#define PCI1XXXX_SPI_CLK_10MHZ (10000000) +#define PCI1XXXX_SPI_MIN_CLOCK_HZ (2000000) + +#define PCI1XXXX_SPI_BUFFER_SIZE (320) + +#define SPI_MST_CTL_DEVSEL_MASK (GENMASK(27, 25)) +#define SPI_MST_CTL_CMD_LEN_MASK (GENMASK(16, 8)) +#define SPI_MST_CTL_SPEED_MASK (GENMASK(7, 5)) +#define SPI_MSI_VECTOR_SEL_MASK (GENMASK(4, 4)) + +#define SPI_MST_CTL_FORCE_CE (BIT(4)) +#define SPI_MST_CTL_MODE_SEL (BIT(2)) +#define SPI_MST_CTL_GO (BIT(0)) + +#define SPI_MST1_ADDR_BASE (0x800) + +/* x refers to SPI Host Controller HW instance id in the below macros - 0 = or 1 */ + +#define SPI_MST_CMD_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x00) +#define SPI_MST_RSP_BUF_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x200) +#define SPI_MST_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x400) +#define SPI_MST_EVENT_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x420) +#define SPI_MST_EVENT_MASK_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x4= 24) +#define SPI_MST_PAD_CTL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x460) +#define SPIALERT_MST_DB_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x464) +#define SPIALERT_MST_VAL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x46= 8) +#define SPI_PCI_CTRL_REG_OFFSET(x) (((x) * SPI_MST1_ADDR_BASE) + 0x480) + +#define PCI1XXXX_IRQ_FLAGS (IRQF_NO_SUSPEND | IRQF_TRIGGER_NONE) +#define SPI_MAX_DATA_LEN 320 + +#define PCI1XXXX_SPI_TIMEOUT (msecs_to_jiffies(100)) + +#define SPI_INTR BIT(8) +#define SPI_FORCE_CE BIT(4) + +#define SPI_CHIP_SEL_COUNT 7 +#define VENDOR_ID_MCHP 0x1055 + +struct pci1xxxx_spi_internal { + u8 hw_inst; + bool spi_xfer_in_progress; + int irq; + struct completion spi_xfer_done; + struct spi_master *spi_host; + struct pci1xxxx_spi *parent; + struct { + unsigned int dev_sel : 3; + unsigned int msi_vector_sel : 1; + } prev_val; +}; + +struct pci1xxxx_spi { + struct pci_dev *dev; + u8 total_hw_instances; + void __iomem *reg_base; + struct pci1xxxx_spi_internal *spi_int[]; +}; + +static const struct pci_device_id pci1xxxx_spi_pci_id_table[] =3D { + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa004, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0= x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa014, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0= x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa024, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0= x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa034, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0= x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0001), 0, 0, 0x02}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0002), 0, 0, 0x01}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, 0x0003), 0, 0, 0x11}, + { PCI_DEVICE_SUB(VENDOR_ID_MCHP, 0xa044, PCI_ANY_ID, PCI_ANY_ID), 0, 0, 0= x01}, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, pci1xxxx_spi_pci_id_table); + +static void pci1xxxx_spi_set_cs(struct spi_device *spi, bool enable) +{ + struct pci1xxxx_spi_internal *p =3D spi_controller_get_devdata(spi->contr= oller); + struct pci1xxxx_spi *par =3D p->parent; + u32 regval; + + /* Set the DEV_SEL bits of the SPI_MST_CTL_REG */ + regval =3D readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + if (enable) { + regval &=3D ~SPI_MST_CTL_DEVSEL_MASK; + regval |=3D (spi->chip_select << 25); + writel(regval, + par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + } else { + regval &=3D ~(spi->chip_select << 25); + writel(regval, + par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + + } +} + +static u8 pci1xxxx_get_clock_div(u32 hz) +{ + u8 val =3D 0; + + if (hz >=3D PCI1XXXX_SPI_MAX_CLOCK_HZ) + val =3D 2; + else if ((hz < PCI1XXXX_SPI_MAX_CLOCK_HZ) && (hz >=3D PCI1XXXX_SPI_CLK_20= MHZ)) + val =3D 3; + else if ((hz < PCI1XXXX_SPI_CLK_20MHZ) && (hz >=3D PCI1XXXX_SPI_CLK_15MHZ= )) + val =3D 4; + else if ((hz < PCI1XXXX_SPI_CLK_15MHZ) && (hz >=3D PCI1XXXX_SPI_CLK_12MHZ= )) + val =3D 5; + else if ((hz < PCI1XXXX_SPI_CLK_12MHZ) && (hz >=3D PCI1XXXX_SPI_CLK_10MHZ= )) + val =3D 6; + else if ((hz < PCI1XXXX_SPI_CLK_10MHZ) && (hz >=3D PCI1XXXX_SPI_MIN_CLOCK= _HZ)) + val =3D 7; + else + val =3D 2; + + return val; +} + +static int pci1xxxx_spi_transfer_one(struct spi_controller *spi_ctlr, + struct spi_device *spi, struct spi_transfer *xfer) +{ + struct pci1xxxx_spi_internal *p =3D spi_controller_get_devdata(spi_ctlr); + int mode, len, loop_iter, transfer_len; + struct pci1xxxx_spi *par =3D p->parent; + unsigned long bytes_transfered; + unsigned long bytes_recvd; + unsigned long loop_count; + u8 *rx_buf, result; + const u8 *tx_buf; + u32 regval; + u8 clkdiv; + + p->spi_xfer_in_progress =3D true; + mode =3D spi->mode; + clkdiv =3D pci1xxxx_get_clock_div(xfer->speed_hz); + tx_buf =3D xfer->tx_buf; + rx_buf =3D xfer->rx_buf; + transfer_len =3D xfer->len; + regval =3D readl(par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); + writel(regval, par->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)); + + if (tx_buf) { + bytes_transfered =3D 0; + bytes_recvd =3D 0; + loop_count =3D transfer_len / SPI_MAX_DATA_LEN; + if (transfer_len % SPI_MAX_DATA_LEN !=3D 0) + loop_count +=3D 1; + + for (loop_iter =3D 0; loop_iter < loop_count; loop_iter++) { + len =3D SPI_MAX_DATA_LEN; + if ((transfer_len % SPI_MAX_DATA_LEN !=3D 0) && + (loop_iter =3D=3D loop_count - 1)) + len =3D transfer_len % SPI_MAX_DATA_LEN; + + reinit_completion(&p->spi_xfer_done); + memcpy_toio(par->reg_base + SPI_MST_CMD_BUF_OFFSET(p->hw_inst), + &tx_buf[bytes_transfered], len); + bytes_transfered +=3D len; + regval =3D readl(par->reg_base + + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + regval &=3D ~(SPI_MST_CTL_MODE_SEL | SPI_MST_CTL_CMD_LEN_MASK | + SPI_MST_CTL_SPEED_MASK); + + if (mode =3D=3D SPI_MODE_3) + regval |=3D SPI_MST_CTL_MODE_SEL; + else + regval &=3D ~SPI_MST_CTL_MODE_SEL; + + regval |=3D ((clkdiv << 5) | SPI_FORCE_CE | (len << 8)); + regval &=3D ~SPI_MST_CTL_CMD_LEN_MASK; + writel(regval, par->reg_base + + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + regval =3D readl(par->reg_base + + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + regval |=3D SPI_MST_CTL_GO; + writel(regval, par->reg_base + + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + + /* Wait for DMA_TERM interrupt */ + result =3D wait_for_completion_timeout(&p->spi_xfer_done, + PCI1XXXX_SPI_TIMEOUT); + if (!result) + return -ETIMEDOUT; + + if (rx_buf) { + memcpy_fromio(&rx_buf[bytes_recvd], par->reg_base + + SPI_MST_RSP_BUF_OFFSET(p->hw_inst), len); + bytes_recvd +=3D len; + } + } + } + + regval =3D readl(par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + regval &=3D ~SPI_FORCE_CE; + writel(regval, par->reg_base + SPI_MST_CTL_REG_OFFSET(p->hw_inst)); + p->spi_xfer_in_progress =3D false; + + return 0; +} + +static irqreturn_t pci1xxxx_spi_isr(int irq, void *dev) +{ + struct pci1xxxx_spi_internal *p =3D dev; + irqreturn_t spi_int_fired =3D IRQ_NONE; + u32 regval; + + /* Clear the SPI GO_BIT Interrupt */ + regval =3D readl(p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_ins= t)); + if (regval & SPI_INTR) { + /* Clear xfer_done */ + complete(&p->spi_xfer_done); + spi_int_fired =3D IRQ_HANDLED; + } + + writel(regval, p->parent->reg_base + SPI_MST_EVENT_REG_OFFSET(p->hw_inst)= ); + + return spi_int_fired; +} + +static int pci1xxxx_spi_probe(struct pci_dev *pdev, const struct pci_devic= e_id *ent) +{ + u8 hw_inst_cnt, iter, start, only_sec_inst; + struct pci1xxxx_spi_internal *spi_sub_ptr; + struct device *dev =3D &pdev->dev; + struct pci1xxxx_spi *spi_bus; + struct spi_master *spi_host; + u32 regval; + int ret; + + hw_inst_cnt =3D ent->driver_data & 0x0f; + start =3D (ent->driver_data & 0xf0) >> 4; + if (start =3D=3D 1) + only_sec_inst =3D 1; + else + only_sec_inst =3D 0; + + spi_bus =3D devm_kzalloc(&pdev->dev, + struct_size(spi_bus, spi_int, hw_inst_cnt), + GFP_KERNEL); + if (!spi_bus) + return -ENOMEM; + + spi_bus->dev =3D pdev; + spi_bus->total_hw_instances =3D hw_inst_cnt; + pci_set_master(pdev); + + for (iter =3D 0; iter < hw_inst_cnt; iter++) { + spi_bus->spi_int[iter] =3D devm_kzalloc(&pdev->dev, + sizeof(struct pci1xxxx_spi_internal), + GFP_KERNEL); + spi_sub_ptr =3D spi_bus->spi_int[iter]; + spi_sub_ptr->spi_host =3D devm_spi_alloc_master(dev, sizeof(struct spi_m= aster)); + if (!spi_sub_ptr->spi_host) + return -ENOMEM; + + spi_sub_ptr->parent =3D spi_bus; + spi_sub_ptr->spi_xfer_in_progress =3D false; + + if (!iter) { + ret =3D pcim_enable_device(pdev); + if (ret) + return -ENOMEM; + + ret =3D pci_request_regions(pdev, DRV_NAME); + if (ret) + return -ENOMEM; + + spi_bus->reg_base =3D pcim_iomap(pdev, 0, pci_resource_len(pdev, 0)); + if (!spi_bus->reg_base) { + ret =3D -EINVAL; + goto error; + } + + ret =3D pci_alloc_irq_vectors(pdev, hw_inst_cnt, hw_inst_cnt, + PCI_IRQ_ALL_TYPES); + if (ret < 0) { + dev_err(&pdev->dev, "Error allocating MSI vectors\n"); + goto error; + } + + init_completion(&spi_sub_ptr->spi_xfer_done); + /* Initialize Interrupts - SPI_INT */ + regval =3D readl(spi_bus->reg_base + + SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); + regval &=3D ~SPI_INTR; + writel(regval, spi_bus->reg_base + + SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); + spi_sub_ptr->irq =3D pci_irq_vector(pdev, 0); + + ret =3D devm_request_irq(&pdev->dev, spi_sub_ptr->irq, + pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS, + pci_name(pdev), spi_sub_ptr); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to request irq : %d", + spi_sub_ptr->irq); + ret =3D -ENODEV; + goto error; + } + + /* This register is only applicable for 1st instance */ + regval =3D readl(spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); + if (!only_sec_inst) + regval |=3D (BIT(4)); + else + regval &=3D ~(BIT(4)); + + writel(regval, spi_bus->reg_base + SPI_PCI_CTRL_REG_OFFSET(0)); + } + + spi_sub_ptr->hw_inst =3D start++; + + if (iter =3D=3D 1) { + init_completion(&spi_sub_ptr->spi_xfer_done); + /* Initialize Interrupts - SPI_INT */ + regval =3D readl(spi_bus->reg_base + + SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); + regval &=3D ~SPI_INTR; + writel(regval, spi_bus->reg_base + + SPI_MST_EVENT_MASK_REG_OFFSET(spi_sub_ptr->hw_inst)); + spi_sub_ptr->irq =3D pci_irq_vector(pdev, iter); + ret =3D devm_request_irq(&pdev->dev, spi_sub_ptr->irq, + pci1xxxx_spi_isr, PCI1XXXX_IRQ_FLAGS, + pci_name(pdev), spi_sub_ptr); + if (ret < 0) { + dev_err(&pdev->dev, "Unable to request irq : %d", + spi_sub_ptr->irq); + ret =3D -ENODEV; + goto error; + } + } + + spi_host =3D spi_sub_ptr->spi_host; + spi_host->num_chipselect =3D SPI_CHIP_SEL_COUNT; + spi_host->mode_bits =3D SPI_MODE_0 | SPI_MODE_3 | SPI_RX_DUAL | + SPI_TX_DUAL | SPI_LOOP; + spi_host->transfer_one =3D pci1xxxx_spi_transfer_one; + spi_host->set_cs =3D pci1xxxx_spi_set_cs; + spi_host->bits_per_word_mask =3D SPI_BPW_MASK(8); + spi_host->max_speed_hz =3D PCI1XXXX_SPI_MAX_CLOCK_HZ; + spi_host->min_speed_hz =3D PCI1XXXX_SPI_MIN_CLOCK_HZ; + spi_host->flags =3D SPI_MASTER_MUST_TX; + spi_master_set_devdata(spi_host, spi_sub_ptr); + ret =3D devm_spi_register_master(dev, spi_host); + if (ret) + goto error; + } + pci_set_drvdata(pdev, spi_bus); + + return 0; + +error: + pci_release_regions(pdev); + return ret; +} + +static struct pci_driver pci1xxxx_spi_driver =3D { + .name =3D DRV_NAME, + .id_table =3D pci1xxxx_spi_pci_id_table, + .probe =3D pci1xxxx_spi_probe, +}; + +module_pci_driver(pci1xxxx_spi_driver); + +MODULE_DESCRIPTION("Microchip Technology Inc. pci1xxxx SPI bus driver"); +MODULE_AUTHOR("Tharun Kumar P"); +MODULE_AUTHOR("Kumaravel Thiagarajan"= ); +MODULE_LICENSE("GPL v2"); --=20 2.25.1 From nobody Mon Apr 6 19:24:13 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 765B9C433F5 for ; Thu, 6 Oct 2022 05:05:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230120AbiJFFFW (ORCPT ); Thu, 6 Oct 2022 01:05:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230080AbiJFFFR (ORCPT ); Thu, 6 Oct 2022 01:05:17 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 938D91758D; Wed, 5 Oct 2022 22:05:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1665032714; x=1696568714; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=r89GP71acqtvT+cSew3Z+ThnfYFOelp8yN2BadEoGLI=; b=KNfCYnTsmncWaEcQGp6bDZ0z/cnmhQDKrQ1ZfXLJ1vKEdedfnuZ1+csg 3x3YWHsM5K33xvQHEYka+HpZqNGb7K75I7E50FGXutzXFyJIu04/38XxJ JbRc/y1GpvTEEtkqJtpuragNRrvihJw91IcAQGMU8Gj0ycF784Np/DYJm UvHOCYSA0lw4k3x9BkkNKoThqZqXJnvRuPN3Y3WBM57QFK0oIobXFIURk iuy6eSHvh+5xr4OV9PC8IrHVklCi1cSQZoNm989mXLwdpUPnJkLLAHuBV HL2qF9oFPXi/ATBuzT7o89Shx0dZXIZnovuRmFNY2s61OjQ9KjetHRG8T g==; X-IronPort-AV: E=Sophos;i="5.95,163,1661842800"; d="scan'208";a="117093016" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Oct 2022 22:05:13 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 5 Oct 2022 22:05:10 -0700 Received: from CHE-LT-UNGSOFTWARE.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 5 Oct 2022 22:05:08 -0700 From: Tharun Kumar P To: CC: , , Subject: [PATCH v2 SPI for-next 2/2] spi: microchip: pci1xxxx: Add suspend and resume support for PCI1XXXX SPI driver Date: Thu, 6 Oct 2022 10:35:14 +0530 Message-ID: <20221006050514.115564-3-tharunkumar.pasumarthi@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006050514.115564-1-tharunkumar.pasumarthi@microchip.com> References: <20221006050514.115564-1-tharunkumar.pasumarthi@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Implement suspend, resume callbacks, store config at suspend and restore config at time of resume Signed-off-by: Tharun Kumar P --- drivers/spi/spi-pci1xxxx.c | 78 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/spi/spi-pci1xxxx.c b/drivers/spi/spi-pci1xxxx.c index 958503a4d911..a31c3b612a43 100644 --- a/drivers/spi/spi-pci1xxxx.c +++ b/drivers/spi/spi-pci1xxxx.c @@ -57,6 +57,9 @@ #define SPI_CHIP_SEL_COUNT 7 #define VENDOR_ID_MCHP 0x1055 =20 +#define SPI_SUSPEND_CONFIG 0x101 +#define SPI_RESUME_CONFIG 0x303 + struct pci1xxxx_spi_internal { u8 hw_inst; bool spi_xfer_in_progress; @@ -383,10 +386,85 @@ static int pci1xxxx_spi_probe(struct pci_dev *pdev, c= onst struct pci_device_id * return ret; } =20 +static void store_restore_config(struct pci1xxxx_spi *spi_ptr, + struct pci1xxxx_spi_internal *spi_sub_ptr, + u8 inst, bool store) +{ + u32 regval; + + if (store) { + regval =3D readl(spi_ptr->reg_base + + SPI_MST_CTL_REG_OFFSET(spi_sub_ptr->hw_inst)); + regval &=3D SPI_MST_CTL_DEVSEL_MASK; + spi_sub_ptr->prev_val.dev_sel =3D (regval >> 25) & 7; + regval =3D readl(spi_ptr->reg_base + + SPI_PCI_CTRL_REG_OFFSET(spi_sub_ptr->hw_inst)); + regval &=3D SPI_MSI_VECTOR_SEL_MASK; + spi_sub_ptr->prev_val.msi_vector_sel =3D (regval >> 4) & 1; + } else { + regval =3D readl(spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst)); + regval &=3D ~SPI_MST_CTL_DEVSEL_MASK; + regval |=3D (spi_sub_ptr->prev_val.dev_sel << 25); + writel(regval, + spi_ptr->reg_base + SPI_MST_CTL_REG_OFFSET(inst)); + writel((spi_sub_ptr->prev_val.msi_vector_sel << 4), + spi_ptr->reg_base + SPI_PCI_CTRL_REG_OFFSET(inst)); + } +} + +static int pci1xxxx_spi_resume(struct device *dev) +{ + struct pci1xxxx_spi *spi_ptr =3D dev_get_drvdata(dev); + struct pci1xxxx_spi_internal *spi_sub_ptr; + u32 regval =3D SPI_RESUME_CONFIG; + u8 iter; + + for (iter =3D 0; iter < spi_ptr->total_hw_instances; iter++) { + spi_sub_ptr =3D spi_ptr->spi_int[iter]; + spi_master_resume(spi_sub_ptr->spi_host); + writel(regval, spi_ptr->reg_base + + SPI_MST_EVENT_MASK_REG_OFFSET(iter)); + + /* Restore config at resume */ + store_restore_config(spi_ptr, spi_sub_ptr, iter, 0); + } + + return 0; +} + +static int pci1xxxx_spi_suspend(struct device *dev) +{ + struct pci1xxxx_spi *spi_ptr =3D dev_get_drvdata(dev); + struct pci1xxxx_spi_internal *spi_sub_ptr; + u32 reg1 =3D SPI_SUSPEND_CONFIG; + u8 iter; + + for (iter =3D 0; iter < spi_ptr->total_hw_instances; iter++) { + spi_sub_ptr =3D spi_ptr->spi_int[iter]; + + while (spi_sub_ptr->spi_xfer_in_progress) + msleep(20); + + /* Store existing config before suspend */ + store_restore_config(spi_ptr, spi_sub_ptr, iter, 1); + spi_master_suspend(spi_sub_ptr->spi_host); + writel(reg1, spi_ptr->reg_base + + SPI_MST_EVENT_MASK_REG_OFFSET(iter)); + } + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(spi_pm_ops, pci1xxxx_spi_suspend, + pci1xxxx_spi_resume); + static struct pci_driver pci1xxxx_spi_driver =3D { .name =3D DRV_NAME, .id_table =3D pci1xxxx_spi_pci_id_table, .probe =3D pci1xxxx_spi_probe, + .driver =3D { + .pm =3D pm_sleep_ptr(&spi_pm_ops), + }, }; =20 module_pci_driver(pci1xxxx_spi_driver); --=20 2.25.1