From nobody Sat Sep 21 11:32:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FE14C433F5 for ; Thu, 6 Oct 2022 04:35:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229886AbiJFEfS (ORCPT ); Thu, 6 Oct 2022 00:35:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229777AbiJFEfO (ORCPT ); Thu, 6 Oct 2022 00:35:14 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BDE4356D7 for ; Wed, 5 Oct 2022 21:35:06 -0700 (PDT) X-UUID: 612e2e2bd02c417587ff21691b56ca06-20221006 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=oeUlVgx+QgZwWz9wCjYV71PSLvTf5NrW0pJ9W294SgA=; b=SlfHEHHwaCAPwhYdq4R97XUehV+hyssq9Bj/yxW6tGK6Y/ZCrwlg8pPl1IaACNrFnsXveEcI91Pkr08xG+20Ws2TqtqJ/HG6R/fYadivcv+g9YgnlRPtvfa3wbu+dC3+TMDo00Qr2bNdh9CjqL5kRr/tz28UGmX6rGrY/8fYbHM=; X-CID-P-RULE: Spam_GS6885AD X-CID-O-INFO: VERSION:1.1.11,REQID:95c7bd7b-3c55-4af7-9fe9-c410187a24a6,IP:0,U RL:0,TC:0,Content:59,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS6885AD,AC TION:quarantine,TS:159 X-CID-INFO: VERSION:1.1.11,REQID:95c7bd7b-3c55-4af7-9fe9-c410187a24a6,IP:0,URL :0,TC:0,Content:59,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_US65DF41,ACTI ON:quarantine,TS:159 X-CID-META: VersionHash:39a5ff1,CLOUDID:948265fe-ee8c-4ff7-afe9-644435e96625,B ulkID:221006123502A2191ENS,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824|801,TC:nil,Content:3,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC: nil,COL:0 X-UUID: 612e2e2bd02c417587ff21691b56ca06-20221006 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1139609805; Thu, 06 Oct 2022 12:35:00 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 6 Oct 2022 12:34:59 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 6 Oct 2022 12:34:58 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu CC: Jassi Brar , Matthias Brugger , , , , , Hsin-Yi Wang , Yongqiang Niu Subject: [PATCH v9, 1/4] mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number Date: Thu, 6 Oct 2022 12:34:53 +0800 Message-ID: <20221006043456.8754-2-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006043456.8754-1-yongqiang.niu@mediatek.com> References: <20221006043456.8754-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use GCE_CTRL_BY_SW definition instead of number Signed-off-by: Yongqiang Niu Reviewed-by: AngeloGioacchino Del Regno --- drivers/mailbox/mtk-cmdq-mailbox.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 9465f9081515..c3cb24f51699 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -38,6 +38,7 @@ #define CMDQ_THR_PRIORITY 0x40 =20 #define GCE_GCTL_VALUE 0x48 +#define GCE_CTRL_BY_SW GENMASK(2, 0) =20 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -129,7 +130,8 @@ static void cmdq_init(struct cmdq *cmdq) =20 WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); if (cmdq->control_by_sw) - writel(0x7, cmdq->base + GCE_GCTL_VALUE); + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i =3D 0; i <=3D CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); --=20 2.25.1 From nobody Sat Sep 21 11:32:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E713C433F5 for ; Thu, 6 Oct 2022 04:35:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229976AbiJFEfc (ORCPT ); Thu, 6 Oct 2022 00:35:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229841AbiJFEfO (ORCPT ); Thu, 6 Oct 2022 00:35:14 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A881B3DF35 for ; Wed, 5 Oct 2022 21:35:08 -0700 (PDT) X-UUID: 33843c57057141f381755673ef51d9ee-20221006 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=PZSUDXKuBX55AkLTuJcDPMFfjbZLwqwhmdsquhnUJDU=; b=D4dvNb3iPfD9WAkk5CncZKibjCFpC5u53BQA4mNaywv+naaOw3oGdsNzXVKY8unJHCDHBAc8rPv4/+N0EIt3jgsae2EzWNriV5Rhj3hQQ+4UsZgbkPpQB3ceQNjJ0oxzh6utFZDe/iVBPjDi2Edbkbfxr5zdsEZIqZvjnR8Or8Y=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:1cbe79aa-3d30-4794-acb3-f7f79e1c895c,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:100 X-CID-INFO: VERSION:1.1.11,REQID:1cbe79aa-3d30-4794-acb3-f7f79e1c895c,IP:0,URL :0,TC:0,Content:0,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTIO N:quarantine,TS:100 X-CID-META: VersionHash:39a5ff1,CLOUDID:ffe0ab85-5312-4339-9a65-dc27c4b243b8,B ulkID:2210061235023TDK31LU,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil, COL:0 X-UUID: 33843c57057141f381755673ef51d9ee-20221006 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 852628176; Thu, 06 Oct 2022 12:35:00 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 6 Oct 2022 12:34:59 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 6 Oct 2022 12:34:59 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu CC: Jassi Brar , Matthias Brugger , , , , , Hsin-Yi Wang , Yongqiang Niu Subject: [PATCH v9, 2/4] mailbox: mtk-cmdq: add gce software ddr enable private data Date: Thu, 6 Oct 2022 12:34:54 +0800 Message-ID: <20221006043456.8754-3-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006043456.8754-1-yongqiang.niu@mediatek.com> References: <20221006043456.8754-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" if gce work control by software, we need set software enable for MT8186 Soc there is a handshake flow between gce and ddr hardware, if not set ddr enable flag of gce, ddr will fall into idle mode, then gce instructions will not process done. we need set this flag of gce to tell ddr when gce is idle or busy controlled by software flow. 0x48[2:0] means control by software 0x48[18:16] means ddr enable 0x48[2:0] is pre-condition of 0x48[18:16]. if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same time. and only these bits is useful, other bits is useless bits Signed-off-by: Yongqiang Niu --- drivers/mailbox/mtk-cmdq-mailbox.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index c3cb24f51699..04eb44d89119 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -39,6 +39,7 @@ =20 #define GCE_GCTL_VALUE 0x48 #define GCE_CTRL_BY_SW GENMASK(2, 0) +#define GCE_DDR_EN GENMASK(18, 16) =20 #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 @@ -81,6 +82,7 @@ struct cmdq { bool suspended; u8 shift_pa; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; =20 @@ -88,6 +90,7 @@ struct gce_plat { u32 thread_nr; u8 shift; bool control_by_sw; + bool sw_ddr_en; u32 gce_num; }; =20 @@ -132,6 +135,9 @@ static void cmdq_init(struct cmdq *cmdq) if (cmdq->control_by_sw) writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); =20 + if (cmdq->sw_ddr_en) + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i =3D 0; i <=3D CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); @@ -545,6 +551,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr =3D plat_data->thread_nr; cmdq->shift_pa =3D plat_data->shift; cmdq->control_by_sw =3D plat_data->control_by_sw; + cmdq->sw_ddr_en =3D plat_data->sw_ddr_en; cmdq->gce_num =3D plat_data->gce_num; cmdq->irq_mask =3D GENMASK(cmdq->thread_nr - 1, 0); err =3D devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, --=20 2.25.1 From nobody Sat Sep 21 11:32:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0004C433F5 for ; Thu, 6 Oct 2022 04:35:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229805AbiJFEf2 (ORCPT ); Thu, 6 Oct 2022 00:35:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229565AbiJFEfO (ORCPT ); Thu, 6 Oct 2022 00:35:14 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BCF733E1D for ; Wed, 5 Oct 2022 21:35:05 -0700 (PDT) X-UUID: 66c3dbb9af434f24ae32bfb86ecd6600-20221006 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=U/TQbV5m104HfRcT9S9HCCZ0p5prmyu9kaPPLbaRReM=; b=ORKzjQc3lUBmt1dwt0lVvyeLPzGA83TML3T762iU+iGFMiQZWmhNTdgaJ9O4+H2QY7AQE6P2hk/Zh8sLAYYAq8RbLGXnwZIinJvOPKmhN2zFOIJTQEpUTuHbiHqgg4xnttVxj3aMNjTkbVSV2SXVt2nEmtgPGDfjqY6YeH4BSKI=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11,REQID:1f5adf4c-3bd9-4e16-abf5-18289f5e42a0,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1,CLOUDID:65e1ab85-5312-4339-9a65-dc27c4b243b8,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 66c3dbb9af434f24ae32bfb86ecd6600-20221006 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 184232541; Thu, 06 Oct 2022 12:35:02 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 6 Oct 2022 12:35:00 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 6 Oct 2022 12:35:00 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu CC: Jassi Brar , Matthias Brugger , , , , , Hsin-Yi Wang , Yongqiang Niu Subject: [PATCH v9, 3/4] mailbox: mtk-cmdq: add gce ddr enable support flow Date: Thu, 6 Oct 2022 12:34:55 +0800 Message-ID: <20221006043456.8754-4-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006043456.8754-1-yongqiang.niu@mediatek.com> References: <20221006043456.8754-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" add gce ddr enable control flow when gce suspend/resume when all cmdq instruction task has been processed done, we need set this gce ddr enable to disable status to tell cmdq hardware gce there is none task need process, and the hardware can go into idle mode and no access ddr anymore, then the spm can go into suspend. the original issue is gce still access ddr when cmdq suspend function call, but there is no task run. so, we need control gce access ddr with this flow. when cmdq suspend function, there is no task need process, we can disable gce access ddr, to make sure system go into suspend success. Signed-off-by: Yongqiang Niu Reviewed-by: AngeloGioacchino Del Regno --- drivers/mailbox/mtk-cmdq-mailbox.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 04eb44d89119..2db82ff838ed 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -94,6 +94,18 @@ struct gce_plat { u32 gce_num; }; =20 +static void cmdq_sw_ddr_enable(struct cmdq *cmdq, bool enable) +{ + WARN_ON(clk_bulk_enable(cmdq->gce_num, cmdq->clocks)); + + if (enable) + writel(GCE_DDR_EN | GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + else + writel(GCE_CTRL_BY_SW, cmdq->base + GCE_GCTL_VALUE); + + clk_bulk_disable(cmdq->gce_num, cmdq->clocks); +} + u8 cmdq_get_shift_pa(struct mbox_chan *chan) { struct cmdq *cmdq =3D container_of(chan->mbox, struct cmdq, mbox); @@ -319,6 +331,9 @@ static int cmdq_suspend(struct device *dev) if (task_running) dev_warn(dev, "exist running task(s) in suspend\n"); =20 + if (cmdq->sw_ddr_en) + cmdq_sw_ddr_enable(cmdq, false); + clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); =20 return 0; @@ -330,6 +345,10 @@ static int cmdq_resume(struct device *dev) =20 WARN_ON(clk_bulk_prepare(cmdq->gce_num, cmdq->clocks)); cmdq->suspended =3D false; + + if (cmdq->sw_ddr_en) + cmdq_sw_ddr_enable(cmdq, true); + return 0; } =20 @@ -337,6 +356,9 @@ static int cmdq_remove(struct platform_device *pdev) { struct cmdq *cmdq =3D platform_get_drvdata(pdev); =20 + if (cmdq->sw_ddr_en) + cmdq_sw_ddr_enable(cmdq, false); + clk_bulk_unprepare(cmdq->gce_num, cmdq->clocks); return 0; } --=20 2.25.1 From nobody Sat Sep 21 11:32:43 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FC50C433FE for ; Thu, 6 Oct 2022 04:35:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230037AbiJFEfg (ORCPT ); Thu, 6 Oct 2022 00:35:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55554 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229846AbiJFEfP (ORCPT ); Thu, 6 Oct 2022 00:35:15 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A5FD43631 for ; Wed, 5 Oct 2022 21:35:09 -0700 (PDT) X-UUID: 8a7f8ed27c3e4409a262bf1a7199ea9c-20221006 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=NZWxLXQ17WP/R85ToaTl8qMRc3BR0Gqh4CJuSbllU70=; b=moe5lA8diHPnZ7FYG6r0AuWtr6ilTwNWeAo6hMBEU3WJN4aLefvGfLp8oovX45GcCf4zZiUdbQwQJwodNrbPVSBRhrkouP5xMe9/o4Lt/vK284MowKrpmrkPkGSly3TymO/14C5F8WkaffYV5p9j+YfNxZcjM0fY6Eyj13lc5IU=; X-CID-P-RULE: Spam_GS6885AD X-CID-O-INFO: VERSION:1.1.11,REQID:2ef9e254-bc25-448f-9f6a-7a707b326b43,IP:0,U RL:0,TC:0,Content:33,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS6885AD,AC TION:quarantine,TS:133 X-CID-INFO: VERSION:1.1.11,REQID:2ef9e254-bc25-448f-9f6a-7a707b326b43,IP:0,URL :0,TC:0,Content:33,EDM:0,RT:0,SF:100,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:133 X-CID-META: VersionHash:39a5ff1,CLOUDID:458365fe-ee8c-4ff7-afe9-644435e96625,B ulkID:221006123505MWBZXWNQ,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:3,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil, COL:0 X-UUID: 8a7f8ed27c3e4409a262bf1a7199ea9c-20221006 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 327454711; Thu, 06 Oct 2022 12:35:02 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 6 Oct 2022 12:35:01 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 6 Oct 2022 12:35:00 +0800 From: Yongqiang Niu To: CK Hu , Chun-Kuang Hu CC: Jassi Brar , Matthias Brugger , , , , , Hsin-Yi Wang , Yongqiang Niu Subject: [PATCH v9, 4/4] mailbox: mtk-cmdq: add MT8186 support Date: Thu, 6 Oct 2022 12:34:56 +0800 Message-ID: <20221006043456.8754-5-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221006043456.8754-1-yongqiang.niu@mediatek.com> References: <20221006043456.8754-1-yongqiang.niu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" add MT8186 cmdq support Signed-off-by: Yongqiang Niu Reviewed-by: AngeloGioacchino Del Regno --- drivers/mailbox/mtk-cmdq-mailbox.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 2db82ff838ed..98eed8d22688 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -691,9 +691,18 @@ static const struct gce_plat gce_plat_v6 =3D { .gce_num =3D 2 }; =20 +static const struct gce_plat gce_plat_v7 =3D { + .thread_nr =3D 24, + .shift =3D 3, + .control_by_sw =3D true, + .sw_ddr_en =3D true, + .gce_num =3D 1 +}; + static const struct of_device_id cmdq_of_ids[] =3D { {.compatible =3D "mediatek,mt8173-gce", .data =3D (void *)&gce_plat_v2}, {.compatible =3D "mediatek,mt8183-gce", .data =3D (void *)&gce_plat_v3}, + {.compatible =3D "mediatek,mt8186-gce", .data =3D (void *)&gce_plat_v7}, {.compatible =3D "mediatek,mt6779-gce", .data =3D (void *)&gce_plat_v4}, {.compatible =3D "mediatek,mt8192-gce", .data =3D (void *)&gce_plat_v5}, {.compatible =3D "mediatek,mt8195-gce", .data =3D (void *)&gce_plat_v6}, --=20 2.25.1