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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:46 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 01/10] dt-bindings: pwm: Document Synopsys DesignWare snps,pwm-dw-apb-timers-pwm2 Date: Wed, 5 Oct 2022 23:12:33 +0100 Message-Id: <20221005221242.470734-2-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add documentation for the bindings for Synopsys' DesignWare PWM block as we will be adding DT/platform support to the Linux driver soon. Signed-off-by: Ben Dooks Reviewed-by: Krzysztof Kozlowski --- v5: - fixed order of properties - corrected clock to two items v4: - fixed typos, added reg v3: - add description and example - merge the snps,pwm-number into this patch - rename snps,pwm to snps,dw-apb-timers-pwm2 v2: - fix #pwm-cells to be 3 - fix indentation and ordering issues --- .../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/snps,dw-apb-timer= s-pwm2.yaml diff --git a/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.= yaml b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml new file mode 100644 index 000000000000..9aabdb373afa --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DW-APB timers PWM controller + +maintainers: + - Ben Dooks + +description: + This describes the DesignWare APB timers module when used in the PWM + mode. The IP core can be generated with various options which can + control the functionality, the number of PWMs available and other + internal controls the designer requires. + + The IP block has a version register so this can be used for detection + instead of having to encode the IP version number in the device tree + comaptible. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: snps,dw-apb-timers-pwm2 + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Interface bus clock + - description: PWM reference clock + + clock-names: + items: + - const: bus + - const: timer + + snps,pwm-number: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [1, 2, 3, 4, 5, 6, 7, 8] + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + pwm: pwm@180000 { + compatible =3D "snps,dw-apb-timers-pwm2"; + reg =3D <0x180000 0x200>; + #pwm-cells =3D <3>; + clocks =3D <&bus>, <&timer>; + clock-names =3D "bus", "timer"; + }; --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2CC79C433F5 for ; Wed, 5 Oct 2022 22:13:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229676AbiJEWNB (ORCPT ); Wed, 5 Oct 2022 18:13:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229581AbiJEWMu (ORCPT ); Wed, 5 Oct 2022 18:12:50 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D8EA83074 for ; Wed, 5 Oct 2022 15:12:49 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id v130-20020a1cac88000000b003bcde03bd44so1732190wme.5 for ; Wed, 05 Oct 2022 15:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=JfTi7Q4REwIMcUKxyjals5QXXaBkiKSjiHGfvVJiUh9pJA4nKbMPndrv+Uf4On0HUT yeQodr0ZlNeWkEZ2aDPOZmClKlQV/AETC/C6IfCDGJ0nh6enqCN6Yxj1kypNEUsGgZfJ Lcnjnfv7aCTF7jK/BbuIPr6nKeL8ckv1n+MDyNvQjwT2ixTehdUxZL30c312cMrSMpS1 7frz1ihgRrLgKa9xAHXf8HlbKmG4rR4sn31ZnB5EthkL91DBwcwDih0OwDxOimucmWzm Z6P3laNOC1KL9cK6Iy3BzQVkbDqXsuuOXa6TM85ChIRXlzZs/IZL643iQLZV/ivv9vKt bNww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=pOKidRu+yxajr1o110Z9rt8XpJh4zLytmd2a75/kdaY=; b=zRPgETCdFGKnWBPPgIMeNgkvOU8d0YFPmviBjvUr3NIWPrPVWfdTHm3lAqW8kanY2M eQcZRY1XFcULu6XvgLqYHJTV3h87GTPGeK6IJu2d2vX4FDh6/0Jy7AwpUroqylKjM8uS WwgT7585q8QuxXAYLKX/8sx6Mj7pQeJJrcm5JUGp/uOZP/Q7Ru2CayHEgI6CoslyURUZ qwkQ2ZU2G7fDkddK+rLHypkE8E0Ze1X+x+tJbnQHZ7/EhFL1o/XpJgSmfj8GE4Jmb5F1 8kLBnm6+HicA9Wmaj0MjbtKbEEPhxnal5CsGvRQMLCo+AN2D6G22xbbcKd/zbe5He+RJ kH5Q== X-Gm-Message-State: ACrzQf2p3KXZfAruBg+JfOQOnZaoPZhtMUDh5rhq5drbhW1oQxeD5tbj OuO+7Untu5IgXM7k/C0Z1cmAUQ== X-Google-Smtp-Source: AMsMyM65hJh6hJqULT8KOjLg6DEY1ebIrG7h+/neOAH34aclmhLTi/wYs2S1O91+peqAakpAjYVZOg== X-Received: by 2002:a05:600c:1d11:b0:3b4:7644:b788 with SMTP id l17-20020a05600c1d1100b003b47644b788mr1107538wms.114.1665007968129; Wed, 05 Oct 2022 15:12:48 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:47 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 02/10] pwm: dwc: allow driver to be built with COMPILE_TEST Date: Wed, 5 Oct 2022 23:12:34 +0100 Message-Id: <20221005221242.470734-3-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Allow dwc driver to be built with COMPILE_TEST should allow better coverage when build testing. Signed-off-by: Ben Dooks --- v4: - moved to earlier in the series v3: - add HAS_IOMEM depdency for compile testing --- drivers/pwm/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 60d13a949bc5..3f3c53af4a56 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -176,7 +176,8 @@ config PWM_CROS_EC =20 config PWM_DWC tristate "DesignWare PWM Controller" - depends on PCI + depends on PCI || COMPILE_TEST + depends on HAS_IOMEM help PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. =20 --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57AE9C433F5 for ; Wed, 5 Oct 2022 22:13:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229734AbiJEWNF (ORCPT ); Wed, 5 Oct 2022 18:13:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229586AbiJEWMu (ORCPT ); Wed, 5 Oct 2022 18:12:50 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7541483058 for ; Wed, 5 Oct 2022 15:12:49 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id a10so15491413wrm.12 for ; Wed, 05 Oct 2022 15:12:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=VSxSa3rea769WcJeCZBGNkJoHT2kIKG/V+nPY89aK3CfQRIT8MMN9BaN/doC1InOFa 6fqL0v1UA5Z1Acp4mdOx9NboMCQHfhaEm34AyEe7VMrz+jMoHYo/gRv0hV6d/1NP/Lfa 7TZ873O/ppGZlkmfFJ0Rz37fORUXoonDeMwOPTsFEfpdmTkrm6g4UtvpVta6Kwywqaj9 XLTZtQf04xQgzJUAyvsCDSmHWXM5oM+kKGR9CAomBI3BRyFYdmROqMgSX3DbMRDKkNQ6 FEUEUTBE+Y+0fAeFqozz5OKBhftilOsww2VBKbiW1cpz5IQXNu3SyNqHz1qIKzZGKRuH wDng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=BEOpRioXienSDDf6vjruAkPlsDKDhUNbn1dmZioZ4X4=; b=IoNLGM3UmjVg2QUqOIKha6JZe6TeM7Rvqd2IJDKBRe2YB2j+TzWsYfHSPJdnHcuY+Q H2CMu5FawN+TB/5/SUKNDq1yKUa7Ja5IGL1hB5iXFlXVRlu2uZtEikxleCXMFDPxGPa7 TK9jvLqW19csaxHhtQpHebtM69CZTN9t1KvYmuHxq2OSbxt2PjynD+7BfWCL1FRH0eZ0 hvO+66KUw3sH0b8iazd+32zNjhy7fSOkrIOtfinw5nUs3pz5NQmnut8+kGgyvO5nVWJy RUj+BAuS0prtYrp9mQ/yq4BCPocmwlW8x3NGF/H7DKMes5TiwyxXZoICburCZXmjlw8m 004g== X-Gm-Message-State: ACrzQf0rk3EGshWQ2LIJDeun+Q9Kxmmb3Vcqnu4zjh9lKBKDYH24ln9u puien5GW0au7tagBwrSmRCz75Q== X-Google-Smtp-Source: AMsMyM482vi2maJSOPEx3SNNXxYZFc6clxuujhf+yB8wdjpjq6Wh4uT014rkevtaTy87y9llX+CB5A== X-Received: by 2002:a5d:428c:0:b0:22e:5d4e:c71e with SMTP id k12-20020a5d428c000000b0022e5d4ec71emr1016893wrq.19.1665007969099; Wed, 05 Oct 2022 15:12:49 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:48 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 03/10] pwm: dwc: change &pci->dev to dev in probe Date: Wed, 5 Oct 2022 23:12:35 +0100 Message-Id: <20221005221242.470734-4-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The dwc_pwm_probe() assignes dev to be &pci->dev but then uses &pci->dev throughout the function. Change these all to the be 'dev' variable to make lines shorter. Signed-off-by: Ben Dooks Acked-by: Uwe Kleine-K=C3=B6nig --- drivers/pwm/pwm-dwc.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 7568300bb11e..c706ef9a7ba1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -202,14 +202,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const s= truct pci_device_id *id) struct dwc_pwm *dwc; int ret; =20 - dwc =3D devm_kzalloc(&pci->dev, sizeof(*dwc), GFP_KERNEL); + dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); if (!dwc) return -ENOMEM; =20 ret =3D pcim_enable_device(pci); if (ret) { - dev_err(&pci->dev, - "Failed to enable device (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); return ret; } =20 @@ -217,14 +216,13 @@ static int dwc_pwm_probe(struct pci_dev *pci, const s= truct pci_device_id *id) =20 ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); if (ret) { - dev_err(&pci->dev, - "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); return ret; } =20 dwc->base =3D pcim_iomap_table(pci)[0]; if (!dwc->base) { - dev_err(&pci->dev, "Base address missing\n"); + dev_err(dev, "Base address missing\n"); return -ENOMEM; } =20 --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E44CAC433F5 for ; Wed, 5 Oct 2022 22:13:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229766AbiJEWNI (ORCPT ); Wed, 5 Oct 2022 18:13:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229612AbiJEWMx (ORCPT ); Wed, 5 Oct 2022 18:12:53 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E347483200 for ; Wed, 5 Oct 2022 15:12:51 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id o5so11611041wms.1 for ; Wed, 05 Oct 2022 15:12:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=3SdKoJam1KKdYl+ZS8hBn9qpHaB89KQkUoXzOnMw6QQ=; b=CwxRItFiSyGkSsVk03I7odc5pM54LdjFqGNovlI4mDdFuQud975xo1ZjzOe2Tb1Hdn V0Yx+6mj4qnKLaLmhOL9CZodhkZjQqjYF9QS63Zg5n/pKEItDyJhgowMN4IMJoKuclH9 Btl8W2jz10SoFTXSKHP6lXB5M7Bg+asVc0M4z+I8o8TRjTwkyuWeavONqCZLqbBAZiid ByPKUCPe314HaigLiCBpHBU5U/pkRgfe4uV9yA4W9ORFA1zrkOFEiOp+U3ADWo55kVcu ggq96TIzVLPo70QeSxfNC0SzkuI1xG1DW8kYEZaoNAgX9I72gS41m6X24w3wq6H/lHtj zLCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=3SdKoJam1KKdYl+ZS8hBn9qpHaB89KQkUoXzOnMw6QQ=; b=rbOw0k5f/pQHHSx4dFxsdVJGGkXY4aRi2mWtuagH1LxDGONYJjEOg6dN0z6LxFdu3I T6KVUMe1Sn9vJpNYUTiy0Umbg9GpXV2eNFLJNrXVo1XdETmXekc2GBF2h9cWKP8evpCC B8teEaak9VnpffG+vIqOoB//9kjumjgswo4w6Ca1bKDK0hPqgOOvuPS0V6IPwywNAgyZ MH27UINNP2QvbnqSLVRgieojV+uUBFJkUFeIZc+/zZAcDREYeGN5eGgVFFK1+SwKwxVI QPqjvvlGbGqy1VR9vN1q2vvp5ja6K07ke6q+Xz7tZCzzegKDHNVgll6UUGmcKtLhpm4s XjBA== X-Gm-Message-State: ACrzQf3YYleCyL+EpFOK0YMYczm52OF7o4QxxKdDrxavR2VoZkyHj7R7 NEckgPPzB51RBqwCeHwLhTVaTA== X-Google-Smtp-Source: AMsMyM7Wbls2cncHeDTU+qrNRSHvee+oD9v+FEyIh3tQFDImWYF5CdvGzSyiNAUur29eVaQLYjAI2Q== X-Received: by 2002:a7b:c3d4:0:b0:3be:88e:2265 with SMTP id t20-20020a7bc3d4000000b003be088e2265mr4681373wmj.163.1665007970185; Wed, 05 Oct 2022 15:12:50 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:49 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 04/10] pwm: dwc: move memory alloc to own function Date: Wed, 5 Oct 2022 23:12:36 +0100 Message-Id: <20221005221242.470734-5-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for adding other bus support, move the allocation of the pwm struct out of the main driver code. Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index c706ef9a7ba1..61f11e0a9319 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -196,13 +196,29 @@ static const struct pwm_ops dwc_pwm_ops =3D { .owner =3D THIS_MODULE, }; =20 +static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +{ + struct dwc_pwm *dwc; + + dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return NULL; + + dwc->chip.dev =3D dev; + dwc->chip.ops =3D &dwc_pwm_ops; + dwc->chip.npwm =3D DWC_TIMERS_TOTAL; + + dev_set_drvdata(dev, dwc); + return dwc; +} + static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) { struct device *dev =3D &pci->dev; struct dwc_pwm *dwc; int ret; =20 - dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); + dwc =3D dwc_pwm_alloc(dev); if (!dwc) return -ENOMEM; =20 @@ -226,12 +242,6 @@ static int dwc_pwm_probe(struct pci_dev *pci, const st= ruct pci_device_id *id) return -ENOMEM; } =20 - pci_set_drvdata(pci, dwc); - - dwc->chip.dev =3D dev; - dwc->chip.ops =3D &dwc_pwm_ops; - dwc->chip.npwm =3D DWC_TIMERS_TOTAL; - ret =3D pwmchip_add(&dwc->chip); if (ret) return ret; --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8DEE0C433FE for ; Wed, 5 Oct 2022 22:13:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229774AbiJEWNL (ORCPT ); Wed, 5 Oct 2022 18:13:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39104 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229514AbiJEWMx (ORCPT ); Wed, 5 Oct 2022 18:12:53 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03DDF8306F for ; Wed, 5 Oct 2022 15:12:53 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id a3so9830wrt.0 for ; Wed, 05 Oct 2022 15:12:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=JVsjMt/QqWDQIkbN9ThQA44X6Q8M6+q3vjfLdgd5aDk=; b=lns6fCmSp1PmCoJBnYkhAb1nQxyf69647ZdqX1ZEZsl0yxpJhWobRqY0R/rhtzgEZj KVIoTT60Tv0pIZmmnD9m1I195DBzHzTEMOxrAoWfI5nItLrKzGvaTTVo4TuGA8A/bwgI FvgrWLjPE6WSNO7zMIcJD1Dbk2dH4yKS87CRB2Q6aHz4NUP1/OaW4s0QkcFpco4tZKUn 3GDVX64VGS8OPsMDf9BW8bF+ncgYPOJeZIQvAnnJffEuG8OHg/E+24nQs13P9sDbbPSC 41g6QzIOh713i2HKRk1UEbxwKUrzreIA0Jfr0gtOGlvY1S1Niqt7u2/jWKOn3DhpeI53 cZSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=JVsjMt/QqWDQIkbN9ThQA44X6Q8M6+q3vjfLdgd5aDk=; b=vPRDZvTQjLIRxmFKJjCyGksGqXkjR+ut3FhvPLT55qd9LkM28exjO/3x6KaP/a4RIH hKnHcAIAX7bwlR+YxpDELTd1Iq7Dy8SPVrR26cACZDpEhdzX1rDVhRiSk64jZsszzOwO SPZEVr8yNelmKv7Dl2mWeH9XKBLJGnoD5lvBhePcrcWqmshM+FkkLmQ5EGrsugCJilHM cSqrbrGPaqhuMz5wowk56S6evxROGep5rOwxdCRmQBylJq6o1V6cOXb/wSgDI0WAJwHx z2uNKsFITxwkrZ0LZymNdVWruiKKMkbMBEFheup/rsXUpOQDrxegeVU2oJ55HNT3LEHP /HUw== X-Gm-Message-State: ACrzQf2cRB12CygH+segfmU+BEtXSIxt7btVrb6kiialzWrZTt6i9GEc 6uGrAawPNzS7yiUWK6YpWkbK0Q== X-Google-Smtp-Source: AMsMyM64144/H+SMQ4cld0JX811x0IsidPU2IR5ZlGuFZbVWusIQE0gBZpA9vl7SFsyXTQungnHxew== X-Received: by 2002:adf:eacf:0:b0:22e:369:2081 with SMTP id o15-20020adfeacf000000b0022e03692081mr1071029wrn.339.1665007971560; Wed, 05 Oct 2022 15:12:51 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:50 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 05/10] pwm: dwc: use devm_pwmchip_add Date: Wed, 5 Oct 2022 23:12:37 +0100 Message-Id: <20221005221242.470734-6-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Use devm_pwmchip_add() to add the pwm chip to avoid having to manually remove it (useful for the next patch which adds the platform-device support). Signed-off-by: Ben Dooks --- drivers/pwm/pwm-dwc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 61f11e0a9319..56cde9da2c0e 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -242,7 +242,7 @@ static int dwc_pwm_probe(struct pci_dev *pci, const str= uct pci_device_id *id) return -ENOMEM; } =20 - ret =3D pwmchip_add(&dwc->chip); + ret =3D devm_pwmchip_add(dev, &dwc->chip); if (ret) return ret; =20 @@ -254,12 +254,8 @@ static int dwc_pwm_probe(struct pci_dev *pci, const st= ruct pci_device_id *id) =20 static void dwc_pwm_remove(struct pci_dev *pci) { - struct dwc_pwm *dwc =3D pci_get_drvdata(pci); - pm_runtime_forbid(&pci->dev); pm_runtime_get_noresume(&pci->dev); - - pwmchip_remove(&dwc->chip); } =20 #ifdef CONFIG_PM_SLEEP --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF710C433FE for ; Wed, 5 Oct 2022 22:13:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229786AbiJEWNR (ORCPT ); Wed, 5 Oct 2022 18:13:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39114 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229496AbiJEWM4 (ORCPT ); Wed, 5 Oct 2022 18:12:56 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CB1483074 for ; Wed, 5 Oct 2022 15:12:54 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id u10so27714183wrq.2 for ; Wed, 05 Oct 2022 15:12:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=jHgpM9msku+bALl651QUnjaXOaBmDTjcFSZrhAOsAIw=; b=ezLldVzIELuh9GKUtqN4sVyuwnjPmYYBPXCfkjBKE/FsxomHUgP+7BpBb+1UpnpJvz M6fmKDq8I4mASuhtpimGdyHbk7wh5x8I6XLBDsY7D7gmYFFU/8/gSFrmCSTvBkMrEuvO +aGKVzCO5JwcKPOrFXAC7iMCdoNoxicOZivO6b88si/p1fK8RRdvGspAOcONCFI6njf1 xFlu4XdTF3mvs/TxUMgui26yDOAjJEmUUALq6WvGnbG0i7hXQHqMXAkApAdaTODifg5b as6D+XqGhKBJk+pYvyV3tTC0qnl1XhvhaYNvc48XQpGRMMRt1CC0da/wvpcNrnBwR1gh +arQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=jHgpM9msku+bALl651QUnjaXOaBmDTjcFSZrhAOsAIw=; b=LrTLKEzDeSRrDKkbkRd8FOAeo52UCEsDK+69rcJ2AEDr45/tdxnmx7PuJbj3Ipbrm1 xvZLyWtJ2pRHAHQeOEDTBKypO9dhC65oBCJUFcZa9E6OoAK/vJUBh1bZuvgPbTjsS0Nr rSkDdNbUFlgfY4g/ecNsn156d6T/MKmxlIBPVqX1thSe8nLQhqtbqxaa5z+A7O2XXrbm zX7vN9TzO+IyV9+dRKdqq3BCfKVlfpv+5yxr+V5sWRd0+PRVeh0R1t4fgdJ/1AYYTJ+N gR7SOPJOokG5RF/3ak47LkYIc9R4KtLMZGvpsmnqgj94fyE4Ilwo3T+fcDCKZHyjxJ2W Rn+w== X-Gm-Message-State: ACrzQf3PGPi0gAhqeoVPFNp7QsV/t93Y5YuJw2w0vDxvDmzsfcC+ZiG/ QG0NJUqtOyKhIcISuvVe+8dCWg== X-Google-Smtp-Source: AMsMyM48dy7nhBw1QhwHlThXoLMpumSZYnAYmoM8IiCvXW8DPZmEy/BLepUg+NN9JWNUYKze2OPQHw== X-Received: by 2002:adf:fd4a:0:b0:22d:d3aa:e004 with SMTP id h10-20020adffd4a000000b0022dd3aae004mr1039755wrs.173.1665007972657; Wed, 05 Oct 2022 15:12:52 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:52 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 06/10] pwm: dwc: split pci out of core driver Date: Wed, 5 Oct 2022 23:12:38 +0100 Message-Id: <20221005221242.470734-7-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Moving towards adding non-pci support for the driver, move the pci parts out of the core into their own module. This is partly due to the module_driver() code only being allowed once in a module and also to avoid a number of #ifdef if we build a single file in a system without pci support. Signed-off-by: Ben Dooks --- v4: - removed DWC_PERIOD_NS as not needed --- drivers/pwm/Kconfig | 14 +++- drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-pci.c | 133 ++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.c | 158 +------------------------------------- drivers/pwm/pwm-dwc.h | 57 ++++++++++++++ 5 files changed, 206 insertions(+), 157 deletions(-) create mode 100644 drivers/pwm/pwm-dwc-pci.c create mode 100644 drivers/pwm/pwm-dwc.h diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 3f3c53af4a56..a9f1c554db2b 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -175,15 +175,23 @@ config PWM_CROS_EC Controller. =20 config PWM_DWC - tristate "DesignWare PWM Controller" - depends on PCI || COMPILE_TEST + tristate "DesignWare PWM Controller core" depends on HAS_IOMEM help - PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + PWM driver for Synopsys DWC PWM Controller. =20 To compile this driver as a module, choose M here: the module will be called pwm-dwc. =20 +config PWM_DWC_PCI + tristate "DesignWare PWM Controller core" + depends on PWM_DWC && HAS_IOMEM && PCI + help + PWM driver for Synopsys DWC PWM Controller attached to a PCI bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-pci. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 7bf1a29f02b8..a70d36623129 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o +obj-$(CONFIG_PWM_DWC_PCI) +=3D pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) +=3D pwm-fsl-ftm.o obj-$(CONFIG_PWM_HIBVT) +=3D pwm-hibvt.o diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c new file mode 100644 index 000000000000..2213d0e7f3c8 --- /dev/null +++ b/drivers/pwm/pwm-dwc-pci.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver (PCI part) + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + * + * Limitations: + * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and= low + * periods are one or more input clock periods long. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) +{ + struct device *dev =3D &pci->dev; + struct dwc_pwm *dwc; + int ret; + + dwc =3D dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + ret =3D pcim_enable_device(pci); + if (ret) { + dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); + return ret; + } + + pci_set_master(pci); + + ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); + if (ret) { + dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); + return ret; + } + + dwc->base =3D pcim_iomap_table(pci)[0]; + if (!dwc->base) { + dev_err(dev, "Base address missing\n"); + return -ENOMEM; + } + + ret =3D devm_pwmchip_add(dev, &dwc->chip); + if (ret) + return ret; + + pm_runtime_put(dev); + pm_runtime_allow(dev); + + return 0; +} + +static void dwc_pwm_remove(struct pci_dev *pci) +{ + pm_runtime_forbid(&pci->dev); + pm_runtime_get_noresume(&pci->dev); +} + +#ifdef CONFIG_PM_SLEEP +static int dwc_pwm_suspend(struct device *dev) +{ + struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); + int i; + + for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { + if (dwc->chip.pwms[i].state.enabled) { + dev_err(dev, "PWM %u in use by consumer (%s)\n", + i, dwc->chip.pwms[i].label); + return -EBUSY; + } + dwc->ctx[i].cnt =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); + dwc->ctx[i].cnt2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); + dwc->ctx[i].ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); + } + + return 0; +} + +static int dwc_pwm_resume(struct device *dev) +{ + struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); + struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); + int i; + + for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { + dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); + dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); + } + + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); + +static const struct pci_device_id dwc_pwm_id_table[] =3D { + { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ + { } /* Terminating Entry */ +}; +MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); + +static struct pci_driver dwc_pwm_driver =3D { + .name =3D "pwm-dwc", + .probe =3D dwc_pwm_probe, + .remove =3D dwc_pwm_remove, + .id_table =3D dwc_pwm_id_table, + .driver =3D { + .pm =3D &dwc_pwm_pm_ops, + }, +}; + +module_pci_driver(dwc_pwm_driver); + +MODULE_AUTHOR("Felipe Balbi (Intel)"); +MODULE_AUTHOR("Jarkko Nikula "); +MODULE_AUTHOR("Raymond Tan "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 56cde9da2c0e..90a8ae1252a1 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -1,16 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 /* - * DesignWare PWM Controller driver + * DesignWare PWM Controller driver core * * Copyright (C) 2018-2020 Intel Corporation * * Author: Felipe Balbi (Intel) * Author: Jarkko Nikula * Author: Raymond Tan - * - * Limitations: - * - The hardware cannot generate a 0 % or 100 % duty cycle. Both high and= low - * periods are one or more input clock periods long. */ =20 #include @@ -21,51 +17,7 @@ #include #include =20 -#define DWC_TIM_LD_CNT(n) ((n) * 0x14) -#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) -#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) -#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) -#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) -#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) - -#define DWC_TIMERS_INT_STS 0xa0 -#define DWC_TIMERS_EOI 0xa4 -#define DWC_TIMERS_RAW_INT_STS 0xa8 -#define DWC_TIMERS_COMP_VERSION 0xac - -#define DWC_TIMERS_TOTAL 8 -#define DWC_CLK_PERIOD_NS 10 - -/* Timer Control Register */ -#define DWC_TIM_CTRL_EN BIT(0) -#define DWC_TIM_CTRL_MODE BIT(1) -#define DWC_TIM_CTRL_MODE_FREE (0 << 1) -#define DWC_TIM_CTRL_MODE_USER (1 << 1) -#define DWC_TIM_CTRL_INT_MASK BIT(2) -#define DWC_TIM_CTRL_PWM BIT(3) - -struct dwc_pwm_ctx { - u32 cnt; - u32 cnt2; - u32 ctrl; -}; - -struct dwc_pwm { - struct pwm_chip chip; - void __iomem *base; - struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; -}; -#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) - -static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) -{ - return readl(dwc->base + offset); -} - -static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offs= et) -{ - writel(value, dwc->base + offset); -} +#include "pwm-dwc.h" =20 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) { @@ -196,7 +148,7 @@ static const struct pwm_ops dwc_pwm_ops =3D { .owner =3D THIS_MODULE, }; =20 -static struct dwc_pwm *dwc_pwm_alloc(struct device *dev) +struct dwc_pwm *dwc_pwm_alloc(struct device *dev) { struct dwc_pwm *dwc; =20 @@ -211,109 +163,7 @@ static struct dwc_pwm *dwc_pwm_alloc(struct device *d= ev) dev_set_drvdata(dev, dwc); return dwc; } - -static int dwc_pwm_probe(struct pci_dev *pci, const struct pci_device_id *= id) -{ - struct device *dev =3D &pci->dev; - struct dwc_pwm *dwc; - int ret; - - dwc =3D dwc_pwm_alloc(dev); - if (!dwc) - return -ENOMEM; - - ret =3D pcim_enable_device(pci); - if (ret) { - dev_err(dev, "Failed to enable device (%pe)\n", ERR_PTR(ret)); - return ret; - } - - pci_set_master(pci); - - ret =3D pcim_iomap_regions(pci, BIT(0), pci_name(pci)); - if (ret) { - dev_err(dev, "Failed to iomap PCI BAR (%pe)\n", ERR_PTR(ret)); - return ret; - } - - dwc->base =3D pcim_iomap_table(pci)[0]; - if (!dwc->base) { - dev_err(dev, "Base address missing\n"); - return -ENOMEM; - } - - ret =3D devm_pwmchip_add(dev, &dwc->chip); - if (ret) - return ret; - - pm_runtime_put(dev); - pm_runtime_allow(dev); - - return 0; -} - -static void dwc_pwm_remove(struct pci_dev *pci) -{ - pm_runtime_forbid(&pci->dev); - pm_runtime_get_noresume(&pci->dev); -} - -#ifdef CONFIG_PM_SLEEP -static int dwc_pwm_suspend(struct device *dev) -{ - struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); - int i; - - for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { - if (dwc->chip.pwms[i].state.enabled) { - dev_err(dev, "PWM %u in use by consumer (%s)\n", - i, dwc->chip.pwms[i].label); - return -EBUSY; - } - dwc->ctx[i].cnt =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(i)); - dwc->ctx[i].cnt2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(i)); - dwc->ctx[i].ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(i)); - } - - return 0; -} - -static int dwc_pwm_resume(struct device *dev) -{ - struct pci_dev *pdev =3D container_of(dev, struct pci_dev, dev); - struct dwc_pwm *dwc =3D pci_get_drvdata(pdev); - int i; - - for (i =3D 0; i < DWC_TIMERS_TOTAL; i++) { - dwc_pwm_writel(dwc, dwc->ctx[i].cnt, DWC_TIM_LD_CNT(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].cnt2, DWC_TIM_LD_CNT2(i)); - dwc_pwm_writel(dwc, dwc->ctx[i].ctrl, DWC_TIM_CTRL(i)); - } - - return 0; -} -#endif - -static SIMPLE_DEV_PM_OPS(dwc_pwm_pm_ops, dwc_pwm_suspend, dwc_pwm_resume); - -static const struct pci_device_id dwc_pwm_id_table[] =3D { - { PCI_VDEVICE(INTEL, 0x4bb7) }, /* Elkhart Lake */ - { } /* Terminating Entry */ -}; -MODULE_DEVICE_TABLE(pci, dwc_pwm_id_table); - -static struct pci_driver dwc_pwm_driver =3D { - .name =3D "pwm-dwc", - .probe =3D dwc_pwm_probe, - .remove =3D dwc_pwm_remove, - .id_table =3D dwc_pwm_id_table, - .driver =3D { - .pm =3D &dwc_pwm_pm_ops, - }, -}; - -module_pci_driver(dwc_pwm_driver); +EXPORT_SYMBOL_GPL(dwc_pwm_alloc); =20 MODULE_AUTHOR("Felipe Balbi (Intel)"); MODULE_AUTHOR("Jarkko Nikula "); diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h new file mode 100644 index 000000000000..c8dd690eefb3 --- /dev/null +++ b/drivers/pwm/pwm-dwc.h @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver + * + * Copyright (C) 2018-2020 Intel Corporation + * + * Author: Felipe Balbi (Intel) + * Author: Jarkko Nikula + * Author: Raymond Tan + */ + +#define DWC_TIM_LD_CNT(n) ((n) * 0x14) +#define DWC_TIM_LD_CNT2(n) (((n) * 4) + 0xb0) +#define DWC_TIM_CUR_VAL(n) (((n) * 0x14) + 0x04) +#define DWC_TIM_CTRL(n) (((n) * 0x14) + 0x08) +#define DWC_TIM_EOI(n) (((n) * 0x14) + 0x0c) +#define DWC_TIM_INT_STS(n) (((n) * 0x14) + 0x10) + +#define DWC_TIMERS_INT_STS 0xa0 +#define DWC_TIMERS_EOI 0xa4 +#define DWC_TIMERS_RAW_INT_STS 0xa8 +#define DWC_TIMERS_COMP_VERSION 0xac + +#define DWC_TIMERS_TOTAL 8 + +/* Timer Control Register */ +#define DWC_TIM_CTRL_EN BIT(0) +#define DWC_TIM_CTRL_MODE BIT(1) +#define DWC_TIM_CTRL_MODE_FREE (0 << 1) +#define DWC_TIM_CTRL_MODE_USER (1 << 1) +#define DWC_TIM_CTRL_INT_MASK BIT(2) +#define DWC_TIM_CTRL_PWM BIT(3) + +struct dwc_pwm_ctx { + u32 cnt; + u32 cnt2; + u32 ctrl; +}; + +struct dwc_pwm { + struct pwm_chip chip; + void __iomem *base; + struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; +}; +#define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) + +static inline u32 dwc_pwm_readl(struct dwc_pwm *dwc, u32 offset) +{ + return readl(dwc->base + offset); +} + +static inline void dwc_pwm_writel(struct dwc_pwm *dwc, u32 value, u32 offs= et) +{ + writel(value, dwc->base + offset); +} + +extern struct dwc_pwm *dwc_pwm_alloc(struct device *dev); --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ED885C433FE for ; Wed, 5 Oct 2022 22:13:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229806AbiJEWNU (ORCPT ); Wed, 5 Oct 2022 18:13:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229603AbiJEWM5 (ORCPT ); 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:53 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 07/10] pwm: dwc: make timer clock configurable Date: Wed, 5 Oct 2022 23:12:39 +0100 Message-Id: <20221005221242.470734-8-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add a configurable clock base rate for the pwm as when being built for non-PCI the block may be sourced from an internal clock. Signed-off-by: Ben Dooks --- v4: - moved earlier before the of changes to make the of changes one patch v2: - removed the ifdef and merged the other clock patch in here --- drivers/pwm/pwm-dwc-pci.c | 1 + drivers/pwm/pwm-dwc.c | 10 ++++++---- drivers/pwm/pwm-dwc.h | 2 ++ 3 files changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pwm/pwm-dwc-pci.c b/drivers/pwm/pwm-dwc-pci.c index 2213d0e7f3c8..949423e368f9 100644 --- a/drivers/pwm/pwm-dwc-pci.c +++ b/drivers/pwm/pwm-dwc-pci.c @@ -20,6 +20,7 @@ #include #include #include +#include =20 #include "pwm-dwc.h" =20 diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 90a8ae1252a1..1251620ab771 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include =20 @@ -47,13 +48,13 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, DWC_CLK_PERIOD_NS); + tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - DWC_CLK_PERIOD_NS); + dwc->clk_ns); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; @@ -128,12 +129,12 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, =20 duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); duty +=3D 1; - duty *=3D DWC_CLK_PERIOD_NS; + duty *=3D dwc->clk_ns; state->duty_cycle =3D duty; =20 period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); period +=3D 1; - period *=3D DWC_CLK_PERIOD_NS; + period *=3D dwc->clk_ns; period +=3D duty; state->period =3D period; =20 @@ -156,6 +157,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; =20 + dwc->clk_ns =3D 10; dwc->chip.dev =3D dev; dwc->chip.ops =3D &dwc_pwm_ops; dwc->chip.npwm =3D DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index c8dd690eefb3..dc451cb2eff5 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -40,6 +40,8 @@ struct dwc_pwm_ctx { struct dwc_pwm { struct pwm_chip chip; void __iomem *base; + struct clk *clk; + unsigned int clk_ns; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCA69C433FE for ; Wed, 5 Oct 2022 22:13:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229813AbiJEWNY (ORCPT ); Wed, 5 Oct 2022 18:13:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229646AbiJEWM5 (ORCPT ); Wed, 5 Oct 2022 18:12:57 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AC1983068 for ; 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:54 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 08/10] pwm: dwc: add of/platform support Date: Wed, 5 Oct 2022 23:12:40 +0100 Message-Id: <20221005221242.470734-9-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The dwc pwm controller can be used in non-PCI systems, so allow either platform or OF based probing. Signed-off-by: Ben Dooks --- v5: - fix missing " in kconfig - remove .remove method, devm already sorts this. - merge pwm-number code - split the of code out of the core - get bus clock v4: - moved the compile test code earlier - fixed review comments - used NS_PER_SEC - use devm_clk_get_enabled - ensure we get the bus clock v3: - changed compatible name fixup add pwm/Kconfig --- drivers/pwm/Kconfig | 9 +++++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-of.c | 76 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 86 insertions(+) create mode 100644 drivers/pwm/pwm-dwc-of.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index a9f1c554db2b..c734f58a8bfc 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -192,6 +192,15 @@ config PWM_DWC_PCI To compile this driver as a module, choose M here: the module will be called pwm-dwc-pci. =20 +config PWM_DWC_OF + tristate "DesignWare PWM Controller (OF bus)" + depends on PWM_DWC && OF + help + PWM driver for Synopsys DWC PWM Controller on an OF bus. + + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-of. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index a70d36623129..d1fd1641f077 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PWM_CLPS711X) +=3D pwm-clps711x.o obj-$(CONFIG_PWM_CRC) +=3D pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) +=3D pwm-cros-ec.o obj-$(CONFIG_PWM_DWC) +=3D pwm-dwc.o +obj-$(CONFIG_PWM_DWC_OF) +=3D pwm-dwc-of.o obj-$(CONFIG_PWM_DWC_PCI) +=3D pwm-dwc-pci.o obj-$(CONFIG_PWM_EP93XX) +=3D pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) +=3D pwm-fsl-ftm.o diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c new file mode 100644 index 000000000000..c5b4351cc7b0 --- /dev/null +++ b/drivers/pwm/pwm-dwc-of.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DesignWare PWM Controller driver OF + * + * Copyright (C) 2022 SiFive, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pwm-dwc.h" + +static int dwc_pwm_plat_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct dwc_pwm *dwc; + struct clk *bus; + u32 nr_pwm; + + dwc =3D dwc_pwm_alloc(dev); + if (!dwc) + return -ENOMEM; + + if (!device_property_read_u32(dev, "snps,pwm-number", &nr_pwm)) { + if (nr_pwm > DWC_TIMERS_TOTAL) + dev_err(dev, "too many PWMs (%d) specified, capping at %d\n", + nr_pwm, dwc->chip.npwm); + else + dwc->chip.npwm =3D nr_pwm; + } + + dwc->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dwc->base)) + return PTR_ERR(dwc->base); + + bus =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(bus)) + return dev_err_probe(dev, PTR_ERR(bus), + "failed to get clock\n"); + + dwc->clk =3D devm_clk_get_enabled(dev, "timer"); + if (IS_ERR(dwc->clk)) + return dev_err_probe(dev, PTR_ERR(dwc->clk), + "failed to get timer clock\n"); + + dwc->clk_ns =3D NSEC_PER_SEC / clk_get_rate(dwc->clk); + return devm_pwmchip_add(dev, &dwc->chip); +} + +static const struct of_device_id dwc_pwm_dt_ids[] =3D { + { .compatible =3D "snps,dw-apb-timers-pwm2" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc_pwm_dt_ids); + +static struct platform_driver dwc_pwm_plat_driver =3D { + .driver =3D { + .name =3D "dwc-pwm", + .of_match_table =3D dwc_pwm_dt_ids, + }, + .probe =3D dwc_pwm_plat_probe, +}; + +module_platform_driver(dwc_pwm_plat_driver); + +MODULE_ALIAS("platform:dwc-pwm-of"); +MODULE_AUTHOR("Ben Dooks "); +MODULE_DESCRIPTION("DesignWare PWM Controller"); +MODULE_LICENSE("GPL"); --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6860CC433FE for ; Wed, 5 Oct 2022 22:13:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229993AbiJEWNm (ORCPT ); Wed, 5 Oct 2022 18:13:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39128 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229751AbiJEWNH (ORCPT ); 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:55 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 09/10] pwm: dwc: add PWM bit unset in get_state call Date: Wed, 5 Oct 2022 23:12:41 +0100 Message-Id: <20221005221242.470734-10-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If we are not in PWM mode, then the output is technically a 50% output based on a single timer instead of the high-low based on the two counters. Add a check for the PWM mode in dwc_pwm_get_state() and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle. This may only be an issue on initialisation, as the rest of the code currently assumes we're always going to have the extended PWM mode using two counters. Signed-off-by: Ben Dooks --- v4: - fixed review comment on mulit-line calculations --- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 1251620ab771..5ef0fe7ea3e9 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -121,23 +121,30 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); u64 duty, period; + u32 ctrl, ld, ld2; =20 pm_runtime_get_sync(chip->dev); =20 - state->enabled =3D !!(dwc_pwm_readl(dwc, - DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN); + ctrl =3D dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm)); + ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); + ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); =20 - duty =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); - duty +=3D 1; - duty *=3D dwc->clk_ns; - state->duty_cycle =3D duty; + state->enabled =3D !!(ctrl & DWC_TIM_CTRL_EN); =20 - period =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); - period +=3D 1; - period *=3D dwc->clk_ns; - period +=3D duty; - state->period =3D period; + /* If we're not in PWM, technically the output is a 50-50 + * based on the timer load-count only. + */ + if (ctrl & DWC_TIM_CTRL_PWM) { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D (ld2 + 1) * dwc->clk_ns; + period +=3D duty; + } else { + duty =3D (ld + 1) * dwc->clk_ns; + period =3D duty * 2; + } =20 + state->period =3D period; + state->duty_cycle =3D duty; state->polarity =3D PWM_POLARITY_INVERSED; =20 pm_runtime_put_sync(chip->dev); --=20 2.35.1 From nobody Mon Apr 6 19:38:37 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E09E4C433FE for ; Wed, 5 Oct 2022 22:13:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229959AbiJEWNh (ORCPT ); Wed, 5 Oct 2022 18:13:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229747AbiJEWNH (ORCPT ); Wed, 5 Oct 2022 18:13:07 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 822EA8322C for ; Wed, 5 Oct 2022 15:12:59 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id w18so19090752wro.7 for ; Wed, 05 Oct 2022 15:12:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=MuQJZUiYgsrv6ydPrE/ryH64TRoc2yWi4dM3ARWJNR4=; b=S6BifuCtg7j9Yg/lQuw1lNviDWh59FRm5YLJA3VIdpwkWkCXro7gQlvvYPOTWyH4gU T7nUGm//z73JpFf8OKGrFLYTNY6vva50NG3tsnA+yN3M66zC+cgyvaNrhCKdY5CUdczu kV6RD4cbZjg4mUyObTnA3dfsi8NlBsxASXgbaZQqHpMtDVas0f99mnSX5O6Pz0JYFiGt XaHLdTQJA2/HMMa3+Wda5HwmaQLoYTyOHVHObjDUFINEPxDZ/dyBiKQeuAsmFyr/uPVW jaWgW8dd5+ltqixppG5TjxvF/uKmn5m8a+1iTdeQRdi0R80qR7ytDy5G54xS7TfgoRyT QJ8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=MuQJZUiYgsrv6ydPrE/ryH64TRoc2yWi4dM3ARWJNR4=; b=u1aev+WgcNaiGtWt29XIwZCdoE1jmnHPio+lFV2G6OMTclZgGBsqp4d7DZdiaM8M82 4JZwRejxjN4J4JTZyGQS+81fWMwxdB/Uh2hf07H7xbGy+foirK3P7RJteAUr9Pzb3av8 rhZiPwqzjVhRPwpo+xloQB3RhasMKuKs+2vgo+EqYI96QFPM6umnQy7icgktsobvtVw1 EAZD9ko8n8HVu7wgp9kPnfKi+MFEXI687x+ndL0hnWdZeSv/3+x5ZzQgEJCCqcxSZW/7 JRV1q6CJJx2hIq2/tonJNUdoGtRzE7hzhMCWDAFCcSjGqkWYVYUGQ/4f/8QKFOPHXYhq /Bsg== X-Gm-Message-State: ACrzQf0H+ywCnIpsigWSBKWw2HAZZyfsx+eo1kd/JH5MzrVt+B9gSgbQ dz25DwGx+JzawM/AOSk/+5lubw== X-Google-Smtp-Source: AMsMyM7k19FwtuqbY+riimgVPEMXQz/6JQL+rFU+kGr25+GC0WrX1Vhu5mmN57nPcKuJoROVKUDLlQ== X-Received: by 2002:a5d:6a42:0:b0:22e:6706:647b with SMTP id t2-20020a5d6a42000000b0022e6706647bmr1070556wrw.58.1665007977246; Wed, 05 Oct 2022 15:12:57 -0700 (PDT) Received: from rainbowdash.. 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[86.15.83.122]) by smtp.gmail.com with ESMTPSA id d2-20020adffd82000000b0022e327f849fsm12184437wrr.5.2022.10.05.15.12.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 15:12:56 -0700 (PDT) From: Ben Dooks To: linux-pwm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Lee Jones , u.kleine-koenig@pengutronix.de, Thierry Reding , Krzysztof Kozlowski , Greentime Hu , jarkko.nikula@linux.intel.com, William Salmon , Jude Onyenegecha , Ben Dooks Subject: [PATCH v5 10/10] pwm: dwc: use clock rate in hz to avoid rounding issues Date: Wed, 5 Oct 2022 23:12:42 +0100 Message-Id: <20221005221242.470734-11-ben.dooks@sifive.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221005221242.470734-1-ben.dooks@sifive.com> References: <20221005221242.470734-1-ben.dooks@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org As noted, the clock-rate when not a nice multiple of ns is probably going to end up with inacurate caculations, as well as on a non pci system the rate may change (although we've not put a clock rate change notifier in this code yet) so we also add some quick checks of the rate when we do any calculations with it. Signed-off-by; Ben Dooks Reported-by: Uwe Kleine-K=C3=B6nig --- drivers/pwm/pwm-dwc-of.c | 2 +- drivers/pwm/pwm-dwc.c | 29 ++++++++++++++++++++--------- drivers/pwm/pwm-dwc.h | 2 +- 3 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/pwm/pwm-dwc-of.c b/drivers/pwm/pwm-dwc-of.c index c5b4351cc7b0..5f7f066859d4 100644 --- a/drivers/pwm/pwm-dwc-of.c +++ b/drivers/pwm/pwm-dwc-of.c @@ -50,7 +50,7 @@ static int dwc_pwm_plat_probe(struct platform_device *pde= v) return dev_err_probe(dev, PTR_ERR(dwc->clk), "failed to get timer clock\n"); =20 - dwc->clk_ns =3D NSEC_PER_SEC / clk_get_rate(dwc->clk); + dwc->clk_rate =3D clk_get_rate(dwc->clk); return devm_pwmchip_add(dev, &dwc->chip); } =20 diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c index 5ef0fe7ea3e9..f48a6245a3b5 100644 --- a/drivers/pwm/pwm-dwc.c +++ b/drivers/pwm/pwm-dwc.c @@ -43,18 +43,22 @@ static int __dwc_pwm_configure_timer(struct dwc_pwm *dw= c, u32 high; u32 low; =20 + if (dwc->clk) + dwc->clk_rate =3D clk_get_rate(dwc->clk); + /* * Calculate width of low and high period in terms of input clock * periods and check are the result within HW limits between 1 and * 2^32 periods. */ - tmp =3D DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); + tmp =3D state->duty_cycle * dwc->clk_rate; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; low =3D tmp - 1; =20 - tmp =3D DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, - dwc->clk_ns); + tmp =3D (state->period - state->duty_cycle) * dwc->clk_rate; + tmp =3D DIV_ROUND_CLOSEST_ULL(tmp, NSEC_PER_SEC); if (tmp < 1 || tmp > (1ULL << 32)) return -ERANGE; high =3D tmp - 1; @@ -120,6 +124,7 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, st= ruct pwm_device *pwm, struct pwm_state *state) { struct dwc_pwm *dwc =3D to_dwc_pwm(chip); + unsigned long clk_rate; u64 duty, period; u32 ctrl, ld, ld2; =20 @@ -129,22 +134,28 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, ld =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm)); ld2 =3D dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm)); =20 + if (dwc->clk) + dwc->clk_rate =3D clk_get_rate(dwc->clk); + + clk_rate =3D dwc->clk_rate; state->enabled =3D !!(ctrl & DWC_TIM_CTRL_EN); =20 /* If we're not in PWM, technically the output is a 50-50 * based on the timer load-count only. */ if (ctrl & DWC_TIM_CTRL_PWM) { - duty =3D (ld + 1) * dwc->clk_ns; - period =3D (ld2 + 1) * dwc->clk_ns; + duty =3D ld + 1; + period =3D ld2 + 1; period +=3D duty; } else { - duty =3D (ld + 1) * dwc->clk_ns; + duty =3D ld + 1; period =3D duty * 2; } =20 - state->period =3D period; - state->duty_cycle =3D duty; + duty *=3D NSEC_PER_SEC; + period *=3D NSEC_PER_SEC; + state->period =3D DIV_ROUND_CLOSEST_ULL(period, clk_rate); + state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL(duty, clk_rate); state->polarity =3D PWM_POLARITY_INVERSED; =20 pm_runtime_put_sync(chip->dev); @@ -164,7 +175,7 @@ struct dwc_pwm *dwc_pwm_alloc(struct device *dev) if (!dwc) return NULL; =20 - dwc->clk_ns =3D 10; + dwc->clk_rate =3D NSEC_PER_SEC / 10; dwc->chip.dev =3D dev; dwc->chip.ops =3D &dwc_pwm_ops; dwc->chip.npwm =3D DWC_TIMERS_TOTAL; diff --git a/drivers/pwm/pwm-dwc.h b/drivers/pwm/pwm-dwc.h index dc451cb2eff5..19bdc2224690 100644 --- a/drivers/pwm/pwm-dwc.h +++ b/drivers/pwm/pwm-dwc.h @@ -41,7 +41,7 @@ struct dwc_pwm { struct pwm_chip chip; void __iomem *base; struct clk *clk; - unsigned int clk_ns; + unsigned long clk_rate; struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL]; }; #define to_dwc_pwm(p) (container_of((p), struct dwc_pwm, chip)) --=20 2.35.1