From nobody Fri Dec 19 17:00:03 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C06FDC433FE for ; Wed, 5 Oct 2022 16:16:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230526AbiJEQQw (ORCPT ); Wed, 5 Oct 2022 12:16:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230472AbiJEQQX (ORCPT ); Wed, 5 Oct 2022 12:16:23 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC68E7E339; Wed, 5 Oct 2022 09:16:16 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 295D8tma012981; Wed, 5 Oct 2022 18:15:50 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=iyz5w+TWRIOyUqxHw7BoijPFfbfPlmmExF0v8d2qvpU=; b=VUCNHB/LZHoHnEMCPx9VEXGUIIebaQt2rh5OhsOqY1bJISGuTNJkdclbTlKWP3TfkBxa jvhZh24EIkVg6j/WCfpo6kZ7Cs2/Rfl3COhR7uJlSHb/D1JfoCIZCv64rlIDoi2HHjBG u70sPSSL7AiRSVfUTDDbba96H25ZdBlMINiEi3xy9Up2Id4QTUfT1zBvJ53JHeZJXZ0g bcJut2Si1psT8vJdGZstavBV8GRypkv5E14WEcnaa1pwlQo5vGvEokLLLWHkL77n8Fru p1wd2VL/atNiRjADtoYDU8Ab5fX9nQCs1wGIjmuznTAC7k02Y7YD+M0wWP17uTG37lrM Nw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3jxcw28eqg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Oct 2022 18:15:50 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0CBC910002A; Wed, 5 Oct 2022 18:15:45 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C9CEB235F12; Wed, 5 Oct 2022 18:15:45 +0200 (CEST) Received: from localhost (10.75.127.116) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2375.31; Wed, 5 Oct 2022 18:15:45 +0200 From: Olivier Moysan To: Alexandre Torgue , Andy Shevchenko , Fabrice Gasnier , Jonathan Cameron , Lars-Peter Clausen , Maxime Coquelin , , Olivier Moysan , Paul Cercueil , Sebastian Andrzej Siewior , Wan Jiabing , Yannick Brosseau CC: , , , Subject: [PATCH v3 5/8] ARM: dts: stm32: add adc support to stm32mp13 Date: Wed, 5 Oct 2022 18:14:21 +0200 Message-ID: <20221005161424.4537-6-olivier.moysan@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221005161424.4537-1-olivier.moysan@foss.st.com> References: <20221005161424.4537-1-olivier.moysan@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.75.127.116] X-ClientProxiedBy: GPXDAG2NODE4.st.com (10.75.127.68) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-05_03,2022-10-05_01,2022-06-22_01 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add ADC1 and ADC2 support to STM32MP13 SoC family. The STM32MP131 provides only ADC2, while other STM32MP13 SoCs provide both ADC1 and ADC2. Internal channels support limitations: - VREFINT internal channel requires calibration data from OTP memory. The nvmem properties used to access OTP are not defined for time being, as OTP support is not yet enabled. - VBAT internal channel is not defined by default in SoC DT, and has be defined in board DT when needed, instead. This avoids unwanted current consumption on battery, when ADC conversions are performed on any other channels. Signed-off-by: Olivier Moysan --- arch/arm/boot/dts/stm32mp131.dtsi | 43 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp133.dtsi | 31 ++++++++++++++++++++++ 2 files changed, 74 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp1= 31.dtsi index 3a921db23e9f..5e46234f60f2 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -153,6 +153,49 @@ dmamux1: dma-router@48002000 { dma-channels =3D <16>; }; =20 + adc_2: adc@48004000 { + compatible =3D "st,stm32mp13-adc-core"; + reg =3D <0x48004000 0x400>; + interrupts =3D ; + clocks =3D <&rcc ADC2>, <&rcc ADC2_K>; + clock-names =3D "bus", "adc"; + interrupt-controller; + #interrupt-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + adc2: adc@0 { + compatible =3D "st,stm32mp13-adc"; + #io-channel-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0>; + interrupt-parent =3D <&adc_2>; + interrupts =3D <0>; + dmas =3D <&dmamux1 10 0x400 0x80000001>; + dma-names =3D "rx"; + status =3D "disabled"; + + channel@13 { + reg =3D <13>; + label =3D "vrefint"; + }; + channel@14 { + reg =3D <14>; + label =3D "vddcore"; + }; + channel@16 { + reg =3D <16>; + label =3D "vddcpu"; + }; + channel@17 { + reg =3D <17>; + label =3D "vddq_ddr"; + }; + }; + }; + rcc: rcc@50000000 { compatible =3D "st,stm32mp13-rcc", "syscon"; reg =3D <0x50000000 0x1000>; diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp1= 33.dtsi index 531c263c9f46..6bc702fe43af 100644 --- a/arch/arm/boot/dts/stm32mp133.dtsi +++ b/arch/arm/boot/dts/stm32mp133.dtsi @@ -8,6 +8,37 @@ =20 / { soc { + adc_1: adc@48003000 { + compatible =3D "st,stm32mp13-adc-core"; + reg =3D <0x48003000 0x400>; + interrupts =3D ; + clocks =3D <&rcc ADC1>, <&rcc ADC1_K>; + clock-names =3D "bus", "adc"; + interrupt-controller; + #interrupt-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + + adc1: adc@0 { + compatible =3D "st,stm32mp13-adc"; + #io-channel-cells =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0x0>; + interrupt-parent =3D <&adc_1>; + interrupts =3D <0>; + dmas =3D <&dmamux1 9 0x400 0x80000001>; + dma-names =3D "rx"; + status =3D "disabled"; + + channel@18 { + reg =3D <18>; + label =3D "vrefint"; + }; + }; + }; + m_can1: can@4400e000 { compatible =3D "bosch,m_can"; reg =3D <0x4400e000 0x400>, <0x44011000 0x1400>; --=20 2.25.1