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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:21 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:12 +0100 Subject: [PATCH v6 01/10] dt-bindings: input: mtk-pmic-keys: add binding for MT6357 PMIC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-1-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1006; i=amergnat@baylibre.com; h=from:subject:message-id; bh=acIU37N8P1oQiEeAFVfuuIgjK7XT7A/zFtqy1fGJDhM=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsWWZDdwoLf/Rb2AU6TJp1j5Of+uaN7zUCgekqo ZCgL05SJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFgAKCRArRkmdfjHURa0oD/ 95wHQ5+U7hl58gSJwszReViGY6DKPWH/ihnDPhk6ryLI3o/2xnFnqVAVvNcZkKxIyXBRcnI2txdll8 ynvVkvnt1idkQevWBMNV30PTAgH+GUjeczGTSZZLA2e0iAPomE9YoCZI2JQgYDZLmvx77dB1m+7ayz Qr5xRPrkEUyYJfKtFHxMN28AeMia8+0o8N/sklrrj+1kPzFYub/LdhWGegOlV6D6MjVsfrCOhDFxts xgVeutSlAD4YlRmGvdGYirXOgqow21qIxkZkHidLJl3aEDx/9AAgreME6ARMXq1qsUu/9hsvS5S4sP tsRirbSAOaffwLolt4/RxvBk8j6G3yZAHIVwZQ6YEWZqS6jJh7Lhyho2/Pnm/xbx+ZLUf91zuNj3qs uUObedBl1h3FzF3fi8LFkc9zOVjVFUmkut18bgX5swXkCD8AxqX7WuaBFlW/rmzAF3Sq3Ibx3Wo5W6 ZGTMjv9e4smBWFkodhGM7Yg0pPgYF19EINb3CScsPvlWS6X01mq5aIQOS4QXtz4YeFh+2O7b2i/5O1 IyOB+/I8l9ft1cnu77UiIBHPjupGODDILzv2nzNXJcwf4thOr2wGKl/y7T0K05IB9ez8mvX4pr6crr Ozd7qR/UGNVRgAqDqxTbsArppi3rLfWempLVRSwW4f8J7uMSHPpkob6GBVkw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add binding documentation for the PMIC keys on MT6357. Signed-off-by: Fabien Parent Acked-by: Rob Herring Acked-by: Dmitry Torokhov Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yam= l b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index 2f72ec418415..037c3ae9f1c3 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -26,6 +26,7 @@ properties: enum: - mediatek,mt6323-keys - mediatek,mt6331-keys + - mediatek,mt6357-keys - mediatek,mt6358-keys - mediatek,mt6397-keys =20 --=20 b4 0.10.1 From nobody Sat Sep 21 09:39:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EE38AC4167B for ; Fri, 25 Nov 2022 15:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230071AbiKYPLc (ORCPT ); Fri, 25 Nov 2022 10:11:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229624AbiKYPL0 (ORCPT ); Fri, 25 Nov 2022 10:11:26 -0500 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB13932043 for ; Fri, 25 Nov 2022 07:11:24 -0800 (PST) Received: by mail-wm1-x32b.google.com with SMTP id 5so3687754wmo.1 for ; Fri, 25 Nov 2022 07:11:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LtaodGVpC5RT6XYiK+eOY0rwcK2uWhEYktwBYDm+D3U=; b=cHgcsWDMIqHdG9vIOjx3pGbnzji09i6C/57tbtdajxuwQin3LJIy/otdn9HakMSAaV BAYil3kI7Zkw5G2sDuV5fky92NeDeMOafch2EtwF0XalxCBbIDTBMslaHe9myzp3z/CM 27neY6DmjCGt/vh0gIYAHW84hOO/ut96SIAvr1bLt2Xk76/zN4kUcxt8XUdBq8oB4q/q TRguZd4h84BRFgfBqGed8tubSQjD1Ud4avL0tZ+TJIGkyTWWV77GS+LTimU6OKI+xmON NJhwyJBlKgh7bVhy4kYjPWiCc6GcWkZT1aJExOWuVfQmHiX2NYI5P6JlZgLcaXmF6bIt Bbbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LtaodGVpC5RT6XYiK+eOY0rwcK2uWhEYktwBYDm+D3U=; b=64fT5y8x7u9HicNE+91t7Aepbsld7zuV0tNEhGs4o+E2Dh6XwBc/FvpZUCb+yD0lTv RPuvipUIsBhew6lIgsXQ5Jaako0mRQWNFgcXlz7gVl1UIB7ztSL/CDeCswc8+HK4it8w ctGwIHhQY8USM0HbepVT44Deu+uGjX6IPqQMvLwHiVWnvROnuNQinA2D79kstlf/jrm+ 7tBasMc8k0+19S8IL0TGN0Q8rMXG1hRFt9E3B6JslD7Lldud/NW3Vf7f2KmSHH5s6PGR DUCTglT+sy5e0jdN97Io1LmoUtO/CJ+zfVX36MW4/qJtI/sXxik84ywFr6LxYP3g5tFR ROJg== X-Gm-Message-State: ANoB5pmk9THQDHB2ZjrD3RkDgdJhGK+Ot76sX0ys6wqPabxXfz11bpX2 3xuntXeVKhPVfY8sSFrxoMZ7RA== X-Google-Smtp-Source: AA0mqf7kS6Tz5quZlQxyKibRuFvfNP/J7F+sa3rlIYYznVcbfnJ73G8BTJTH5t51EQwIS0NI1o/fXw== X-Received: by 2002:a05:600c:3543:b0:3cf:74bb:feb1 with SMTP id i3-20020a05600c354300b003cf74bbfeb1mr27647631wmq.102.1669389082982; Fri, 25 Nov 2022 07:11:22 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:22 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:13 +0100 Subject: [PATCH v6 02/10] dt-bindings: rtc: mediatek: convert MT6397 rtc documentation MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-2-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3564; i=amergnat@baylibre.com; h=from:subject:message-id; bh=CtchvNUNYKQ+sRRXF+yBXQCgDbmvYDamNuPU/DlwH4k=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsWBup/boE8Lq7PLq5YmKC0aWKnYNDwZdf/JlDr xt36kAKJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFgAKCRArRkmdfjHURddkD/ 9zvzIvPq1+3Cpu/j5+tk7ih7fpJnVPzD77DkXewOg33pWoCx6R801Pll71H/M4kA4aTOdJTwP3Tf30 gi1HMRFOWbXgt3b7sKwh20Dxtze5EsaVItBwcintwufuPqBft5aaGTgtYLTEXDYvNZvRJqqBr3NzBv oP6DbwOwshLRTnkd7CiHOcldrQHmlKlV0jGijF90IQI+6x9//I3FuNdsPrkp0rh7pIkqhWjWKSMQ2l Z3k8Tw8SR2hjnNRdeah4BineZFlFzAU8nPWP/XlmDMf8aWQbQZ3mIvsmFqKzlHGd1kSmvFLjw58F6R HAcvn4sEZOukScbDhpYFZMftpXtNT2VIx74E1PtkdglxKtwkDu/D6p6T6tKa/o+ZBMmF4mcXxGc22W gI9xc9bGkZEg7kjQHMkA2fuOqecibRV/+PhrxZDa3mt9qr2baES47gbc46qeOqD/7RtASyVgCyMmqP TB7wLMkzNAQwv8G5Nnt1pfomjnY+BIeeD2F7w6sK5YH0OwXFSDGmTbimBVkilFTgqZCt9rOuFugP8K ToCmVX3L1X1jw17Zar/CPYAP9FtVbLJ/krIpi6Wa+EavsSXap92KI+bcyvT6cHhAC4sFfmP8FQkATJ K1eb7AikJbJV6VW5FuwdKgN2Axk5uhQjfawxo6vwERasEbDQt1dqdmZAeqGQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Convert rtc/rtc-mt6397.txt to rtc/mt6397-rtc.yaml - Add maintainer - Remove the .txt binding file Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/mfd/mt6397.txt | 2 +- .../bindings/rtc/mediatek,mt6397-rtc.yaml | 35 ++++++++++++++++++= ++++ .../devicetree/bindings/rtc/rtc-mt6397.txt | 31 ------------------- 3 files changed, 36 insertions(+), 32 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentati= on/devicetree/bindings/mfd/mt6397.txt index 0088442efca1..79aaf21af8e9 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -33,7 +33,7 @@ Optional subnodes: - compatible: "mediatek,mt6331-rtc" - compatible: "mediatek,mt6358-rtc" - compatible: "mediatek,mt6397-rtc" - For details, see ../rtc/rtc-mt6397.txt + For details, see ../rtc/mediatek,mt6397-rtc.yaml - regulators Required properties: - compatible: "mediatek,mt6323-regulator" diff --git a/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml= b/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml new file mode 100644 index 000000000000..97b09c81e548 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml @@ -0,0 +1,35 @@ + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/mediatek,mt6397-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6397/MT6366/MT6358/MT6323 RTC + +maintainers: + - Tianping Fang + - Alexandre Mergnat + +description: + MediaTek PMIC based RTC is an independent function of MediaTek PMIC that= works + as a type of multi-function device (MFD). The RTC can be configured and = set up + with PMIC wrapper bus which is a common resource shared with the other + functions found on the same PMIC. + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + enum: + - mediatek,mt6323-rtc + - mediatek,mt6358-rtc + - mediatek,mt6366-rtc + - mediatek,mt6397-rtc + + start-year: true + +additionalProperties: false + +required: + - compatible diff --git a/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt b/Documen= tation/devicetree/bindings/rtc/rtc-mt6397.txt deleted file mode 100644 index 7212076a8f1b..000000000000 --- a/Documentation/devicetree/bindings/rtc/rtc-mt6397.txt +++ /dev/null @@ -1,31 +0,0 @@ -Device-Tree bindings for MediaTek PMIC based RTC - -MediaTek PMIC based RTC is an independent function of MediaTek PMIC that w= orks -as a type of multi-function device (MFD). The RTC can be configured and se= t up -with PMIC wrapper bus which is a common resource shared with the other -functions found on the same PMIC. - -For MediaTek PMIC MFD bindings, see: -../mfd/mt6397.txt - -For MediaTek PMIC wrapper bus bindings, see: -../soc/mediatek/pwrap.txt - -Required properties: -- compatible: Should be one of follows - "mediatek,mt6323-rtc": for MT6323 PMIC - "mediatek,mt6358-rtc": for MT6358 PMIC - "mediatek,mt6366-rtc", "mediatek,mt6358-rtc": for MT6366 PMIC - "mediatek,mt6397-rtc": for MT6397 PMIC - -Example: - - pmic { - compatible =3D "mediatek,mt6323"; - - ... - - rtc { - compatible =3D "mediatek,mt6323-rtc"; - }; - }; --=20 b4 0.10.1 From nobody Sat Sep 21 09:39:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 000E2C4332F for ; Fri, 25 Nov 2022 15:11:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230119AbiKYPLe (ORCPT ); Fri, 25 Nov 2022 10:11:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229599AbiKYPL0 (ORCPT ); Fri, 25 Nov 2022 10:11:26 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B72B91CB23 for ; Fri, 25 Nov 2022 07:11:25 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id n3so7193266wrp.5 for ; Fri, 25 Nov 2022 07:11:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=SERY71Vd1RHSOGeZoeNuejCrV5VkyCcMPbYPY5d0cXg=; b=CnUVkXQCV0WmPc2slCHcG/UmeprUoeDc+HlyXnUrx7JqxMpxCpCSA7pFyTYrn3mqf6 chG2YxoLRHhLgIiCELc++4B1UO7vEWIO0oHL6z/LV5CSTxCatVilLeg11jMkZCBQMWs3 zW1rSxQQf6k1mTmZojQfo+AVzx5qoZe9/cxOpyLTNcJJKKZ/JVHOjVrvrVtlzzAZjiWA AdCxHGywAm/G7J/6ExZqMAYEmYougS7BANF2KKGxYQf+O/ca1CLWhzgOzDRAu5nkw4BI +twOvRJipNrOLHGP757UiYCkaCsXZQC/C/MSNzWd5wmskYQprhUJm6FXSZTcpkXY1jub Lf2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SERY71Vd1RHSOGeZoeNuejCrV5VkyCcMPbYPY5d0cXg=; b=FoB1r8RoULyKJ45xPxKnV3bRqzNAwOX5Er1LifUXvUVnKaCA7cbWdK5Dte6kiRelQK ov086i6W4FuYxtc5bdv9y79U55ltkJfV9NFsYWOktJNGkMb1OxIhtxxK/UpEkLSKy43D ZHWwh1YSEOz19jNSDxGrOPFS/YSdFbhu7+4IM6bCK90s3tLGqBfVLXCLqZC8RihNpwAH TNI4AlC9qcETJeIEvU7AehvKDnth/iR1YK0K4KpjtF0QdjGhALWGgtImO+QOBE7YVo9o CnRVl6uTgxkt+bSilC25xAk+NrWVc9AY901CXMzg8Et60rsV2u4A3t3xSWZ6jr4JY0FO 2w3Q== X-Gm-Message-State: ANoB5pnyq7rU257N/fjjVv8JBHwfRLFIVzpA1+eB1gUo/Xkj3iPGfMdD REXDGkJm9cUD09+WSojCbg2JkA== X-Google-Smtp-Source: AA0mqf4igpRB04xMtP9+f7/oC4bWlo8PKHx3XdmeOCBzo2w9zn/sPMuCZmOrNXrSKGKCwWr79oTWzw== X-Received: by 2002:a05:6000:12c3:b0:236:8130:56e7 with SMTP id l3-20020a05600012c300b00236813056e7mr23334960wrx.309.1669389084210; Fri, 25 Nov 2022 07:11:24 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:23 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:14 +0100 Subject: [PATCH v6 03/10] dt-bindings: rtc: mediatek: add MT6357 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-3-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1164; i=amergnat@baylibre.com; h=from:subject:message-id; bh=UVzrRIoQ4/WPI9WfRYNgs1FH7udWyYMvOv47aHSYxpY=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsWWFNWP2r19g13DFXu9HWhIrsdMIy+ZJjgbRS0 4ii6dxSJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFgAKCRArRkmdfjHURbZuEA C1kbaOn8T/19Axqe3IfUlgoWPR1nuWLhIdexIoDHt5ai1UR3KlEIGPpLp5zkUbGqisBFdfLXUgdySq So0aFZ68mnCH8+tFAz4oqBHk/Kx/EoNpegC2r4cOtkqd3g0WemyRvhmdt22Suc+f5U1O55Hwk27fpT voC0B4CNXRlYSt8nhl/5UYmU/5Zx1wEoDNDoT8GGfg1khPYigJVg9qN54MyBAe5VhSW/+O5Lm/NHOw f0BNO7b0xqaQtiWHZxuBvbVR8pHjD8yaoUiueX7qsCRLCdiyNwOGm8NXBdP/33XuoIFGI6jWzUOka+ vw3G1++yCphEWdHa4oN9TZW1g7DKJvS0xqgceVp9+DhGR/nABNcrpXMXlVi/nbvCZrvWectGs9nmCv IG53KpWjnDuQHrQHGgafivFJ9OhnwAXLVDQSiwpyqB0dzr+kvITTfDJ5rgsajWG7YyPB4XVypVHV1H zp+a90msg74NHsfBUwX+yHan9SDPefltQZz7DCYJxHntrSK+uQaKkaqt13DkzOr+GJNxSp/bEntTII N2P+Wycdlai24xk0YFDSsTppcFqo3Mjyy/ZpB7QzHeclL+0FIuwzGvFNdzFdt23qwRQkRMgVu0RGS/ 8BubbetpaGvJv3LIsowBFn0x3WRA0DWP10IaGZvOmFWyX3zcVWGXOMdg3Zjg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add binding documentation of mediatek,mt6397-rtc for mt6357 SoC. Acked-by: Rob Herring Signed-off-by: Alexandre Mergnat --- Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml= b/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml index 97b09c81e548..d582625430e3 100644 --- a/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/mediatek,mt6397-rtc.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/rtc/mediatek,mt6397-rtc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: MediaTek MT6397/MT6366/MT6358/MT6323 RTC +title: MediaTek MT6397/MT6366/MT6358/MT6357/MT6323 RTC =20 maintainers: - Tianping Fang @@ -23,6 +23,7 @@ properties: compatible: enum: - mediatek,mt6323-rtc + - mediatek,mt6357-rtc - mediatek,mt6358-rtc - mediatek,mt6366-rtc - mediatek,mt6397-rtc --=20 b4 0.10.1 From nobody Sat Sep 21 09:39:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A68A0C4332F for ; Fri, 25 Nov 2022 15:12:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230339AbiKYPLz (ORCPT ); Fri, 25 Nov 2022 10:11:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229701AbiKYPLo (ORCPT ); Fri, 25 Nov 2022 10:11:44 -0500 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 02FC13D902 for ; Fri, 25 Nov 2022 07:11:27 -0800 (PST) Received: by mail-wm1-x32d.google.com with SMTP id ja4-20020a05600c556400b003cf6e77f89cso6503664wmb.0 for ; Fri, 25 Nov 2022 07:11:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=EaP34wv8cHsMbN5b2lelNoPsr3chehdl/q6+cIBNPQg=; b=a00aeEiqNLdfaP8pJJMTlm1st+CBVpharXXE5efjNd2t+tAUicUKf/ATqv/wQf4KtM 5isOcb82wBidTFJ/PIPU1/e6lKXxwVog19esAb8AekyIsE9jXXMMnjT/TBt2tbe/A2Y3 ymLxUZHqE83wczl7D157EExhyny7uqe2+9uakjDnwUK0qj6DyVxsf7HrXjvDaLcMWAiQ eo2oIh2nJZeNKGr9m725hWaapJZptybryEs2KFHTdVByGChUXuU3WMhvQ1JzMzmu7mKX 5yIMjmdRbC4onl01PEXEyZDl6L6mi1L0Wduyr/WNO88SDp3u8bmLuIpZ4OQhMBk+7f/g NZVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EaP34wv8cHsMbN5b2lelNoPsr3chehdl/q6+cIBNPQg=; b=H3x8t54rSaG4CGHuT8g/zfaR0GsZlzG4QT5VCGQJQvVSav5wixnT6qglofJcUS1wlv ytcMxbHFXdBNPBGa6Rauf0njbBcq39qWr8Rpz7OYgLFWtJzeVS8oXF6mwoc1aQtT5CaO ZFS6kkfFJwBkrKvaJzDjOH/2QyecvyQkcNiz1Oj9is4tpV36hDF04JpmFZswujoXaz1e hU0euhy8yL92B8P7S4UCpiH7uUJywxeFQfkNdjeiZjZRvsL8c7jT4LRQ99qzbwJLgKtu 7zy6cvRddZMue6cPd8R/J6FJzti+w39E0hKkBVZUlnPt+Jt7MljQes0nQXsiWMv+r1Iy XpZg== X-Gm-Message-State: ANoB5pkIZhgAq3APG4Ng1t/HOloeVCszJ4GsILANOFVQUAke9clZWiOp c8/M7iAxuE9uEDt2m+iZ8BYqdQ== X-Google-Smtp-Source: AA0mqf7dcJLl74CAaap1sCd5Hcm4X7ZYFAQ7k75impAxJ2nhLCoKmK4mcDwYRq6oPcj/HAQ7JXaQ2g== X-Received: by 2002:a05:600c:3d8b:b0:3d0:545:a0 with SMTP id bi11-20020a05600c3d8b00b003d0054500a0mr17157532wmb.123.1669389085313; Fri, 25 Nov 2022 07:11:25 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:24 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:15 +0100 Subject: [PATCH v6 04/10] regulator: dt-bindings: Add binding schema for mt6357 regulators MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-4-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=11440; i=amergnat@baylibre.com; h=from:subject:message-id; bh=y+MiriLy7hAWFi7TI2kfD8KqIfIYGSLRk1pCtSC2vQw=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsX6//zoBpr5oyYTNAos+h38wGLdiC8i63x0Vz4 VEYdOJmJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFwAKCRArRkmdfjHURb8VD/ 0SsXN0bcyn8GquzvUjms7TA0ZXjPNqCOYo/8CW9hr+Wp6id+9npjhRUc3KcVJTvJWxraUeGicgbpSB gEktBlQKhzFFqqKQ2eoHOWGeK276+q6u5qCKEfcbzmZTIfoU7DsGdyCbvQ3+2NZszHmh4XUDDvyLhf Pbi9S7myzSiuheIqrpvOXIbAnQkLlK7aJept4z5gx87F/NsDyfd3TzMzVkI/b+AVzB3/H08tvwPNzJ IW5Lst1FlMeiC8EvQ1FbUfAn+8cHjSBVAjUO32pnAfNmmg3elkOGSsUXOVyrBUQiZlOpIE4LN4NPbr ttePExE7mKpbACFnaZvLc7iTfl3iRivw08xC9U5xA1RbEmEqhFmaGuvRJUEC4PzLl+6fkg9R+OIHh7 K4T2eG0pxrhiBDA+WceZGU+Ng2F/jJWuogNGOViffxHfvDe+w1+HpEn7NoYXroSddylaq1hJxHq/hr FXQRJfpPbi4AmFH5Oe78ZRFcxs530KIGRCC2l3yH2ApqA0gHB/pZrXFIKaO/93ibtmMz7P4L3wAS8B vXy7eDOyX1xcMuiqlvztObihURyskXuxv5cubBJ9NFltiYPr1suKBWzNWkGw0dZuFc4K3h15S0nD7A ma5+uFM9VJo+ULDHEsdGs7DEjHhbhK8IGbB3PQo2aWVVQKq8BUGQShWJ83UQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add YAML schema for the MediaTek MT6357 regulators. Signed-off-by: Fabien Parent Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Mergnat --- .../regulator/mediatek,mt6357-regulator.yaml | 294 +++++++++++++++++= ++++ 1 file changed, 294 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6357-re= gulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-= regulator.yaml new file mode 100644 index 000000000000..6327bb2f6ee0 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6357-regulator= .yaml @@ -0,0 +1,294 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6357-regulator.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6357 Regulators + +maintainers: + - Chen Zhong + - Fabien Parent + - Alexandre Mergnat + +description: | + The MT6357 PMIC provides 5 BUCK and 29 LDO. + Regulators and nodes are named according to the regulator type: + - buck- + - ldo-. + MT6357 regulators node should be sub node of the MT6397 MFD node. + +patternProperties: + "^buck-v(core|modem|pa|proc|s1)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single BUCK regulator. + + required: + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + + "^ldo-v(camio18|aud28|aux18|io18|io28|rf12|rf18|cn18|cn28|fe28)$": + type: object + $ref: fixed-regulator.yaml# + unevaluatedProperties: false + description: + Properties for single fixed LDO regulator. + + required: + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + + "^ldo-v(efuse|ibr|ldo28|mch|cama|camd|cn33-bt|cn33-wifi)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + + "^ldo-v(xo22|emc|mc|sim1|sim2|sram-others|sram-proc|dram|usb33)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + required: + - regulator-name + - regulator-min-microvolt + - regulator-max-microvolt + +additionalProperties: false + +examples: + - | + pmic { + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name =3D "vproc"; + regulator-min-microvolt =3D <518750>; + regulator-max-microvolt =3D <1312500>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <220>; + regulator-always-on; + }; + mt6357_vcore_reg: buck-vcore { + regulator-name =3D "vcore"; + regulator-min-microvolt =3D <518750>; + regulator-max-microvolt =3D <1312500>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <220>; + regulator-always-on; + }; + mt6357_vmodem_reg: buck-vmodem { + regulator-name =3D "vmodem"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <1193750>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <220>; + }; + mt6357_vs1_reg: buck-vs1 { + regulator-name =3D "vs1"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <2200000>; + regulator-ramp-delay =3D <12500>; + regulator-enable-ramp-delay =3D <220>; + regulator-always-on; + }; + mt6357_vpa_reg: buck-vpa { + regulator-name =3D "vpa"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <3650000>; + regulator-ramp-delay =3D <50000>; + regulator-enable-ramp-delay =3D <220>; + }; + mt6357_vfe28_reg: ldo-vfe28 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vfe28"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vxo22_reg: ldo-vxo22 { + regulator-name =3D "vxo22"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <2400000>; + regulator-enable-ramp-delay =3D <110>; + }; + mt6357_vrf18_reg: ldo-vrf18 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vrf18"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <110>; + }; + mt6357_vrf12_reg: ldo-vrf12 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vrf12"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-enable-ramp-delay =3D <110>; + }; + mt6357_vefuse_reg: ldo-vefuse { + regulator-name =3D "vefuse"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3300000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vcn33_bt_reg: ldo-vcn33-bt { + regulator-name =3D "vcn33-bt"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3500000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vcn33_wifi_reg: ldo-vcn33-wifi { + regulator-name =3D "vcn33-wifi"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3500000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vcn28_reg: ldo-vcn28 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcn28"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vcn18_reg: ldo-vcn18 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcn18"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vcama_reg: ldo-vcama { + regulator-name =3D "vcama"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vcamd_reg: ldo-vcamd { + regulator-name =3D "vcamd"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vcamio_reg: ldo-vcamio18 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcamio"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vldo28_reg: ldo-vldo28 { + regulator-name =3D "vldo28"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <3000000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vsram_others_reg: ldo-vsram-others { + regulator-name =3D "vsram-others"; + regulator-min-microvolt =3D <518750>; + regulator-max-microvolt =3D <1312500>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <110>; + regulator-always-on; + }; + mt6357_vsram_proc_reg: ldo-vsram-proc { + regulator-name =3D "vsram-proc"; + regulator-min-microvolt =3D <518750>; + regulator-max-microvolt =3D <1312500>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <110>; + regulator-always-on; + }; + mt6357_vaux18_reg: ldo-vaux18 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vaux18"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vaud28_reg: ldo-vaud28 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vaud28"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vio28_reg: ldo-vio28 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vio28"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vio18_reg: ldo-vio18 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vio18"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <264>; + regulator-always-on; + }; + mt6357_vdram_reg: ldo-vdram { + regulator-name =3D "vdram"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1200000>; + regulator-enable-ramp-delay =3D <3300>; + }; + mt6357_vmc_reg: ldo-vmc { + regulator-name =3D "vmc"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-enable-ramp-delay =3D <44>; + }; + mt6357_vmch_reg: ldo-vmch { + regulator-name =3D "vmch"; + regulator-min-microvolt =3D <2900000>; + regulator-max-microvolt =3D <3300000>; + regulator-enable-ramp-delay =3D <44>; + }; + mt6357_vemc_reg: ldo-vemc { + regulator-name =3D "vemc"; + regulator-min-microvolt =3D <2900000>; + regulator-max-microvolt =3D <3300000>; + regulator-enable-ramp-delay =3D <44>; + regulator-always-on; + }; + mt6357_vsim1_reg: ldo-vsim1 { + regulator-name =3D "vsim1"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <3100000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vsim2_reg: ldo-vsim2 { + regulator-name =3D "vsim2"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <3100000>; + regulator-enable-ramp-delay =3D <264>; + }; + mt6357_vibr_reg: ldo-vibr { + regulator-name =3D "vibr"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <3300000>; + regulator-enable-ramp-delay =3D <44>; + }; + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name =3D "vusb33"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3100000>; + regulator-enable-ramp-delay =3D <264>; + }; + }; + }; +... --=20 b4 0.10.1 From nobody Sat Sep 21 09:39:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12360C4332F for ; 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:26 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:16 +0100 Subject: [PATCH v6 05/10] dt-bindings: soc: mediatek: convert pwrap documentation MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-5-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=9574; i=amergnat@baylibre.com; h=from:subject:message-id; bh=lGcU/tLnBFuf2FChwx+BufI9cy58Bma4z2fSLbd1Gq8=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsXrE+qken7Fg4GdIMw699mOYmNxNcxMzRrKYcW DqDHHiGJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFwAKCRArRkmdfjHURdcfD/ 4yUBxuy8lZAuqNkA98FGpztVt3vWRQg+DjKN+vKmyIg+em2/axvFo80WIiVPVkzWCXPRP3HLhGcUvt vyDGcS69fXg8EWL0G1pZHl2fmweNpTq0L1nFRpV1jpfeDNPmH9TBGO2MVkJ33q1Mi8Jc/7AGb3pCJ1 SZn7D7nkmcKjcac0cLWe4YBpnD7wtCb6OXGb+8VOPZtD4J7B/jJwzmVJluC6cBA6JTrtlQ9ImNC0m+ rhpCLu0m7w2uKvO1GSQO/lK2LoVEgYiEXvnx5gQtrqZ6cpFanYRx4RW7ZCNG4mnj4NExLHhJlL97Jr WBCx5niS8fGHK3SAWrYnbYrx4zM3NVvWkCsy26CNo8Em0InrrS1c4XZqvnP9fU3Qrf/rf/QUMtVIk4 8+vjaee5dLm2nCrEsYhDq3bLybbhaKfWgQgqdlHhlAHpeUrycQaQ2PY+to2wW870uE/bIjBPyWtygp XAGZIgl1UMhQCYQY3qANQYw/1rWZQZ/tX57qSIkhZz71SD4y2dS1ABdQFo33l2JAWRWy4hi3ZLn1+B QzCZ9XbYdETYL8ZMl8U5Mvaz/m0KlyJ0Z+erc7+CKyJZFdBWW7jza/EWDVmjG6awoT6bF9uLy5dbyk LKLTCDU8a0iLr1YIRW6ooy0xG5JvMAbxt/pNkWaUGkgqxH6wRTicTb7jg6aA== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Convert soc/mediatek/pwrap.txt to soc/mediatek/mediatek,pwrap.yaml - Add syscon compatible const for mt8186 and mt8195 to match the DTS needs. Signed-off-by: Alexandre Mergnat --- .../devicetree/bindings/leds/leds-mt6323.txt | 2 +- Documentation/devicetree/bindings/mfd/mt6397.txt | 2 +- .../bindings/soc/mediatek/mediatek,pwrap.yaml | 147 +++++++++++++++++= ++++ .../devicetree/bindings/soc/mediatek/pwrap.txt | 75 ----------- 4 files changed, 149 insertions(+), 77 deletions(-) diff --git a/Documentation/devicetree/bindings/leds/leds-mt6323.txt b/Docum= entation/devicetree/bindings/leds/leds-mt6323.txt index 45bf9f7d85f3..73353692efa1 100644 --- a/Documentation/devicetree/bindings/leds/leds-mt6323.txt +++ b/Documentation/devicetree/bindings/leds/leds-mt6323.txt @@ -9,7 +9,7 @@ MT6323 PMIC hardware. For MT6323 MFD bindings see: Documentation/devicetree/bindings/mfd/mt6397.txt For MediaTek PMIC wrapper bindings see: -Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml =20 Required properties: - compatible : Must be "mediatek,mt6323-led" diff --git a/Documentation/devicetree/bindings/mfd/mt6397.txt b/Documentati= on/devicetree/bindings/mfd/mt6397.txt index 79aaf21af8e9..3bee4a42555d 100644 --- a/Documentation/devicetree/bindings/mfd/mt6397.txt +++ b/Documentation/devicetree/bindings/mfd/mt6397.txt @@ -13,7 +13,7 @@ MT6397/MT6323 is a multifunction device with the followin= g sub modules: It is interfaced to host controller using SPI interface by a proprietary h= ardware called PMIC wrapper or pwrap. MT6397/MT6323 MFD is a child device of pwrap. See the following for pwarp node definitions: -../soc/mediatek/pwrap.txt +../soc/mediatek/mediatek,pwrap.yaml =20 This document describes the binding for MFD device and its sub module. =20 diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.= yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml new file mode 100644 index 000000000000..3969871eaced --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,pwrap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek PMIC Wrapper + +maintainers: + - Flora Fu + - Alexandre Mergnat + +description: + On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface + is not directly visible to the CPU, but only through the PMIC wrapper + inside the SoC. The communication between the SoC and the PMIC can + optionally be encrypted. Also a non standard Dual IO SPI mode can be + used to increase speed. + + IP Pairing + + On MT8135 the pins of some SoC internal peripherals can be on the PMIC. + The signals of these pins are routed over the SPI bus using the pwrap + bridge. In the binding description below the properties needed for bridg= ing + are marked with "IP Pairing". These are optional on SoCs which do not su= pport + IP Pairing + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt2701-pwrap + - mediatek,mt6765-pwrap + - mediatek,mt6779-pwrap + - mediatek,mt6797-pwrap + - mediatek,mt6873-pwrap + - mediatek,mt7622-pwrap + - mediatek,mt8135-pwrap + - mediatek,mt8173-pwrap + - mediatek,mt8183-pwrap + - mediatek,mt8186-pwrap + - mediatek,mt8188-pwrap + - mediatek,mt8195-pwrap + - mediatek,mt8365-pwrap + - mediatek,mt8516-pwrap + - items: + - enum: + - mediatek,mt8186-pwrap + - mediatek,mt8195-pwrap + - const: syscon + + reg: + minItems: 1 + items: + - description: PMIC wrapper registers + - description: IP pairing registers + + reg-names: + minItems: 1 + items: + - const: pwrap + - const: pwrap-bridge + + interrupts: + maxItems: 1 + + clocks: + minItems: 2 + items: + - description: SPI bus clock + - description: Main module clock + - description: System module clock + - description: Timer module clock + + clock-names: + minItems: 2 + items: + - const: spi + - const: wrap + - const: sys + - const: tmr + + resets: + minItems: 1 + items: + - description: PMIC wrapper reset + - description: IP pairing reset + + reset-names: + minItems: 1 + items: + - const: pwrap + - const: pwrap-bridge + + pmic: + type: object + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + +dependentRequired: + resets: [reset-names] + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8365-pwrap + then: + properties: + clocks: + minItems: 4 + + clock-names: + minItems: 4 + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + pwrap@1000d000 { + compatible =3D "mediatek,mt8135-pwrap"; + reg =3D <0 0x1000f000 0 0x1000>, + <0 0x11017000 0 0x1000>; + reg-names =3D "pwrap", "pwrap-bridge"; + interrupts =3D ; + clocks =3D <&clk26m>, <&clk26m>; + clock-names =3D "spi", "wrap"; + resets =3D <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, + <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; + reset-names =3D "pwrap", "pwrap-bridge"; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Doc= umentation/devicetree/bindings/soc/mediatek/pwrap.txt deleted file mode 100644 index 8424b93c432e..000000000000 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ /dev/null @@ -1,75 +0,0 @@ -MediaTek PMIC Wrapper Driver - -This document describes the binding for the MediaTek PMIC wrapper. - -On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface -is not directly visible to the CPU, but only through the PMIC wrapper -inside the SoC. The communication between the SoC and the PMIC can -optionally be encrypted. Also a non standard Dual IO SPI mode can be -used to increase speed. - -IP Pairing - -on MT8135 the pins of some SoC internal peripherals can be on the PMIC. -The signals of these pins are routed over the SPI bus using the pwrap -bridge. In the binding description below the properties needed for bridging -are marked with "IP Pairing". These are optional on SoCs which do not supp= ort -IP Pairing - -Required properties in pwrap device node. -- compatible: - "mediatek,mt2701-pwrap" for MT2701/7623 SoCs - "mediatek,mt6765-pwrap" for MT6765 SoCs - "mediatek,mt6779-pwrap" for MT6779 SoCs - "mediatek,mt6797-pwrap" for MT6797 SoCs - "mediatek,mt6873-pwrap" for MT6873/8192 SoCs - "mediatek,mt7622-pwrap" for MT7622 SoCs - "mediatek,mt8135-pwrap" for MT8135 SoCs - "mediatek,mt8173-pwrap" for MT8173 SoCs - "mediatek,mt8183-pwrap" for MT8183 SoCs - "mediatek,mt8186-pwrap" for MT8186 SoCs - "mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs - "mediatek,mt8195-pwrap" for MT8195 SoCs - "mediatek,mt8365-pwrap" for MT8365 SoCs - "mediatek,mt8516-pwrap" for MT8516 SoCs -- interrupts: IRQ for pwrap in SOC -- reg-names: "pwrap" is required; "pwrap-bridge" is optional. - "pwrap": Main registers base - "pwrap-bridge": bridge base (IP Pairing) -- reg: Must contain an entry for each entry in reg-names. -- clock-names: Must include the following entries: - "spi": SPI bus clock - "wrap": Main module clock - "sys": System module clock (for MT8365 SoC) - "tmr": Timer module clock (for MT8365 SoC) -- clocks: Must contain an entry for each entry in clock-names. - -Optional properities: -- reset-names: Some SoCs include the following entries: - "pwrap" - "pwrap-bridge" (IP Pairing) -- resets: Must contain an entry for each entry in reset-names. -- pmic: Using either MediaTek PMIC MFD as the child device of pwrap - See the following for child node definitions: - Documentation/devicetree/bindings/mfd/mt6397.txt - or the regulator-only device as the child device of pwrap, such as MT638= 0. - See the following definitions for such kinds of devices. - Documentation/devicetree/bindings/regulator/mt6380-regulator.txt - -Example: - pwrap: pwrap@1000f000 { - compatible =3D "mediatek,mt8135-pwrap"; - reg =3D <0 0x1000f000 0 0x1000>, - <0 0x11017000 0 0x1000>; - reg-names =3D "pwrap", "pwrap-bridge"; - interrupts =3D ; - resets =3D <&infracfg MT8135_INFRA_PMIC_WRAP_RST>, - <&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>; - reset-names =3D "pwrap", "pwrap-bridge"; - clocks =3D <&clk26m>, <&clk26m>; - clock-names =3D "spi", "wrap"; - - pmic { - compatible =3D "mediatek,mt6397"; - }; - }; --=20 b4 0.10.1 From nobody Sat Sep 21 09:39:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48DDDC47090 for ; Fri, 25 Nov 2022 15:12:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230431AbiKYPMF (ORCPT ); Fri, 25 Nov 2022 10:12:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36366 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229747AbiKYPLp (ORCPT ); Fri, 25 Nov 2022 10:11:45 -0500 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A0963E0B1 for ; Fri, 25 Nov 2022 07:11:28 -0800 (PST) Received: by mail-wr1-x42b.google.com with SMTP id g12so7162292wrs.10 for ; Fri, 25 Nov 2022 07:11:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/WfPFIvXQkUy4+HZsCcjoOy5HXh/OR2xwCOtqD43AE4=; b=w1SA1ZGNoJjU/F7vhzubxvZtSsnxd1ZwkoI7EfV/TKpuOm5638uSKo9CbCktX28O51 +wsAkEKOvNcbEzW897EPDQqoFdTCz0saDTVeThjteBmSYXn5MHj8fiWn0e4Q1EZ7LM7x jrkCahK4ICAgxMTRYNXA93+jEQnAv7rHTBpVWYvItytfe7F8C8gLDLOC2FMLK6w6prUj EGw2LBxg8r7DIZVXe8/ajGuhcfyQbFMhUuAbU0XUrNrE0155jxzOcdLJzaH7+BQYoSe+ 6XEDeyKQ1J3YsAwUkSpdMpAWQZs+TvrLLFtoCugWaahiJYycTptgorVCeYSFOwI7TsFl l+hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/WfPFIvXQkUy4+HZsCcjoOy5HXh/OR2xwCOtqD43AE4=; b=orBop8eWRzTLDzt4sIibO74+uSb9fmCVn4CAJ7OUyLEC/ypDvzaK8P66FuNMkoyXCe xaoXbPYNhnFFldK5GkvLibDacxvrHN/jAH9Nyn25Ax3G8y6T9FtkWrtkRVV4EbX1Pnpw vCsxu7uEFq6Afl0zJZJuiY0/LTMhXl5aBABb5X4sGU5Wod4PskKfeeIPRzVYuvpVeMHO 5e6m/ZUzCqkOWrO+TJZEXX/UlKuZukseZ/gtdmpUJrXzTRo+iI4/EsIVaHxBNqpvHOs9 JDP8JTibQhafOt/Wau9WWvVnnvCtdSMqAdB+kaIjqryGlAWJZJOmUbdg365H9oNJktSK TFBQ== X-Gm-Message-State: ANoB5pnk6O9HSAM4d0tA62LoMxEqqQ1Rk/nB0GaPoGPemhARN4hQoSBq 1JfDcHcgr8Ar48bgsW29zYOkxw== X-Google-Smtp-Source: AA0mqf4jxSywcBqwD02kLxE1mauRD2tbT4mXFuMK2P6OZ3jYffHhwCnVXNLquJaHNL8fzoH3Foy1fA== X-Received: by 2002:a5d:6409:0:b0:241:f7ae:b1dd with SMTP id z9-20020a5d6409000000b00241f7aeb1ddmr7131169wru.138.1669389087744; Fri, 25 Nov 2022 07:11:27 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:27 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:17 +0100 Subject: [PATCH v6 06/10] dt-bindings: mfd: mediatek: Add bindings for MT6357 PMIC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-6-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=3860; i=amergnat@baylibre.com; h=from:subject:message-id; bh=hsHJv7tXwGtDI1+UamHOo/TefFAouJ5xvx7nyDsqMfU=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsX/pZnd9dSqEQRhOJBuPEJnpnh/RqRO18ivjZi 9fbakmCJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFwAKCRArRkmdfjHURVZQEA DDNYSSMiJ3lzTJ50OXfaQgj/FSv3bSM7tetVpMTLXk4uizebewWfqZ/8gek76u6K6I3kiTea8srWbl 4DaXtUAP7PI9rTS7MhX8PG5FaKbElkLXTL8pCa5KhRlFnB52tpHhMVgh17PsbMkNbL5u2fAqn1WspR qqMIBASLied/bQ9ix5YDJ2Uq28bPqBR7/ooxMb1dXh6wSXvRY6Pea+ZUcCjtLCeVtOZEfCBeAHKJrJ uxafx2C5sHdhlh/4Nqa2iO9uDLD8/OGfJ5LsUQJxyl45C2RxrnQq27GJLWJD+vCdObuJJG7iyGLquZ L73uTAYMtLIbzFPEIe0okMQIrVRlXwcEzsHMW7SyKAzPSNggx49IvO/8g6B6ybz+dYq+/4HVv6gixl 2AxrNBUX9OeceSG4ix2GcKi0AGgo6m4LW3uptSnWWBki9bEoCVqgJ1HjjTgFsKnoczc65JTH6WKPG0 gd/x5CoyhwhE0zOTXGGUZNiFDuwLYsXya6y6I660rtlsSG7fOSh4l10A7PWzAHuGL/TfH5+Rj7T7pR IohWUhVIjvcf+qMQFfrLUMHvAu/yUGUlglxftIKaQ1HNo7Q5PGZHekCoYGChCBFqMYxRRedz9st/4p kWfOoNAXjTyLZbrWLC77sffUr9yPxplF4Rk0FgKVFbWBeP65fODCyFAsp0EQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently, almost all MT63XX PMIC are documented mfd/mt6397.txt. Unfortunately, the PMICs haven't always similar HW sub-features. To have a better human readable schema, I chose to make one PMIC schema to match the exact HW capabilities instead of convert mt6397.txt to mediatek,mt63xx.yaml and put a bunch of properties behind "if contain ... then ..." - add interrupt property - change property refs to match with new yaml documentation Signed-off-by: Alexandre Mergnat Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/mfd/mediatek,mt6357.yaml | 105 +++++++++++++++++= ++++ 1 file changed, 105 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml b/D= ocumentation/devicetree/bindings/mfd/mediatek,mt6357.yaml new file mode 100644 index 000000000000..2aa8025d1e24 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mediatek,mt6357.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6357 PMIC + +maintainers: + - Flora Fu + - Alexandre Mergnat + +description: | + MT6357 is a power management system chip containing 5 buck + converters and 29 LDOs. Supported features are audio codec, + USB battery charging, fuel gauge, RTC + + This is a multifunction device with the following sub modules: + - Regulator + - RTC + - Keys + + It is interfaced to host controller using SPI interface by a proprietary= hardware + called PMIC wrapper or pwrap. This MFD is a child device of pwrap. + See the following for pwrap node definitions: + Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml + +properties: + compatible: + const: mediatek,mt6357 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + regulators: + type: object + $ref: /schemas/regulator/mediatek,mt6357-regulator.yaml + description: + List of MT6357 BUCKs and LDOs regulators. + + rtc: + type: object + $ref: /schemas/rtc/mediatek,mt6397-rtc.yaml + description: + MT6357 Real Time Clock. + + keys: + type: object + $ref: /schemas/input/mediatek,pmic-keys.yaml + description: + MT6357 power and home keys. + +required: + - compatible + - regulators + +additionalProperties: false + +examples: + - | + #include + + pwrap { + pmic { + compatible =3D "mediatek,mt6357"; + + interrupt-parent =3D <&pio>; + interrupts =3D <145 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells =3D <2>; + + regulators { + mt6357_vproc_reg: buck-vproc { + regulator-name =3D "vproc"; + regulator-min-microvolt =3D <518750>; + regulator-max-microvolt =3D <1312500>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <220>; + regulator-always-on; + }; + + // ... + + mt6357_vusb33_reg: ldo-vusb33 { + regulator-name =3D "vusb33"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3100000>; + regulator-enable-ramp-delay =3D <264>; + }; + }; + + rtc { + compatible =3D "mediatek,mt6357-rtc"; + }; + + keys { + compatible =3D "mediatek,mt6357-keys"; + }; + }; + }; --=20 b4 0.10.1 From nobody Sat Sep 21 09:39:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F3ABC4332F for ; Fri, 25 Nov 2022 15:12:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230354AbiKYPMH (ORCPT ); Fri, 25 Nov 2022 10:12:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230248AbiKYPLv (ORCPT ); Fri, 25 Nov 2022 10:11:51 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F94141982 for ; Fri, 25 Nov 2022 07:11:30 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id i12so7257512wrb.0 for ; Fri, 25 Nov 2022 07:11:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=D/qGjMKoEF7UDLliJtrbx4rWqxj8RHaEUJHMJYnhdEk=; b=FunvwomMzazOiQHP9qjCeutiSj78INhnnswMu9jRrTVOSjAFlaKYxWo7ImMhfIvYZO So1dGYemTGTky64QkEVbNSBzkLAh2NBEpvPFTkWy7eeGtd1Mr+8Bo8ICx+AMWjVJeeFO YDQc6yIbf7q5E7Pjy1g7sJMPvXCkCU7x/9cAyMd2dMf6yhtx19JaT+f8G2clhIr/rECV +VN3ya4t/vxPEUebs7bEXzzMyUjvmVW3OimMLwrXL1dNqY2ovWwUTSccsRwABZCZjphq kWwCSdk/Ia7qTa1RnLytfhBgUiJlILGrrn3TOppX1xoJu5AqpbzKv2ukGmrttpYG6GF1 ockg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D/qGjMKoEF7UDLliJtrbx4rWqxj8RHaEUJHMJYnhdEk=; b=Ufr3gRgLCnfrwhdAEXTDdVDGo1BXK07SLiFt/7iLi/dpRuDX+/sJbpJ3UQyImiEDGm QhYSFS9Cegh2qGe8ioCmbMV4I2QWep30GLb8zydTalxCO8jO+5K3nSWOEAThcUaj30jn Nlfz0qx/xdLyJCz3g9tgE8DW37uCqkI5St1D+p6G6gghmER2GLa4hgQuI9nhBRVkdWJJ NvB1faXU2t6jCpw5JtClUP5dTMQXhYi/vl90wxkee0p5yTXdaRR9PWLIOPI8i8pq9PS8 5vd/aAxhVJnyY3haCpEIiQ7uvqlO6Dh7gBvtNP2IYwcvj4D/H32bnR+8vF2P4BoTVv6Q pXKg== X-Gm-Message-State: ANoB5pnt8/6UiRHITj9XQ2QnMIyumLw8GW4n5QQWqSmF/0YWxIVaz+JG he5wnwBmK3z2axXtOvwKw7aU0g== X-Google-Smtp-Source: AA0mqf46m5/6QUU4T4g/4nUu+fFMz6S02mOIp/205JUHc3bTBuU1MmMK0hz7g+iGfTFHme0vn5ab2w== X-Received: by 2002:a05:6000:1d92:b0:241:6e0a:bfe6 with SMTP id bk18-20020a0560001d9200b002416e0abfe6mr15597315wrb.34.1669389088896; Fri, 25 Nov 2022 07:11:28 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:28 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:18 +0100 Subject: [PATCH v6 07/10] arm64: dts: mt6358: change node names MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-7-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1088; i=amergnat@baylibre.com; h=from:subject:message-id; bh=0w3mp8M+1h003hGCAyGu3KsDIgwbdfb6BOTNA6p/zCk=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsXiaEwliHNuhNheU+36o3pNrBgk4Gv1o/ishDA jjUr+QuJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFwAKCRArRkmdfjHURY0zD/ 4g1XdePNaAEhYmAPAZwxgsV8yEQqZY0CP2rp1y/DApiMmbGJHpJD/BHm3+rHIQgJD2NPuJcqW+LgfJ UYy7gV+YrcCu3woZmwQYAjbxDTOPCd/6gtGRpVSPD7I5RX0nHxdvJnXUz7HSx1QT78r6Rk6ZnMc7VD 4OCSMuLKABzsY+BAqLLYLrZsCh6mc9B1AVpSpS7g/rIlGPHzyZ+Hyh6TMRosMd+4mQAqC8JjD4xuku 6RegXsvTxn1mFj6gXvtc2Kg6/DIxO03E1il67dA3jbNlkDiCXSIeIPCcn5Rlvd/MmsCpgB0SBEWBiv gIuhCJn0/kHPMaGQy8pfuUbYIbBSGQCo6wtYQ/r9iYTbchx4MQrly9NsnfpYR7fC/nAofyU1tZuSp4 8N3JRmuc7PoMtauy9MeZC34Df6yKgXps32+UUJfd0RR4LvQSgOU+3a8PhNZtgbn9o4R13ki4H3IhOR hK/IlfvGj2/gx0rhpTi1pTfhLdDHfXRPrllImPBDnF3cfOTlzM8D02Mt3/pnW9ITCRJbAl0Jo7EI4r bu6Ee11cqSZxt7FmEG6bUHQZ2whgnjj2/BBrFTMJbWY22wSTB2fZEtVbTurlX+slo/KRUhuYhmyfp2 TmVta7emISErzdz9F7YgG5rtKOdfrMANuq89yrx0pI5py+5s9xHqAsttUvmw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Change the node name from "mt6358" to "pmic", "mt6358rtc" to "rtc" and "mt6358keys" to "keys" to be consistent with the generic names recommendati= on. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt6358.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts= /mediatek/mt6358.dtsi index 98f3b0e0c9f6..b605313bed99 100644 --- a/arch/arm64/boot/dts/mediatek/mt6358.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi @@ -5,7 +5,7 @@ #include =20 &pwrap { - pmic: mt6358 { + pmic: pmic { compatible =3D "mediatek,mt6358"; interrupt-controller; interrupt-parent =3D <&pio>; @@ -355,11 +355,11 @@ mt6358_vsim2_reg: ldo_vsim2 { }; }; =20 - mt6358rtc: mt6358rtc { + mt6358rtc: rtc { compatible =3D "mediatek,mt6358-rtc"; }; =20 - mt6358keys: mt6358keys { + mt6358keys: keys { compatible =3D "mediatek,mt6358-keys"; power { linux,keycodes =3D ; --=20 b4 0.10.1 From nobody Sat Sep 21 09:39:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75ED9C43217 for ; Fri, 25 Nov 2022 15:12:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230360AbiKYPMK (ORCPT ); Fri, 25 Nov 2022 10:12:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230266AbiKYPLw (ORCPT ); Fri, 25 Nov 2022 10:11:52 -0500 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81ADF42997 for ; Fri, 25 Nov 2022 07:11:31 -0800 (PST) Received: by mail-wr1-x42e.google.com with SMTP id x17so7188220wrn.6 for ; Fri, 25 Nov 2022 07:11:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wK0CnlZOX9M/iM8SewTczZ0sLEDRfVMf5U5O9npWUVY=; b=AjMhDKUSXlx31DgwVj59ktOHNOh5SInBB3Ica2qU2iTSFLl0FwgV5TPGAfJdydc+KJ n95nGRnjpEYMuNDi51sGoLqUpiUkP5MK2WGX6s/JbwPTziQPppNxTM9sFxdB/hWC3WXB oth989ifui1J3CNEn8NUdXx2nNr1MOLgaF9nWIW0QXBvQxjqDtphj2q4g7GwmxrlvLC8 bewP7mKt06c0/hh+nio3CDoQzJHYRkRm/WyMY5ZdE4saUGPsVPGgr7w7SXI4pGQRTBII O0kM4fldfkHrqeRTbInIEFAS01RUwVUzzmWGYO7/eqpKytOJMn4tQZL1EwIvLpfXivaI yF6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wK0CnlZOX9M/iM8SewTczZ0sLEDRfVMf5U5O9npWUVY=; b=JS1YnPvUVcbh+wfXxLbE1Fd4smJ7Kh2waNVvRyLoVxV7e7hmuyMEnEfjXJWhX+nMDa /61BAX7P73s2NeczeTvSMyvujS6wOpGETPwgTlpxUxc5rZ+mpsAWFT1FRYrKdLHVKB1Y IJoAKsPGvu8JDGDZCm5dAwErl/kzVpbljpr16VrEcXdT4QcbarjzSmCr1N8qm/xTe8nk G+3OXNa0tOKXP9PnNd0fY5ARvVR8IunYUNYZcEsvw6KY1CNwAoCP58R3XOzJSO7TEbWE upG4wrhSYD3GNcaV3NaO8E4Kg1sXItdK6mBZuuipUvus8vNsOF0qiX4x9VcI8GnF8ofd 8DUg== X-Gm-Message-State: ANoB5pmixJ7ge8EYEB4kkZe7gdhxoL4WEQ+8kAcSs2hSI/WDSnLWDCdQ oQxPqk0QJyU+lGAR/SBr57mc0g== X-Google-Smtp-Source: AA0mqf4T1yb35EpIiyEZ2qo9ePUN9VXa08cg2ZMi6OWKY9wZcGVA3BSKqkuf73pxaZ1l/ntdNVH30Q== X-Received: by 2002:a5d:6183:0:b0:241:d386:f6d4 with SMTP id j3-20020a5d6183000000b00241d386f6d4mr13377172wru.707.1669389089975; Fri, 25 Nov 2022 07:11:29 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:29 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:19 +0100 Subject: [PATCH v6 08/10] arm64: dts: mt8173: change node name MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-8-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=1289; i=amergnat@baylibre.com; h=from:subject:message-id; bh=sciAdvxNeIHiHj/noxHzFC381BQRCLfnWiRAfVX/Ztg=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsXQ7iac4y/5bvYvfe1/XziFY5k1T+DtRd9Rmg3 xQh0OBSJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFwAKCRArRkmdfjHURWflD/ 4nuSKT8b5l8xDKS+q7gXOeVYhoAwNCl/KmRiV4oy4YMsbQpfEAMAYjBGM47Pwn6UdymVpk7+HeDXqx qRP2Aq2917yfRFh5xLKCEzpwIxTzQYu2xuCgBy1QCJ9dEAoK4FlzZNC4pkd4VVt2Eme2EXMkjhECQG u/QiQOridfxML1KnAkkl2gmaPKXc6g1nupW5ki8kNUy51+h98SExHp/K3ep29xfj/XALTbSuO9AI+e oW4Fx/T+Frbj/YS9tLQ8kh43rvv0hrkq7D9X0j50QsQb6cYHLuxTTIigkNCXnKJ406XHi9z6laXRZ2 r292CcCk2xCCHqUlHusYpP8lV/LOj17WT1m+E4eBbWUQIe8aw/c+Yrtk16Jf76Eq3y5D5pKpQ1loJ5 0wd/sEMOJ/hAmxN2ao/LvR/qOWqyaw4mifXIvebOlTys1NYhj0IZS8Aoi6I2Bg2nGBCJvqYUYrKrVZ ZKTwod6OyfzPOlazL5rXpJACTsIpMIu4Yaq0lbD8fBR6sfwE8DAwy6tiNY+8sSv3k/wHjy2rnWohp0 EE8bkTdxUNg0XmaddcRbv0jJzm7S9abQyz1D0T2IkkLREXgkw5H2cbf0zIuCKZ872BAySimW7KxQ8G PZ1gATf0/CAjzm2pA6SSG7WzbmR/NgOLj4S3YD8Dp2TihgbAfrPanSLGskhQ== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org - Change the node name from "mt6397" to "pmic" to be consistent with the generic names recommendation. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot= /dts/mediatek/mt8173-elm.dtsi index e21feb85d822..a8f5c48e1782 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -913,7 +913,7 @@ &pwm0 { }; =20 &pwrap { - pmic: mt6397 { + pmic: pmic { compatible =3D "mediatek,mt6397"; #address-cells =3D <1>; #size-cells =3D <1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/= dts/mediatek/mt8173-evb.dts index 0b5f154007be..755df5694234 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -300,7 +300,7 @@ &pwrap { /* Only MT8173 E1 needs USB power domain */ power-domains =3D <&spm MT8173_POWER_DOMAIN_USB>; =20 - pmic: mt6397 { + pmic: pmic { compatible =3D "mediatek,mt6397"; interrupt-parent =3D <&pio>; interrupts =3D <11 IRQ_TYPE_LEVEL_HIGH>; --=20 b4 0.10.1 From nobody Sat Sep 21 09:39:06 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AC97C43219 for ; Fri, 25 Nov 2022 15:12:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230371AbiKYPMR (ORCPT ); Fri, 25 Nov 2022 10:12:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230315AbiKYPLx (ORCPT ); Fri, 25 Nov 2022 10:11:53 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C274743878 for ; Fri, 25 Nov 2022 07:11:32 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id c65-20020a1c3544000000b003cfffd00fc0so6434076wma.1 for ; Fri, 25 Nov 2022 07:11:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=I+WYtC3mBmE4HBeCSm4jFYtF3t8u3124l8X3DjUJU0g=; b=tKdwOqeUUtpYkHxhDIic6WxhmF7Sm/o3BNoVWjVyf24t8qGEmvAULev1njq22iu2h+ 9FiNdxVdSVtU1pB34Wzn8jdN8+Y3Xixs+/5/IkzmX8kNsdFX1lHizerpNcSFw17JGkje ZBxtdboqcbBeXGgvWAzyh39h+mutnO1ZP2KiX8wHE9G63Pp19YHyh39BZAnK3QtDOceG DquhBRxTEjjLqY/Ip32s8yci5Z6nTYDYXbIMbquhiZXF7av7YjtLlSSr38fa3pJqG1ZT pFJkxZQFznuUg6vD2liRoABbFSFkCfXORcizC7tenu15jQ4JxmYSvDPYG1pcpMXrDkcD acUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I+WYtC3mBmE4HBeCSm4jFYtF3t8u3124l8X3DjUJU0g=; b=CQ4uE9bam3QdA2ae29ZAeupxX1SSZVpKyVP+zqCl6Oz+B67h78ag9Dvbt4iqvOVUa1 XJN9KGWx7MfE6k3aFlfVAjW3oP69FiZh+0YgTLzdhnVFGq774k//BbtwLtY3JFTp9tKO cAHUH00lsC57WooZ0/lS8zurrMDsczzEn77GEMdJ+YwRy+AINO9+J0W8gTcfFsv7FLyZ K76LKx6DnduAvbbrj3+dYu0xP01n+oObcY6r81lSXYt33l8bxu2KPLxp0D1FrXc9rxkO yR+1gCzeLk1dc9IzKkr3ffsaiGXj1VEtAzZKggoYCAaOvXZdtzJvbEBCylbV/knOgX8o 4bcg== X-Gm-Message-State: ANoB5plooYysiklRIByd2iy+ToPc8xrU6rlK/dirXxMA8r000t6IkmDn BexI3QPMjHDc4ACIlEBo1samtA== X-Google-Smtp-Source: AA0mqf4ryQtntPLvq7v934Ywv5cEcthT5nQkZmHhQ13Wvf4EawNAMa2N8h+HJB9NFNsm4DAEEKRFqQ== X-Received: by 2002:a1c:ed17:0:b0:3cf:cfce:9d9e with SMTP id l23-20020a1ced17000000b003cfcfce9d9emr16152932wmh.66.1669389091172; Fri, 25 Nov 2022 07:11:31 -0800 (PST) Received: from [127.0.1.1] (158.22.5.93.rev.sfr.net. [93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:30 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:20 +0100 Subject: [PATCH v6 09/10] regulator: add mt6357 regulator MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-9-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=15592; i=amergnat@baylibre.com; h=from:subject:message-id; bh=FjHm7XarKGTIp+0w1oTz5v6T1oFuXdTPbkzeC2DNWpw=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsXKXtTvyC3B5v+S5OaWp+Vgpu5muqeIyubu6bb h7WDpWiJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFwAKCRArRkmdfjHURdEhEA CYsj/PhOobj/WJ12f9hcGlO2eH8uRd9qKcVhL1tgOuvSiCxEsxrukjGEF8pPJ4Gm8mIXgm9jJzuMVK am4RKjK9leCoUSNrmMw1jDn+vwad+dm+Z7zhzkwFESij2ryfBpqc1V7OrIDFEyjAZmI4qO21+QxjkM ++UwegzyKHtBZRUQGm0NI266ZIa58oM5RjlSBFVT85WZNPIvVr8M0z64VIesHINzoS2y4+XdywGq81 w64U9tbnMJ/OT8imt+kR03jKQsXiWHj8coXrbVjfJNDta3ZEONyiuQxlMkyo2MSUzMkmD1BO9Acuzx sBsReGt5Wb7k2LbSLuZfiL7CvragmELy47F4Vy7jD6IUcCTt1bX4Rdnx84S8LFSIOVfzF8Vnjm2/1a +1NouE6OXjTu24CdE3iGCNw9jhZ5VC3mlVArQliavtPkgOsftweW/Is6GKB8SV1QuaG4zMaF8eo+5b 8+zpIvf1/7yN8uoiJdVWcrJ6TpapcZ8kBTCnyX60RPorvya3iDksv7cgBmIYIq9ZKc7toCO20lWm8U STj8dTW7mTjXnQIJooi4Oz7RNjeVfO7FbKDFr5FJHPTEHgjHqOV3goD/NHSzRnjNGcUqAzIAGjEtyG ZiUnPv13m2sjBssplmrM9FE3DDEvPM3kudbGv4HReB+uv1Dy14bHL192yrtw== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add regulator driver for the MT6357 PMIC. Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Alexandre Mergnat --- drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + drivers/regulator/mt6357-regulator.c | 453 +++++++++++++++++++++++++= ++++ include/linux/regulator/mt6357-regulator.h | 51 ++++ 4 files changed, 514 insertions(+) diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig index 070e4403c6c2..a659a57438f4 100644 --- a/drivers/regulator/Kconfig +++ b/drivers/regulator/Kconfig @@ -805,6 +805,15 @@ config REGULATOR_MT6332 This driver supports the control of different power rails of device through regulator interface =20 +config REGULATOR_MT6357 + tristate "MediaTek MT6357 PMIC" + depends on MFD_MT6397 + help + Say y here to select this option to enable the power regulator of + MediaTek MT6357 PMIC. + This driver supports the control of different power rails of device + through regulator interface. + config REGULATOR_MT6358 tristate "MediaTek MT6358 PMIC" depends on MFD_MT6397 diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile index 5962307e1130..e4d67b7b1af6 100644 --- a/drivers/regulator/Makefile +++ b/drivers/regulator/Makefile @@ -97,6 +97,7 @@ obj-$(CONFIG_REGULATOR_MT6315) +=3D mt6315-regulator.o obj-$(CONFIG_REGULATOR_MT6323) +=3D mt6323-regulator.o obj-$(CONFIG_REGULATOR_MT6331) +=3D mt6331-regulator.o obj-$(CONFIG_REGULATOR_MT6332) +=3D mt6332-regulator.o +obj-$(CONFIG_REGULATOR_MT6357) +=3D mt6357-regulator.o obj-$(CONFIG_REGULATOR_MT6358) +=3D mt6358-regulator.o obj-$(CONFIG_REGULATOR_MT6359) +=3D mt6359-regulator.o obj-$(CONFIG_REGULATOR_MT6360) +=3D mt6360-regulator.o diff --git a/drivers/regulator/mt6357-regulator.c b/drivers/regulator/mt635= 7-regulator.c new file mode 100644 index 000000000000..b2352b96aed2 --- /dev/null +++ b/drivers/regulator/mt6357-regulator.c @@ -0,0 +1,453 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2022 MediaTek Inc. +// Copyright (c) 2022 BayLibre, SAS. +// Author: Chen Zhong +// Author: Fabien Parent +// Author: Alexandre Mergnat +// +// Based on mt6397-regulator.c +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * MT6357 regulators' information + * + * @desc: standard fields of regulator description. + * @da_vsel_reg: Monitor register for query buck's voltage. + * @da_vsel_mask: Mask for query buck's voltage. + */ +struct mt6357_regulator_info { + struct regulator_desc desc; + u32 da_vsel_reg; + u32 da_vsel_mask; +}; + +#define MT6357_BUCK(match, vreg, min, max, step, \ + volt_ranges, vosel_reg, vosel_mask, _da_vsel_mask) \ +[MT6357_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D "regulators", \ + .ops =3D &mt6357_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6357_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ((max) - (min)) / (step) + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel_reg, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D MT6357_BUCK_##vreg##_CON0, \ + .enable_mask =3D BIT(0), \ + }, \ + .da_vsel_reg =3D MT6357_BUCK_##vreg##_DBG0, \ + .da_vsel_mask =3D vosel_mask, \ +} + +#define MT6357_LDO(match, vreg, ldo_volt_table, \ + enreg, vosel, vosel_mask) \ +[MT6357_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D "regulators", \ + .ops =3D &mt6357_volt_table_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6357_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ARRAY_SIZE(ldo_volt_table), \ + .volt_table =3D ldo_volt_table, \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + }, \ +} + +#define MT6357_LDO1(match, vreg, min, max, step, volt_ranges, \ + enreg, vosel, vosel_mask) \ +[MT6357_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D "regulators", \ + .ops =3D &mt6357_volt_range_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6357_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D ((max) - (min)) / (step) + 1, \ + .linear_ranges =3D volt_ranges, \ + .n_linear_ranges =3D ARRAY_SIZE(volt_ranges), \ + .vsel_reg =3D vosel, \ + .vsel_mask =3D vosel_mask, \ + .enable_reg =3D enreg, \ + .enable_mask =3D BIT(0), \ + }, \ + .da_vsel_reg =3D MT6357_LDO_##vreg##_DBG0, \ + .da_vsel_mask =3D 0x7f00, \ +} + +#define MT6357_REG_FIXED(match, vreg, volt) \ +[MT6357_ID_##vreg] =3D { \ + .desc =3D { \ + .name =3D #vreg, \ + .of_match =3D of_match_ptr(match), \ + .regulators_node =3D "regulators", \ + .ops =3D &mt6357_volt_fixed_ops, \ + .type =3D REGULATOR_VOLTAGE, \ + .id =3D MT6357_ID_##vreg, \ + .owner =3D THIS_MODULE, \ + .n_voltages =3D 1, \ + .enable_reg =3D MT6357_LDO_##vreg##_CON0, \ + .enable_mask =3D BIT(0), \ + .min_uV =3D volt, \ + }, \ +} + +/** + * mt6357_get_buck_voltage_sel - get_voltage_sel for regmap users + * + * @rdev: regulator to operate on + * + * Regulators that use regmap for their register I/O can set the + * da_vsel_reg and da_vsel_mask fields in the info structure and + * then use this as their get_voltage_vsel operation. + */ +static int mt6357_get_buck_voltage_sel(struct regulator_dev *rdev) +{ + int ret, regval; + struct mt6357_regulator_info *info =3D rdev_get_drvdata(rdev); + + ret =3D regmap_read(rdev->regmap, info->da_vsel_reg, ®val); + if (ret !=3D 0) { + dev_err(&rdev->dev, + "Failed to get mt6357 Buck %s vsel reg: %d\n", + info->desc.name, ret); + return ret; + } + + regval &=3D info->da_vsel_mask; + regval >>=3D ffs(info->da_vsel_mask) - 1; + + return regval; +} + +static const struct regulator_ops mt6357_volt_range_ops =3D { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D mt6357_get_buck_voltage_sel, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, +}; + +static const struct regulator_ops mt6357_volt_table_ops =3D { + .list_voltage =3D regulator_list_voltage_table, + .map_voltage =3D regulator_map_voltage_iterate, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, +}; + +static const struct regulator_ops mt6357_volt_fixed_ops =3D { + .list_voltage =3D regulator_list_voltage_linear, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .is_enabled =3D regulator_is_enabled_regmap, +}; + +static const int vxo22_voltages[] =3D { + 2200000, + 0, + 2400000, +}; + +static const int vefuse_voltages[] =3D { + 1200000, + 1300000, + 1500000, + 0, + 1800000, + 0, + 0, + 0, + 0, + 2800000, + 2900000, + 3000000, + 0, + 3300000, +}; + +static const int vcn33_voltages[] =3D { + 0, + 3300000, + 3400000, + 3500000, +}; + +static const int vcama_voltages[] =3D { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 2500000, + 0, + 0, + 2800000, +}; + +static const int vcamd_voltages[] =3D { + 0, + 0, + 0, + 0, + 1000000, + 1100000, + 1200000, + 1300000, + 0, + 1500000, + 0, + 0, + 1800000, +}; + +static const int vldo28_voltages[] =3D { + 0, + 2800000, + 0, + 3000000, +}; + +static const int vdram_voltages[] =3D { + 0, + 1100000, + 1200000, +}; + +static const int vsim_voltages[] =3D { + 0, + 0, + 0, + 1700000, + 1800000, + 0, + 0, + 0, + 2700000, + 0, + 0, + 3000000, + 3100000, +}; + +static const int vibr_voltages[] =3D { + 1200000, + 1300000, + 1500000, + 0, + 1800000, + 2000000, + 0, + 0, + 0, + 2800000, + 0, + 3000000, + 0, + 3300000, +}; + +static const int vmc_voltages[] =3D { + 0, + 0, + 0, + 0, + 1800000, + 0, + 0, + 0, + 0, + 0, + 2900000, + 3000000, + 0, + 3300000, +}; + +static const int vmch_voltages[] =3D { + 0, + 0, + 2900000, + 3000000, + 0, + 3300000, +}; + +static const int vemc_voltages[] =3D { + 0, + 0, + 2900000, + 3000000, + 0, + 3300000, +}; + +static const int vusb_voltages[] =3D { + 0, + 0, + 0, + 3000000, + 3100000, +}; + +static const struct linear_range buck_volt_range1[] =3D { + REGULATOR_LINEAR_RANGE(518750, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range2[] =3D { + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), +}; + +static const struct linear_range buck_volt_range3[] =3D { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct linear_range buck_volt_range4[] =3D { + REGULATOR_LINEAR_RANGE(1200000, 0, 0x7f, 12500), +}; + +/* The array is indexed by id(MT6357_ID_XXX) */ +static struct mt6357_regulator_info mt6357_regulators[] =3D { + /* Bucks */ + MT6357_BUCK("buck-vcore", VCORE, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VCORE_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vproc", VPROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VPROC_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vmodem", VMODEM, 500000, 1293750, 6250, + buck_volt_range2, MT6357_BUCK_VMODEM_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vpa", VPA, 500000, 3650000, 50000, + buck_volt_range3, MT6357_BUCK_VPA_CON1, 0x3f, 0x3f), + MT6357_BUCK("buck-vs1", VS1, 1200000, 2787500, 12500, + buck_volt_range4, MT6357_BUCK_VS1_ELR0, 0x7f, 0x7f), + + /* LDOs */ + MT6357_LDO("ldo-vcama", VCAMA, vcama_voltages, + MT6357_LDO_VCAMA_CON0, MT6357_VCAMA_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vcamd", VCAMD, vcamd_voltages, + MT6357_LDO_VCAMD_CON0, MT6357_VCAMD_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vcn33-bt", VCN33_BT, vcn33_voltages, + MT6357_LDO_VCN33_CON0_0, MT6357_VCN33_ANA_CON0, 0x300), + MT6357_LDO("ldo-vcn33-wifi", VCN33_WIFI, vcn33_voltages, + MT6357_LDO_VCN33_CON0_1, MT6357_VCN33_ANA_CON0, 0x300), + MT6357_LDO("ldo-vdram", VDRAM, vdram_voltages, + MT6357_LDO_VDRAM_CON0, MT6357_VDRAM_ELR_2, 0x300), + MT6357_LDO("ldo-vefuse", VEFUSE, vefuse_voltages, + MT6357_LDO_VEFUSE_CON0, MT6357_VEFUSE_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vemc", VEMC, vemc_voltages, + MT6357_LDO_VEMC_CON0, MT6357_VEMC_ANA_CON0, 0x700), + MT6357_LDO("ldo-vibr", VIBR, vibr_voltages, + MT6357_LDO_VIBR_CON0, MT6357_VIBR_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vldo28", VLDO28, vldo28_voltages, + MT6357_LDO_VLDO28_CON0_0, MT6357_VLDO28_ANA_CON0, 0x300), + MT6357_LDO("ldo-vmc", VMC, vmc_voltages, + MT6357_LDO_VMC_CON0, MT6357_VMC_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vmch", VMCH, vmch_voltages, + MT6357_LDO_VMCH_CON0, MT6357_VMCH_ANA_CON0, 0x700), + MT6357_LDO("ldo-vsim1", VSIM1, vsim_voltages, + MT6357_LDO_VSIM1_CON0, MT6357_VSIM1_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vsim2", VSIM2, vsim_voltages, + MT6357_LDO_VSIM2_CON0, MT6357_VSIM2_ANA_CON0, 0xf00), + MT6357_LDO("ldo-vusb33", VUSB33, vusb_voltages, + MT6357_LDO_VUSB33_CON0_0, MT6357_VUSB33_ANA_CON0, 0x700), + MT6357_LDO("ldo-vxo22", VXO22, vxo22_voltages, + MT6357_LDO_VXO22_CON0, MT6357_VXO22_ANA_CON0, 0x300), + + MT6357_LDO1("ldo-vsram-proc", VSRAM_PROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_PROC_CON0, + MT6357_LDO_VSRAM_CON0, 0x7f00), + MT6357_LDO1("ldo-vsram-others", VSRAM_OTHERS, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_OTHERS_CON0, + MT6357_LDO_VSRAM_CON1, 0x7f00), + + MT6357_REG_FIXED("ldo-vaud28", VAUD28, 2800000), + MT6357_REG_FIXED("ldo-vaux18", VAUX18, 1800000), + MT6357_REG_FIXED("ldo-vcamio18", VCAMIO, 1800000), + MT6357_REG_FIXED("ldo-vcn18", VCN18, 1800000), + MT6357_REG_FIXED("ldo-vcn28", VCN28, 2800000), + MT6357_REG_FIXED("ldo-vfe28", VFE28, 2800000), + MT6357_REG_FIXED("ldo-vio18", VIO18, 1800000), + MT6357_REG_FIXED("ldo-vio28", VIO28, 2800000), + MT6357_REG_FIXED("ldo-vrf12", VRF12, 1200000), + MT6357_REG_FIXED("ldo-vrf18", VRF18, 1800000), +}; + +static int mt6357_regulator_probe(struct platform_device *pdev) +{ + struct mt6397_chip *mt6357 =3D dev_get_drvdata(pdev->dev.parent); + struct regulator_config config =3D {}; + struct regulator_dev *rdev; + int i; + + pdev->dev.of_node =3D pdev->dev.parent->of_node; + + for (i =3D 0; i < MT6357_MAX_REGULATOR; i++) { + config.dev =3D &pdev->dev; + config.driver_data =3D &mt6357_regulators[i]; + config.regmap =3D mt6357->regmap; + + rdev =3D devm_regulator_register(&pdev->dev, + &mt6357_regulators[i].desc, + &config); + if (IS_ERR(rdev)) { + dev_err(&pdev->dev, "failed to register %s\n", + mt6357_regulators[i].desc.name); + return PTR_ERR(rdev); + } + } + + return 0; +} + +static const struct platform_device_id mt6357_platform_ids[] =3D { + { "mt6357-regulator" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, mt6357_platform_ids); + +static struct platform_driver mt6357_regulator_driver =3D { + .driver =3D { + .name =3D "mt6357-regulator", + }, + .probe =3D mt6357_regulator_probe, + .id_table =3D mt6357_platform_ids, +}; + +module_platform_driver(mt6357_regulator_driver); + +MODULE_AUTHOR("Chen Zhong "); +MODULE_AUTHOR("Fabien Parent "); +MODULE_AUTHOR("Alexandre Mergnat "); +MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6357 PMIC"); +MODULE_LICENSE("GPL"); diff --git a/include/linux/regulator/mt6357-regulator.h b/include/linux/reg= ulator/mt6357-regulator.h new file mode 100644 index 000000000000..238b1ee77ea6 --- /dev/null +++ b/include/linux/regulator/mt6357-regulator.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __LINUX_REGULATOR_MT6357_H +#define __LINUX_REGULATOR_MT6357_H + +enum { + /* Bucks */ + MT6357_ID_VCORE, + MT6357_ID_VMODEM, + MT6357_ID_VPA, + MT6357_ID_VPROC, + MT6357_ID_VS1, + + /* LDOs */ + MT6357_ID_VAUX18, + MT6357_ID_VAUD28, + MT6357_ID_VCAMA, + MT6357_ID_VCAMD, + MT6357_ID_VCAMIO, + MT6357_ID_VCN18, + MT6357_ID_VCN28, + MT6357_ID_VCN33_BT, + MT6357_ID_VCN33_WIFI, + MT6357_ID_VDRAM, + MT6357_ID_VEFUSE, + MT6357_ID_VEMC, + MT6357_ID_VFE28, + MT6357_ID_VIBR, + MT6357_ID_VIO18, + MT6357_ID_VIO28, + MT6357_ID_VLDO28, + MT6357_ID_VMC, + MT6357_ID_VMCH, + MT6357_ID_VRF12, + MT6357_ID_VRF18, + MT6357_ID_VSIM1, + MT6357_ID_VSIM2, + MT6357_ID_VSRAM_OTHERS, + MT6357_ID_VSRAM_PROC, + MT6357_ID_VUSB33, + MT6357_ID_VXO22, + + MT6357_ID_RG_MAX, +}; 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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id w10-20020a05600c474a00b003b435c41103sm11565885wmo.0.2022.11.25.07.11.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 07:11:32 -0800 (PST) From: Alexandre Mergnat Date: Fri, 25 Nov 2022 16:10:21 +0100 Subject: [PATCH v6 10/10] Input: mtk-pmic-keys: add MT6357 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221005-mt6357-support-v6-10-4f589756befa@baylibre.com> References: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> In-Reply-To: <20221005-mt6357-support-v6-0-4f589756befa@baylibre.com> To: Krzysztof Kozlowski , Sean Wang , Rob Herring , Matthias Brugger , Chen Zhong , Fabien Parent , Alessandro Zummo , Mark Brown , Alexandre Belloni , Flora Fu , Tianping Fang , Pavel Machek , Lee Jones , Liam Girdwood , Dmitry Torokhov Cc: Mattijs Korpershoek , Alexandre Mergnat , Rob Herring , AngeloGioacchino Del Regno , linux-rtc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Fabien Parent , linux-input@vger.kernel.org, devicetree@vger.kernel.org, linux-leds@vger.kernel.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=2028; i=amergnat@baylibre.com; h=from:subject:message-id; bh=K2/LktiwnSqpYUY/NYDB7cyyBwW4Kzl5Gx1VcVhpHIg=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBjgNsXQIa1QEIipiruDB9u/aUJuuWuwrFMsam4SPLK 94W6b/+JAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCY4DbFwAKCRArRkmdfjHURavoEA CgtRyRJ2qwmMDOSz6ZGwn/ZANcUmntlsG2vnP8PVpIhZSEpmpPaOC9xB/4cyr6clGsvKNMESMH+Fqc rJFK0L9bcHTfUlN0fAGTvsyXEReg4k8e93E8QkPUAyLlgxoAM6Qkkxw9GrQyOShb5yXjyq39X1AFKj pGHZCnhO7JtRZkzj9ZUpgs+P2tSXss5FUFGbGco/PHUTrLhoIAU5C43uCE/pn3y9m1jGLPjtJuyV9v 6oCV70JLBrYCph2BNCrQdzD3vr1CzWBRTY0Z8ttPDnvTRWiZRb9/vWs+vb6raYU22UYt08uN8hidp9 oWT/CUu9l3hbh3i0E0a6aMXDNS5kIQBnLYZmfl478RtbxlzmhDA/94aFTLVRC1vEtICMvkfCc3P1z/ wIczGve0zj0fMM2Qh2YFcJmLk+T5N+cBGkAskB57Cct+9R8qKKyIhTeRT2Ljh/yIZsJB3O4Pem8nh8 gnFZ9WAyhkTJXlxv73g71vUG6uPiSKTmMw4P6ONR/Jq6szyRXT+3xUeoqpHX0dwrtBxn9CTl1M4gdM GbjY6xdJlez1nPoAXb8Y2LPaBIFeYsbbVjPpWhwOA/BXsy04UxEibIbNEfnSzwTb05A8O812vSsJaU u/j++N0Vyr0mINa1MQDkFOP4gs/9WWeaKwK7Tf96ZFi53RIYBcVW5VvsulZg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Fabien Parent Add PMIC Keys support on MT6357 SoC. Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Mattijs Korpershoek Acked-by: Dmitry Torokhov Signed-off-by: Alexandre Mergnat --- drivers/input/keyboard/mtk-pmic-keys.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/input/keyboard/mtk-pmic-keys.c b/drivers/input/keyboar= d/mtk-pmic-keys.c index 9b34da0ec260..2a63e0718eb6 100644 --- a/drivers/input/keyboard/mtk-pmic-keys.c +++ b/drivers/input/keyboard/mtk-pmic-keys.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -90,6 +91,19 @@ static const struct mtk_pmic_regs mt6331_regs =3D { .rst_lprst_mask =3D MTK_PMIC_MT6331_RST_DU_MASK, }; =20 +static const struct mtk_pmic_regs mt6357_regs =3D { + .keys_regs[MTK_PMIC_PWRKEY_INDEX] =3D + MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS, + 0x2, MT6357_PSC_TOP_INT_CON0, 0x5, + MTK_PMIC_PWRKEY_RST), + .keys_regs[MTK_PMIC_HOMEKEY_INDEX] =3D + MTK_PMIC_KEYS_REGS(MT6357_TOPSTATUS, + 0x8, MT6357_PSC_TOP_INT_CON0, 0xa, + MTK_PMIC_HOMEKEY_INDEX), + .pmic_rst_reg =3D MT6357_TOP_RST_MISC, + .rst_lprst_mask =3D MTK_PMIC_RST_DU_MASK, +}; + static const struct mtk_pmic_regs mt6358_regs =3D { .keys_regs[MTK_PMIC_PWRKEY_INDEX] =3D MTK_PMIC_KEYS_REGS(MT6358_TOPSTATUS, @@ -276,6 +290,9 @@ static const struct of_device_id of_mtk_pmic_keys_match= _tbl[] =3D { }, { .compatible =3D "mediatek,mt6331-keys", .data =3D &mt6331_regs, + }, { + .compatible =3D "mediatek,mt6357-keys", + .data =3D &mt6357_regs, }, { .compatible =3D "mediatek,mt6358-keys", .data =3D &mt6358_regs, --=20 b4 0.10.1