From: Matthew Gerlach <matthew.gerlach@intel.com> This patchset enhances the definition of the Device Feature Header (DFH) used by the Device Feature List (DFL) bus and then uses the new enhancements in a uart driver. Patch 1 updates the DFL documentation to provide the motivation behind the enhancements to the definition of the DFH. Patch 2 adds the definitions for DFHv1. Patch 3 adds basic support DFHv1. It provides a generic mechanism for describing MSIX interrupts used by a particular feature instance, and it gets the location and size of the feature's register set from DFHv1. Patch 4 adds a DFL uart driver that makes use of the new features of DFHv1. Basheer Ahmed Muddebihal (1): fpga: dfl: Add DFHv1 Register Definitions Matthew Gerlach (3): Documentation: fpga: dfl: Add documentation for DFHv1 fpga: dfl: add basic support for DFHv1 tty: serial: 8250: add DFL bus driver for Altera 16550. Documentation/fpga/dfl.rst | 49 ++++++++ drivers/fpga/dfl.c | 150 +++++++++++++++++------- drivers/fpga/dfl.h | 36 +++++- drivers/tty/serial/8250/8250_dfl.c | 177 +++++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 9 ++ drivers/tty/serial/8250/Makefile | 1 + include/linux/dfl.h | 33 +++++- 7 files changed, 414 insertions(+), 41 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_dfl.c -- 2.25.1 From: Matthew Gerlach <matthew.gerlach@linux.intel.com> Add documentation describing the extensions provided by Version 1 of the Device Feature Header (DFHv1). Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- v3: no change v2: s/GUILD/GUID/ add picture --- Documentation/fpga/dfl.rst | 49 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index XXXXXXX..XXXXXXX 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -XXX,XX +XXX,XX @@ new DFL feature via UIO direct access, its feature id should be added to the driver's id_table. +Extending the Device Feature Header - DFHv1 +=========================================== +The current 8 bytes of the Device Feature Header, hereafter referred to as +to DFHv0, provide very little opportunity for the hardware to describe itself +to software. Version 1 of the Device Feature Header (DFHv1) is being introduced +to provide increased flexibility and extensibility to hardware designs using +Device Feature Lists. The list below describes some of the goals behind the +changes in DFHv1: + +* Provide a standardized mechanism for features to describe + parameters/capabilities to software. +* Standardize the use of a GUID for all DFHv1 types. +* Decouple the location of the DFH from the register space of the feature itself. + +Modeled after PCI Capabilities, DFHv1 Parameters provide a mechanism to associate +a list of parameter values to a particular feature. + +With DFHv0, not all features types contained a GUID. DFHv1 makes the GUID standard +across all types. + +With DFHv0, the register map of a given feature is located immediately following +the DFHv0 in the memory space. With DFHv1, the location of the feature register +map can be specified as an offset to the DFHv1 or as an absolute address. The DFHv1 +structure is shown below: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| + +-----------------------------------------------------------------------+ + |63 GUID_L 0| + +-----------------------------------------------------------------------+ + |63 GUID_H 0| + +-----------------------------------------------------------------------+ + |63 Address/Offset 1| Rel 0| + +-----------------------------------------------------------------------+ + |63 Size of register set 32|Params 31|30 Group 16|15 Instance 0| + +-----------------------------------------------------------------------+ + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + + ... + + +-----------------------------------------------------------------------+ + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration -- 2.25.1 From: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com> This patch adds the definitions for DFHv1 header and related register bitfields. Signed-off-by: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- v3: keep DFHv1 definitions "hidden" in drivers/fpga/dfl.h v2: clean up whitespace and one line comments remove extra space in commit use uniform number of digits in constants don't change copyright date because of removed content --- drivers/fpga/dfl.h | 33 ++++++++++++++++++++++++++++++++- include/linux/dfl.h | 13 ++++++++++++- 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index XXXXXXX..XXXXXXX 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -XXX,XX +XXX,XX @@ /* * Driver Header File for FPGA Device Feature List (DFL) Support * - * Copyright (C) 2017-2018 Intel Corporation, Inc. + * Copyright (C) 2017-2022 Intel Corporation, Inc. * * Authors: * Kang Luwei <luwei.kang@intel.com> @@ -XXX,XX +XXX,XX @@ #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ #define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */ #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ #define DFH_TYPE_AFU 1 #define DFH_TYPE_PRIVATE 3 #define DFH_TYPE_FIU 4 +/* + * DFHv1 Register Offset definitons + * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA + * as common header registers + */ +#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */ +#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */ +#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */ + +/* + * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start), + * 1'b1 = absolute (ARM or other non-PCIe use) + */ +#define DFHv1_CSR_ADDR_REL BIT_ULL(0) + +/* CSR Header Register Bit Definitions */ +#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */ + +/* CSR SIZE Goup Register Bit Definitions */ +#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */ +#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */ +#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */ +#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */ + +/* PARAM Header Register Bit Definitions */ +#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */ +#define DFHv1_PARAM_HDR_VERSION GENMASK_ULL(31, 16) /* Version Param */ +#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 32) /* Offset of next Param */ +#define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */ + /* Next AFU Register Bitfield */ #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ diff --git a/include/linux/dfl.h b/include/linux/dfl.h index XXXXXXX..XXXXXXX 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -XXX,XX +XXX,XX @@ /* * Header file for DFL driver and device API * - * Copyright (C) 2020 Intel Corporation, Inc. + * Copyright (C) 2020-2022 Intel Corporation, Inc. */ #ifndef __LINUX_DFL_H @@ -XXX,XX +XXX,XX @@ #include <linux/device.h> #include <linux/mod_devicetable.h> +#define DFHv1_PARAM_ID_MSIX 0x1 +#define DFHv1_PARAM_MSIX_STARTV 0x0 +#define DFHv1_PARAM_MSIX_NUMV 0x4 + +#define DFHv1_PARAM_ID_CLK_FRQ 0x2 +#define DFHv1_PARAM_ID_FIFO_LEN 0x3 + +#define DFHv1_PARAM_ID_REG_LAYOUT 0x4 +#define DFHv1_PARAM_ID_REG_WIDTH GENMASK_ULL(63, 32) +#define DFHv1_PARAM_ID_REG_SHIFT GENMASK_ULL(31, 0) + /** * enum dfl_id_type - define the DFL FIU types */ -- 2.25.1 From: Matthew Gerlach <matthew.gerlach@linux.intel.com> Add generic support for MSIX interrupts for DFL devices. The location of a feature's registers is explicitly described in DFHv1 and can be relative to the base of the DFHv1 or an absolute address. Parse the location and pass the information to DFL driver. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- v3: remove unneeded blank line use clearer variable name pass finfo into parse_feature_irqs() refactor code for better indentation use switch statement for irq parsing squash in code parsing register location v2: fix kernel doc clarify use of DFH_VERSION field --- drivers/fpga/dfl.c | 150 ++++++++++++++++++++++++++++++++------------ drivers/fpga/dfl.h | 3 + include/linux/dfl.h | 20 ++++++ 3 files changed, 134 insertions(+), 39 deletions(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index XXXXXXX..XXXXXXX 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -XXX,XX +XXX,XX @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, ddev->type = feature_dev_id_type(pdev); ddev->feature_id = feature->id; ddev->revision = feature->revision; + ddev->dfh_version = feature->dfh_version; ddev->cdev = pdata->dfl_cdev; + ddev->csr_res.start = feature->csr_res.start; + ddev->csr_res.end = feature->csr_res.end; + ddev->csr_res.flags = IORESOURCE_MEM; /* add mmio resource */ parent_res = &pdev->resource[feature->resource_index]; @@ -XXX,XX +XXX,XX @@ struct build_feature_devs_info { * struct dfl_feature_info - sub feature info collected during feature dev build * * @fid: id of this sub feature. + * @revision: revision of this sub feature + * @dfh_version: version of Device Feature Header (DFH) * @mmio_res: mmio resource of this sub feature. * @ioaddr: mapped base address of mmio resource. * @node: node in sub_features linked list. + * @csr_res: resource of DFHv1 feature registers + * @csr_size: DFHv1 size of feature registers * @irq_base: start of irq index in this sub feature. * @nr_irqs: number of irqs of this sub feature. */ struct dfl_feature_info { u16 fid; u8 revision; + u8 dfh_version; struct resource mmio_res; void __iomem *ioaddr; struct list_head node; + struct resource csr_res; unsigned int irq_base; unsigned int nr_irqs; }; @@ -XXX,XX +XXX,XX @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) feature->dev = fdev; feature->id = finfo->fid; feature->revision = finfo->revision; + feature->dfh_version = finfo->dfh_version; + feature->csr_res.start = finfo->csr_res.start; + feature->csr_res.end = finfo->csr_res.end; /* * the FIU header feature has some fundamental functions (sriov @@ -XXX,XX +XXX,XX @@ static u16 feature_id(u64 value) } static int parse_feature_irqs(struct build_feature_devs_info *binfo, - resource_size_t ofst, u16 fid, - unsigned int *irq_base, unsigned int *nr_irqs) + resource_size_t ofst, struct dfl_feature_info *finfo) { void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; enum dfl_id_type type; - int virq; - u64 v; - - type = feature_dev_id_type(binfo->feature_dev); + u16 fid = finfo->fid; + u64 v, dfh_ver; + int virq, off; /* * Ideally DFL framework should only read info from DFL header, but - * current version DFL only provides mmio resources information for + * current version, DFHv0, only provides mmio resources information for * each feature in DFL Header, no field for interrupt resources. * Interrupt resource information is provided by specific mmio * registers of each private feature which supports interrupt. So in * order to parse and assign irq resources, DFL framework has to look * into specific capability registers of these private features. * - * Once future DFL version supports generic interrupt resource - * information in common DFL headers, the generic interrupt parsing - * code will be added. But in order to be compatible to old version + * DFHv1 supports generic interrupt resource information in DFHv1 + * parameter blocks. But in order to be compatible to old version * DFL, the driver may still fall back to these quirks. */ - if (type == PORT_ID) { - switch (fid) { - case PORT_FEATURE_ID_UINT: - v = readq(base + PORT_UINT_CAP); - ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); - inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + + switch (finfo->dfh_version) { + case 0: + type = feature_dev_id_type(binfo->feature_dev); + if (type == PORT_ID) { + switch (fid) { + case PORT_FEATURE_ID_UINT: + v = readq(base + PORT_UINT_CAP); + ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); + inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + break; + case PORT_FEATURE_ID_ERROR: + v = readq(base + PORT_ERROR_CAP); + ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + break; + } + } else if (type == FME_ID) { + if (fid == FME_FEATURE_ID_GLOBAL_ERR) { + v = readq(base + FME_ERROR_CAP); + ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); + } + } + break; + + case 1: + if (!dfhv1_has_params(base)) break; - case PORT_FEATURE_ID_ERROR: - v = readq(base + PORT_ERROR_CAP); - ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + + off = dfhv1_find_param(base, ofst, DFHv1_PARAM_ID_MSIX); + if (off < 0) break; - } - } else if (type == FME_ID) { - if (fid == FME_FEATURE_ID_GLOBAL_ERR) { - v = readq(base + FME_ERROR_CAP); - ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); - } + + ibase = readl(base + off + DFHv1_PARAM_MSIX_STARTV); + inr = readl(base + off + DFHv1_PARAM_MSIX_NUMV); + break; + + default: + dev_warn(binfo->dev, "unexpected DFH version %lld\n", dfh_ver); + break; } if (!inr) { - *irq_base = 0; - *nr_irqs = 0; + finfo->irq_base = 0; + finfo->nr_irqs = 0; return 0; } @@ -XXX,XX +XXX,XX @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, } } - *irq_base = ibase; - *nr_irqs = inr; + finfo->irq_base = ibase; + finfo->nr_irqs = inr; return 0; } @@ -XXX,XX +XXX,XX @@ static int create_feature_instance(struct build_feature_devs_info *binfo, resource_size_t ofst, resource_size_t size, u16 fid) { - unsigned int irq_base, nr_irqs; struct dfl_feature_info *finfo; + u8 dfh_version = 0; u8 revision = 0; int ret; u64 v; @@ -XXX,XX +XXX,XX @@ create_feature_instance(struct build_feature_devs_info *binfo, if (fid != FEATURE_ID_AFU) { v = readq(binfo->ioaddr + ofst); revision = FIELD_GET(DFH_REVISION, v); - + dfh_version = FIELD_GET(DFH_VERSION, v); /* read feature size and id if inputs are invalid */ size = size ? size : feature_size(v); fid = fid ? fid : feature_id(v); @@ -XXX,XX +XXX,XX @@ create_feature_instance(struct build_feature_devs_info *binfo, if (binfo->len - ofst < size) return -EINVAL; - ret = parse_feature_irqs(binfo, ofst, fid, &irq_base, &nr_irqs); - if (ret) - return ret; - finfo = kzalloc(sizeof(*finfo), GFP_KERNEL); if (!finfo) return -ENOMEM; finfo->fid = fid; finfo->revision = revision; + finfo->dfh_version = dfh_version; finfo->mmio_res.start = binfo->start + ofst; finfo->mmio_res.end = finfo->mmio_res.start + size - 1; finfo->mmio_res.flags = IORESOURCE_MEM; - finfo->irq_base = irq_base; - finfo->nr_irqs = nr_irqs; + + ret = parse_feature_irqs(binfo, ofst, finfo); + if (ret) + return ret; + + if (dfh_version == 1) { + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_ADDR); + if (v & DFHv1_CSR_ADDR_REL) + finfo->csr_res.start = FIELD_GET(DFHv1_CSR_ADDR_MASK, v); + else + finfo->csr_res.start = binfo->start + ofst + + FIELD_GET(DFHv1_CSR_ADDR_MASK, v); + + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_SIZE_GRP); + finfo->csr_res.end = finfo->csr_res.start + + FIELD_GET(DFHv1_CSR_SIZE_GRP_SIZE, v) - 1; + } list_add_tail(&finfo->node, &binfo->sub_features); binfo->feature_num++; @@ -XXX,XX +XXX,XX @@ long dfl_feature_ioctl_set_irq(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(dfl_feature_ioctl_set_irq); +int dfhv1_find_param(void __iomem *base, resource_size_t max, int param) +{ + int off = DFHv1_PARAM_HDR; + u64 v, next; + + while (off < max) { + v = readq(base + off); + if (param == FIELD_GET(DFHv1_PARAM_HDR_ID, v)) + return (DFHv1_PARAM_DATA + off); + + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v); + if (!next) + break; + + off += next; + } + + return -ENOENT; +} +EXPORT_SYMBOL_GPL(dfhv1_find_param); + +int dfhv1_has_params(void __iomem *dfh_base) +{ + return (FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, + readq(dfh_base + DFHv1_CSR_SIZE_GRP))); +} +EXPORT_SYMBOL_GPL(dfhv1_has_params); + static void __exit dfl_fpga_exit(void) { dfl_chardev_uinit(); diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index XXXXXXX..XXXXXXX 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -XXX,XX +XXX,XX @@ struct dfl_feature_irq_ctx { * this index is used to find its mmio resource from the * feature dev (platform device)'s resources. * @ioaddr: mapped mmio resource address. + * @csr_res: resource for DFHv1 feature registers * @irq_ctx: interrupt context list. * @nr_irqs: number of interrupt contexts. * @ops: ops of this sub feature. @@ -XXX,XX +XXX,XX @@ struct dfl_feature { struct platform_device *dev; u16 id; u8 revision; + u8 dfh_version; int resource_index; void __iomem *ioaddr; + struct resource csr_res; struct dfl_feature_irq_ctx *irq_ctx; unsigned int nr_irqs; const struct dfl_feature_ops *ops; diff --git a/include/linux/dfl.h b/include/linux/dfl.h index XXXXXXX..XXXXXXX 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -XXX,XX +XXX,XX @@ enum dfl_id_type { * @type: type of DFL FIU of the device. See enum dfl_id_type. * @feature_id: feature identifier local to its DFL FIU type. * @mmio_res: mmio resource of this dfl device. + * @csr_res: resource for DFHv1 feature registers * @irqs: list of Linux IRQ numbers of this dfl device. * @num_irqs: number of IRQs supported by this dfl device. * @cdev: pointer to DFL FPGA container device this dfl device belongs to. @@ -XXX,XX +XXX,XX @@ struct dfl_device { u16 type; u16 feature_id; u8 revision; + u8 dfh_version; struct resource mmio_res; + struct resource csr_res; int *irqs; unsigned int num_irqs; struct dfl_fpga_cdev *cdev; @@ -XXX,XX +XXX,XX @@ void dfl_driver_unregister(struct dfl_driver *dfl_drv); module_driver(__dfl_driver, dfl_driver_register, \ dfl_driver_unregister) +/** + * dfhv1_find_param() - find the offset of the given parameter + * @base: base pointer to start of DFH + * @max: maximum offset to search + * @param: id of dfl parameter + * + * Return: positive offset of parameter data on success, negative error code otherwise. + */ +int dfhv1_find_param(void __iomem *base, resource_size_t max, int param); + +/** + * dfhv1_has_params() - does DFHv1 have parameters? + * @base: base pointer to start of DFH + * + * Return: non-zero if DFHv1 has parameters, zero otherwise. + */ +int dfhv1_has_params(void __iomem *base); #endif /* __LINUX_DFL_H */ -- 2.25.1 From: Matthew Gerlach <matthew.gerlach@linux.intel.com> Add a Device Feature List (DFL) bus driver for the Altera 16550 implementation of UART. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Reported-by: kernel test robot <lkp@intel.com> --- v3: use passed in location of registers use cleaned up functions for parsing parameters v2: clean up error messages alphabetize header files fix 'missing prototype' error by making function static tried to sort Makefile and Kconfig better --- drivers/tty/serial/8250/8250_dfl.c | 177 +++++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 9 ++ drivers/tty/serial/8250/Makefile | 1 + 3 files changed, 187 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_dfl.c diff --git a/drivers/tty/serial/8250/8250_dfl.c b/drivers/tty/serial/8250/8250_dfl.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/tty/serial/8250/8250_dfl.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA UART + * + * Copyright (C) 2022 Intel Corporation, Inc. + * + * Authors: + * Ananda Ravuri <ananda.ravuri@intel.com> + * Matthew Gerlach <matthew.gerlach@linux.intel.com> + */ + +#include <linux/bitfield.h> +#include <linux/dfl.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/serial.h> +#include <linux/serial_8250.h> + +struct dfl_uart { + int line; +}; + +static int dfl_uart_get_params(struct device *dev, void __iomem *dfh_base, resource_size_t max, + struct uart_8250_port *uart) +{ + u64 v, fifo_len, reg_width; + int off; + + if (!dfhv1_has_params(dfh_base)) { + dev_err(dev, "missing required DFH parameters\n"); + return -EINVAL; + } + + off = dfhv1_find_param(dfh_base, max, DFHv1_PARAM_ID_CLK_FRQ); + if (off < 0) { + dev_err(dev, "missing CLK_FRQ param\n"); + return -EINVAL; + } + + uart->port.uartclk = readq(dfh_base + off); + dev_dbg(dev, "UART_CLK_ID %u Hz\n", uart->port.uartclk); + + off = dfhv1_find_param(dfh_base, max, DFHv1_PARAM_ID_FIFO_LEN); + if (off < 0) { + dev_err(dev, "missing FIFO_LEN param\n"); + return -EINVAL; + } + + fifo_len = readq(dfh_base + off); + dev_dbg(dev, "UART_FIFO_ID fifo_len %llu\n", fifo_len); + + switch (fifo_len) { + case 32: + uart->port.type = PORT_ALTR_16550_F32; + break; + + case 64: + uart->port.type = PORT_ALTR_16550_F64; + break; + + case 128: + uart->port.type = PORT_ALTR_16550_F128; + break; + + default: + dev_err(dev, "bad fifo_len %llu\n", fifo_len); + return -EINVAL; + } + + off = dfhv1_find_param(dfh_base, max, DFHv1_PARAM_ID_REG_LAYOUT); + if (off < 0) { + dev_err(dev, "missing REG_LAYOUT param\n"); + return -EINVAL; + } + + v = readq(dfh_base + off); + uart->port.regshift = FIELD_GET(DFHv1_PARAM_ID_REG_SHIFT, v); + reg_width = FIELD_GET(DFHv1_PARAM_ID_REG_WIDTH, v); + + dev_dbg(dev, "UART_LAYOUT_ID width %lld shift %d\n", + FIELD_GET(DFHv1_PARAM_ID_REG_WIDTH, v), (int)uart->port.regshift); + + switch (reg_width) { + case 4: + uart->port.iotype = UPIO_MEM32; + break; + + case 2: + uart->port.iotype = UPIO_MEM16; + break; + + default: + dev_err(dev, "invalid reg_width %lld\n", reg_width); + return -EINVAL; + } + + return 0; +} + +static int dfl_uart_probe(struct dfl_device *dfl_dev) +{ + struct device *dev = &dfl_dev->dev; + struct uart_8250_port uart; + struct dfl_uart *dfluart; + resource_size_t res_size; + void __iomem *dfh_base; + int ret; + + memset(&uart, 0, sizeof(uart)); + uart.port.flags = UPF_IOREMAP; + uart.port.mapbase = dfl_dev->csr_res.start; + uart.port.mapsize = resource_size(&dfl_dev->csr_res); + + dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL); + if (!dfluart) + return -ENOMEM; + + dfh_base = devm_ioremap_resource(dev, &dfl_dev->mmio_res); + if (IS_ERR(dfh_base)) + return PTR_ERR(dfh_base); + + res_size = resource_size(&dfl_dev->mmio_res); + + ret = dfl_uart_get_params(dev, dfh_base, res_size, &uart); + + devm_iounmap(dev, dfh_base); + devm_release_mem_region(dev, dfl_dev->mmio_res.start, res_size); + + if (ret < 0) + return dev_err_probe(dev, ret, "failed uart feature walk\n"); + + dev_dbg(dev, "nr_irqs %d %p\n", dfl_dev->num_irqs, dfl_dev->irqs); + + if (dfl_dev->num_irqs == 1) + uart.port.irq = dfl_dev->irqs[0]; + + /* register the port */ + dfluart->line = serial8250_register_8250_port(&uart); + if (dfluart->line < 0) + return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n"); + + dev_info(dev, "serial8250_register_8250_port %d\n", dfluart->line); + dev_set_drvdata(dev, dfluart); + + return 0; +} + +static void dfl_uart_remove(struct dfl_device *dfl_dev) +{ + struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev); + + if (dfluart->line >= 0) + serial8250_unregister_port(dfluart->line); +} + +#define FME_FEATURE_ID_UART 0x24 + +static const struct dfl_device_id dfl_uart_ids[] = { + { FME_ID, FME_FEATURE_ID_UART }, + { } +}; +MODULE_DEVICE_TABLE(dfl, dfl_uart_ids); + +static struct dfl_driver dfl_uart_driver = { + .drv = { + .name = "dfl-uart", + }, + .id_table = dfl_uart_ids, + .probe = dfl_uart_probe, + .remove = dfl_uart_remove, +}; +module_dfl_driver(dfl_uart_driver); + +MODULE_DESCRIPTION("DFL Intel UART driver"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -XXX,XX +XXX,XX @@ config SERIAL_8250_BCM2835AUX If unsure, say N. +config SERIAL_8250_DFL + tristate "DFL bus driver for Altera 16550 UART" + depends on SERIAL_8250 && FPGA_DFL + help + This option enables support for a Device Feature List (DFL) bus + driver for the Altera 16650 UART. One or more Altera 16650 UARTs + can be instantiated in a FPGA and then be discovered during + enumeration of the DFL bus. + config SERIAL_8250_FSL bool "Freescale 16550 UART support" if COMPILE_TEST && !(PPC || ARM || ARM64) depends on SERIAL_8250_CONSOLE diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index XXXXXXX..XXXXXXX 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o +obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o -- 2.25.1 From: Matthew Gerlach <matthew.gerlach@intel.com> This patchset enhances the definition of the Device Feature Header (DFH) used by the Device Feature List (DFL) bus and then uses the new enhancements in a uart driver. Patch 1 updates the DFL documentation to provide the motivation behind the enhancements to the definition of the DFH. Patch 2 adds the definitions for DFHv1. Patch 3 adds basic support DFHv1. It provides a generic mechanism for describing MSIX interrupts used by a particular feature instance, and it gets the location and size of the feature's register set from DFHv1. Patch 4 adds a DFL uart driver that makes use of the new features of DFHv1. Basheer Ahmed Muddebihal (1): fpga: dfl: Add DFHv1 Register Definitions Matthew Gerlach (3): Documentation: fpga: dfl: Add documentation for DFHv1 fpga: dfl: add basic support DFHv1 tty: serial: 8250: add DFL bus driver for Altera 16550. Documentation/fpga/dfl.rst | 96 ++++++++++++ drivers/fpga/dfl.c | 234 +++++++++++++++++++++++------ drivers/fpga/dfl.h | 38 +++++ drivers/tty/serial/8250/8250_dfl.c | 149 ++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 12 ++ drivers/tty/serial/8250/Makefile | 1 + include/linux/dfl.h | 15 ++ 7 files changed, 496 insertions(+), 49 deletions(-) create mode 100644 drivers/tty/serial/8250/8250_dfl.c -- 2.25.1 From: Matthew Gerlach <matthew.gerlach@linux.intel.com> Add documentation describing the extensions provided by Version 1 of the Device Feature Header (DFHv1). Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- v4: Remove marketing speak and separate v0 and v1 descriptions. Fix errors reported by "make htmldocs". v3: no change v2: s/GUILD/GUID/ add picture --- Documentation/fpga/dfl.rst | 96 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index XXXXXXX..XXXXXXX 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -XXX,XX +XXX,XX @@ new DFL feature via UIO direct access, its feature id should be added to the driver's id_table. +Device Feature Header - Version 0 +=========================================== +The format of Version 0 of a Device Feature Header (DFH) is shown below:: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| 0x00 + +-----------------------------------------------------------------------+ + |63 GUID_L 0| 0x08 + +-----------------------------------------------------------------------+ + |63 GUID_H 0| 0x10 + +-----------------------------------------------------------------------+ + +Offset 0x00 +Type - The type of DFH (e.g. FME, AFU, or private feature). +DFH VER - The version of the DFH. +Rsvd - Currently unused. +EOL - Set if this DFH is the end of the Device Feature List (DFL). +Next - The offset of the next DFH in the DFL from the start of the DFH. +If EOL is set, Next refers to size of mmio for last feature in the list. +ID - If Type field is 'private feature', then ID of the private feature. + +Offset 0x08 +GUID_L - Least significant 64 bits of a 128 bit Globally Unique Identifier +if Type is FME or AFU. + +Offset 0x10 +GUID_H - Most significant 64 bits of a 128 bit Globally Unique Identifier +if Type is FME or AFU. + + +Device Feature Header - Version 1 +=========================================== +The format of Version 1 of a Device Feature Header (DFH) is shown below:: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| 0x00 + +-----------------------------------------------------------------------+ + |63 GUID_L 0| 0x08 + +-----------------------------------------------------------------------+ + |63 GUID_H 0| 0x10 + +-----------------------------------------------------------------------+ + |63 Address/Offset 1| Rel 0| 0x18 + +-----------------------------------------------------------------------+ + |63 Reg Size 32|Params 31|30 Group 16|15 Instance 0| 0x20 + +-----------------------------------------------------------------------+ + |63 Next 34|RSV33|EOP32|31 Param Version 16|15 Param ID 0| 0x28 + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| 0x30 + +-----------------------------------------------------------------------+ + + ... + + +-----------------------------------------------------------------------+ + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + +Offset 0x00 +Type - The type of DFH (e.g. FME, AFU, or private feature). +DFH VER - The version of the DFH. +Rsvd - Currently unused. +EOL - Set if this DFH is the end of the Device Feature List (DFL). +Next - The offset of the next DFH in the DFL from the start of the DFH. +If EOL is set, Next refers to size of mmio for last feature in the list. +ID - If Type field is 'private feature', then ID of the private feature. + +Offset 0x08 +GUID_L - Least significant 64 bits of a 128 bit Globally Unique Identifier. + +Offset 0x10 +GUID_H - Most significant 64 bits of a 128 bit Globally Unique Identifier +if Type is FME or AFU. + +Offset 0x18 +Address/Offset - If Rel bit is set, then high 63 bits of a 16 bit aligned +absolute address for the location of the feature's registers. +If Rel bit is clear, then the feature's registers start at the +offset from the start of the DFH. + +Offset 0x20 +Reg Size - Size of feature's register set. +Params - Set if DFH has one or more parameter blocks. +Group - Id of group if feature is part of a group. +Instance - Id of instance of feature within a group. + +Offset 0x28 if feature has parameters +Next - High 30 bits of a 32 bit aligned offset to the next parameter block. +If EOP set, size of last parameter. +Param Version - Version of Param ID. +Param ID - ID of parameter. + +Offset 0x30 +Parameter Data - Parameter data whose size and format is defined by version +and ID of the parameter. + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration -- 2.25.1 From: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com> This patch adds the definitions for DFHv1 header and related register bitfields. Signed-off-by: Basheer Ahmed Muddebihal <basheer.ahmed.muddebihal@linux.intel.com> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- v4: s/MSIX/MSI_X/g move kerneldoc to implementation don't change copyright date v3: keep DFHv1 definitions "hidden" in drivers/fpga/dfl.h v2: clean up whitespace and one line comments remove extra space in commit use uniform number of digits in constants don't change copyright date because of removed content dfl.h s/MSIX/MSI_X/g move kerneldoc --- drivers/fpga/dfl.h | 33 +++++++++++++++++++++++++++++++++ include/linux/dfl.h | 11 +++++++++++ 2 files changed, 44 insertions(+) diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index XXXXXXX..XXXXXXX 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -XXX,XX +XXX,XX @@ #define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ #define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ #define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_VERSION GENMASK_ULL(59, 52) /* DFH version */ #define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ #define DFH_TYPE_AFU 1 #define DFH_TYPE_PRIVATE 3 #define DFH_TYPE_FIU 4 +/* + * DFHv1 Register Offset definitons + * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA + * as common header registers + */ +#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */ +#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */ +#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */ + +/* + * CSR Rel Bit, 1'b0 = relative (offset from feature DFH start), + * 1'b1 = absolute (ARM or other non-PCIe use) + */ +#define DFHv1_CSR_ADDR_REL BIT_ULL(0) + +/* CSR Header Register Bit Definitions */ +#define DFHv1_CSR_ADDR_MASK GENMASK_ULL(63, 1) /* 63:1 of CSR address */ + +/* CSR SIZE Goup Register Bit Definitions */ +#define DFHv1_CSR_SIZE_GRP_INSTANCE_ID GENMASK_ULL(15, 0) /* Enumeration instantiated IP */ +#define DFHv1_CSR_SIZE_GRP_GROUPING_ID GENMASK_ULL(30, 16) /* Group Features/interfaces */ +#define DFHv1_CSR_SIZE_GRP_HAS_PARAMS BIT_ULL(31) /* Presence of Parameters */ +#define DFHv1_CSR_SIZE_GRP_SIZE GENMASK_ULL(63, 32) /* Size of CSR Block in bytes */ + +/* PARAM Header Register Bit Definitions */ +#define DFHv1_PARAM_HDR_ID GENMASK_ULL(15, 0) /* Id of this Param */ +#define DFHv1_PARAM_HDR_VERSION GENMASK_ULL(31, 16) /* Version Param */ +#define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 32) /* Offset of next Param */ +#define DFHv1_PARAM_HDR_NEXT_EOL BIT_ULL(0) +#define DFHv1_PARAM_HDR_NEXT_MASK GENMASK_ULL(1, 0) +#define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */ + /* Next AFU Register Bitfield */ #define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ diff --git a/include/linux/dfl.h b/include/linux/dfl.h index XXXXXXX..XXXXXXX 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -XXX,XX +XXX,XX @@ #include <linux/device.h> #include <linux/mod_devicetable.h> +#define DFHv1_PARAM_ID_MSI_X 0x1 +#define DFHv1_PARAM_MSI_X_STARTV 0x0 +#define DFHv1_PARAM_MSI_X_NUMV 0x4 + +#define DFHv1_PARAM_ID_CLK_FRQ 0x2 +#define DFHv1_PARAM_ID_FIFO_LEN 0x3 + +#define DFHv1_PARAM_ID_REG_LAYOUT 0x4 +#define DFHv1_PARAM_ID_REG_WIDTH GENMASK_ULL(63, 32) +#define DFHv1_PARAM_ID_REG_SHIFT GENMASK_ULL(31, 0) + /** * enum dfl_id_type - define the DFL FIU types */ -- 2.25.1 From: Matthew Gerlach <matthew.gerlach@linux.intel.com> Add generic support for MSI-X interrupts for DFL devices. The location of a feature's registers is explicitly described in DFHv1 and can be relative to the base of the DFHv1 or an absolute address. Parse the location and pass the information to DFL driver. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- v4: s/MSIX/MSI_X move kernel doc to implementation use structure assignment fix decode of absolute address clean up comment in parse_feature_irqs remove use of csr_res v3: remove unneeded blank line use clearer variable name pass finfo into parse_feature_irqs() refactor code for better indentation use switch statement for irq parsing squash in code parsing register location v2: fix kernel doc clarify use of DFH_VERSION field --- drivers/fpga/dfl.c | 234 ++++++++++++++++++++++++++++++++++---------- drivers/fpga/dfl.h | 5 + include/linux/dfl.h | 4 + 3 files changed, 194 insertions(+), 49 deletions(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index XXXXXXX..XXXXXXX 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -XXX,XX +XXX,XX @@ static void release_dfl_dev(struct device *dev) if (ddev->mmio_res.parent) release_resource(&ddev->mmio_res); + kfree(ddev->params); + ida_free(&dfl_device_ida, ddev->id); kfree(ddev->irqs); kfree(ddev); @@ -XXX,XX +XXX,XX @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, ddev->type = feature_dev_id_type(pdev); ddev->feature_id = feature->id; ddev->revision = feature->revision; + ddev->dfh_version = feature->dfh_version; ddev->cdev = pdata->dfl_cdev; + if (feature->param_size) { + ddev->params = kmemdup(feature->params, feature->param_size, GFP_KERNEL); + if (!ddev->params) { + ret = -ENOMEM; + goto put_dev; + } + ddev->param_size = feature->param_size; + } /* add mmio resource */ parent_res = &pdev->resource[feature->resource_index]; @@ -XXX,XX +XXX,XX @@ struct build_feature_devs_info { * struct dfl_feature_info - sub feature info collected during feature dev build * * @fid: id of this sub feature. + * @revision: revision of this sub feature + * @dfh_version: version of Device Feature Header (DFH) * @mmio_res: mmio resource of this sub feature. * @ioaddr: mapped base address of mmio resource. * @node: node in sub_features linked list. * @irq_base: start of irq index in this sub feature. * @nr_irqs: number of irqs of this sub feature. + * @param_size: size DFH parameters. + * @params: DFH parameter data. */ struct dfl_feature_info { u16 fid; u8 revision; + u8 dfh_version; struct resource mmio_res; void __iomem *ioaddr; struct list_head node; unsigned int irq_base; unsigned int nr_irqs; + unsigned int param_size; + u64 params[]; }; static void dfl_fpga_cdev_add_port_dev(struct dfl_fpga_cdev *cdev, @@ -XXX,XX +XXX,XX @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) feature->dev = fdev; feature->id = finfo->fid; feature->revision = finfo->revision; + feature->dfh_version = finfo->dfh_version; + if (finfo->param_size) { + feature->params = devm_kmemdup(binfo->dev, + finfo->params, finfo->param_size, + GFP_KERNEL); + if (!feature->params) + return -ENOMEM; + + feature->param_size = finfo->param_size; + } /* * the FIU header feature has some fundamental functions (sriov * set, port enable/disable) needed for the dfl bus device and @@ -XXX,XX +XXX,XX @@ static u16 feature_id(u64 value) return 0; } +static void *find_param(void *base, resource_size_t max, int param) +{ + int off = 0; + u64 v, next; + + while (off < max) { + v = *(u64 *)(base + off); + if (param == FIELD_GET(DFHv1_PARAM_HDR_ID, v)) + return base + off + DFHv1_PARAM_DATA; + + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v); + off += next & ~DFHv1_PARAM_HDR_NEXT_MASK; + if (next & DFHv1_PARAM_HDR_NEXT_EOL) + break; + + } + + return NULL; +} + +/** + * dfh_find_param() - find data for the given parameter id + * @dfl_dev: dfl device + * @param: id of dfl parameter + * + * Return: pointer to parameter data on success, NULL otherwise. + */ +void *dfh_find_param(struct dfl_device *dfl_dev, int param) +{ + return find_param(dfl_dev->params, dfl_dev->param_size, param); +} +EXPORT_SYMBOL_GPL(dfh_find_param); + static int parse_feature_irqs(struct build_feature_devs_info *binfo, - resource_size_t ofst, u16 fid, - unsigned int *irq_base, unsigned int *nr_irqs) + resource_size_t ofst, struct dfl_feature_info *finfo) { void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; + void *params = finfo->params; enum dfl_id_type type; + u16 fid = finfo->fid; int virq; + u32 *p; u64 v; - type = feature_dev_id_type(binfo->feature_dev); + switch (finfo->dfh_version) { + case 0: + /* + * DFHv0 only provides mmio resource information for each feature + * in the DFL header. There is no generic interrupt information. + * Instead, features with interrupt functionality provide + * the information in feature specific registers. + */ + type = feature_dev_id_type(binfo->feature_dev); + if (type == PORT_ID) { + switch (fid) { + case PORT_FEATURE_ID_UINT: + v = readq(base + PORT_UINT_CAP); + ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); + inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + break; + case PORT_FEATURE_ID_ERROR: + v = readq(base + PORT_ERROR_CAP); + ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + break; + } + } else if (type == FME_ID) { + switch (fid) { + case FME_FEATURE_ID_GLOBAL_ERR: + v = readq(base + FME_ERROR_CAP); + ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); + break; + } + } + break; - /* - * Ideally DFL framework should only read info from DFL header, but - * current version DFL only provides mmio resources information for - * each feature in DFL Header, no field for interrupt resources. - * Interrupt resource information is provided by specific mmio - * registers of each private feature which supports interrupt. So in - * order to parse and assign irq resources, DFL framework has to look - * into specific capability registers of these private features. - * - * Once future DFL version supports generic interrupt resource - * information in common DFL headers, the generic interrupt parsing - * code will be added. But in order to be compatible to old version - * DFL, the driver may still fall back to these quirks. - */ - if (type == PORT_ID) { - switch (fid) { - case PORT_FEATURE_ID_UINT: - v = readq(base + PORT_UINT_CAP); - ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); - inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + case 1: + /* + * DFHv1 provides interrupt resource information in DFHv1 + * parameter blocks. + */ + if (!finfo->param_size) break; - case PORT_FEATURE_ID_ERROR: - v = readq(base + PORT_ERROR_CAP); - ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + + p = find_param(params, finfo->param_size, DFHv1_PARAM_ID_MSI_X); + if (!p) break; - } - } else if (type == FME_ID) { - if (fid == FME_FEATURE_ID_GLOBAL_ERR) { - v = readq(base + FME_ERROR_CAP); - ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); - } + + ibase = *p++; + inr = *p; + break; + + default: + dev_warn(binfo->dev, "unexpected DFH version %d\n", finfo->dfh_version); + break; } if (!inr) { - *irq_base = 0; - *nr_irqs = 0; + finfo->irq_base = 0; + finfo->nr_irqs = 0; return 0; } @@ -XXX,XX +XXX,XX @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, } } - *irq_base = ibase; - *nr_irqs = inr; + finfo->irq_base = ibase; + finfo->nr_irqs = inr; return 0; } +static int dfh_get_psize(void __iomem *dfh_base, resource_size_t max) +{ + int size = 0; + u64 v, next; + + if (!FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, + readq(dfh_base + DFHv1_CSR_SIZE_GRP))) + return 0; + + while (size + DFHv1_PARAM_HDR < max) { + v = readq(dfh_base + DFHv1_PARAM_HDR + size); + + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v); + if (!(next & ~DFHv1_PARAM_HDR_NEXT_MASK)) + return -EINVAL; + + size += next & ~DFHv1_PARAM_HDR_NEXT_MASK; + + if (next & DFHv1_PARAM_HDR_NEXT_EOL) + return size; + } + + return -ENOENT; +} + /* * when create sub feature instances, for private features, it doesn't need * to provide resource size and feature id as they could be read from DFH @@ -XXX,XX +XXX,XX @@ static int create_feature_instance(struct build_feature_devs_info *binfo, resource_size_t ofst, resource_size_t size, u16 fid) { - unsigned int irq_base, nr_irqs; struct dfl_feature_info *finfo; + int dfh_psize = 0; u8 revision = 0; + u8 dfh_ver = 0; int ret; u64 v; if (fid != FEATURE_ID_AFU) { v = readq(binfo->ioaddr + ofst); revision = FIELD_GET(DFH_REVISION, v); - + dfh_ver = FIELD_GET(DFH_VERSION, v); /* read feature size and id if inputs are invalid */ size = size ? size : feature_size(v); fid = fid ? fid : feature_id(v); + if (dfh_ver == 1) { + dfh_psize = dfh_get_psize(binfo->ioaddr + ofst, size); + if (dfh_psize < 0) { + dev_err(binfo->dev, + "failed to read size of DFHv1 parameters %d\n", + dfh_psize); + return dfh_psize; + } + dev_dbg(binfo->dev, "dfhv1_psize %d\n", dfh_psize); + } } if (binfo->len - ofst < size) return -EINVAL; - ret = parse_feature_irqs(binfo, ofst, fid, &irq_base, &nr_irqs); - if (ret) - return ret; - - finfo = kzalloc(sizeof(*finfo), GFP_KERNEL); + finfo = kzalloc(sizeof(*finfo) + dfh_psize, GFP_KERNEL); if (!finfo) return -ENOMEM; + if (dfh_psize > 0) { + memcpy_fromio(finfo->params, + binfo->ioaddr + ofst + DFHv1_PARAM_HDR, dfh_psize); + finfo->param_size = dfh_psize; + } + finfo->fid = fid; finfo->revision = revision; - finfo->mmio_res.start = binfo->start + ofst; - finfo->mmio_res.end = finfo->mmio_res.start + size - 1; + finfo->dfh_version = dfh_ver; finfo->mmio_res.flags = IORESOURCE_MEM; - finfo->irq_base = irq_base; - finfo->nr_irqs = nr_irqs; + if (dfh_ver == 1) { + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_ADDR); + if (v & DFHv1_CSR_ADDR_REL) + finfo->mmio_res.start = v & ~DFHv1_CSR_ADDR_REL; + else + finfo->mmio_res.start = binfo->start + ofst + + FIELD_GET(DFHv1_CSR_ADDR_MASK, v); + + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_SIZE_GRP); + finfo->mmio_res.end = finfo->mmio_res.start + + FIELD_GET(DFHv1_CSR_SIZE_GRP_SIZE, v) - 1; + } else { + finfo->mmio_res.start = binfo->start + ofst; + finfo->mmio_res.end = finfo->mmio_res.start + size - 1; + } + + ret = parse_feature_irqs(binfo, ofst, finfo); + if (ret) { + kfree(finfo); + return ret; + } list_add_tail(&finfo->node, &binfo->sub_features); binfo->feature_num++; diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index XXXXXXX..XXXXXXX 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -XXX,XX +XXX,XX @@ struct dfl_feature_irq_ctx { * @ops: ops of this sub feature. * @ddev: ptr to the dfl device of this sub feature. * @priv: priv data of this feature. + * @param_size: size of dfh parameters + * @params: point to memory copy of dfh parameters */ struct dfl_feature { struct platform_device *dev; u16 id; u8 revision; + u8 dfh_version; int resource_index; void __iomem *ioaddr; struct dfl_feature_irq_ctx *irq_ctx; @@ -XXX,XX +XXX,XX @@ struct dfl_feature { const struct dfl_feature_ops *ops; struct dfl_device *ddev; void *priv; + unsigned int param_size; + void *params; }; #define FEATURE_DEV_ID_UNUSED (-1) diff --git a/include/linux/dfl.h b/include/linux/dfl.h index XXXXXXX..XXXXXXX 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -XXX,XX +XXX,XX @@ struct dfl_device { u16 type; u16 feature_id; u8 revision; + u8 dfh_version; struct resource mmio_res; int *irqs; unsigned int num_irqs; + unsigned int param_size; + void *params; struct dfl_fpga_cdev *cdev; const struct dfl_device_id *id_entry; }; @@ -XXX,XX +XXX,XX @@ void dfl_driver_unregister(struct dfl_driver *dfl_drv); module_driver(__dfl_driver, dfl_driver_register, \ dfl_driver_unregister) +void *dfh_find_param(struct dfl_device *dfl_dev, int param); #endif /* __LINUX_DFL_H */ -- 2.25.1 From: Matthew Gerlach <matthew.gerlach@linux.intel.com> Add a Device Feature List (DFL) bus driver for the Altera 16550 implementation of UART. Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> --- v4: use dev_err_probe() everywhere that is appropriate clean up noise change error messages to use the word, unsupported tried again to sort Makefile and KConfig better reorder probe function for easier error handling use new dfh_find_param API v3: use passed in location of registers use cleaned up functions for parsing parameters v2: clean up error messages alphabetize header files fix 'missing prototype' error by making function static tried to sort Makefile and Kconfig better --- drivers/tty/serial/8250/8250_dfl.c | 149 +++++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 12 +++ drivers/tty/serial/8250/Makefile | 1 + 3 files changed, 162 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_dfl.c diff --git a/drivers/tty/serial/8250/8250_dfl.c b/drivers/tty/serial/8250/8250_dfl.c new file mode 100644 index XXXXXXX..XXXXXXX --- /dev/null +++ b/drivers/tty/serial/8250/8250_dfl.c @@ -XXX,XX +XXX,XX @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA UART + * + * Copyright (C) 2022 Intel Corporation, Inc. + * + * Authors: + * Ananda Ravuri <ananda.ravuri@intel.com> + * Matthew Gerlach <matthew.gerlach@linux.intel.com> + */ + +#include <linux/bitfield.h> +#include <linux/dfl.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/serial.h> +#include <linux/serial_8250.h> + +struct dfl_uart { + int line; +}; + +static int dfl_uart_get_params(struct dfl_device *dfl_dev, struct uart_8250_port *uart) +{ + struct device *dev = &dfl_dev->dev; + u64 v, fifo_len, reg_width; + u64 *p; + + p = dfh_find_param(dfl_dev, DFHv1_PARAM_ID_CLK_FRQ); + if (!p) + return dev_err_probe(dev, -EINVAL, "missing CLK_FRQ param\n"); + + uart->port.uartclk = *p; + dev_dbg(dev, "UART_CLK_ID %u Hz\n", uart->port.uartclk); + + p = dfh_find_param(dfl_dev, DFHv1_PARAM_ID_FIFO_LEN); + if (!p) + return dev_err_probe(dev, -EINVAL, "missing FIFO_LEN param\n"); + + fifo_len = *p; + dev_dbg(dev, "UART_FIFO_ID fifo_len %llu\n", fifo_len); + + switch (fifo_len) { + case 32: + uart->port.type = PORT_ALTR_16550_F32; + break; + + case 64: + uart->port.type = PORT_ALTR_16550_F64; + break; + + case 128: + uart->port.type = PORT_ALTR_16550_F128; + break; + + default: + return dev_err_probe(dev, -EINVAL, "unsupported fifo_len %llu\n", fifo_len); + } + + p = dfh_find_param(dfl_dev, DFHv1_PARAM_ID_REG_LAYOUT); + if (!p) + return dev_err_probe(dev, -EINVAL, "missing REG_LAYOUT param\n"); + + v = *p; + uart->port.regshift = FIELD_GET(DFHv1_PARAM_ID_REG_SHIFT, v); + reg_width = FIELD_GET(DFHv1_PARAM_ID_REG_WIDTH, v); + + dev_dbg(dev, "UART_LAYOUT_ID width %lld shift %d\n", reg_width, uart->port.regshift); + + switch (reg_width) { + case 4: + uart->port.iotype = UPIO_MEM32; + break; + + case 2: + uart->port.iotype = UPIO_MEM16; + break; + + default: + return dev_err_probe(dev, -EINVAL, "unsupported reg_width %lld\n", reg_width); + } + + return 0; +} + +static int dfl_uart_probe(struct dfl_device *dfl_dev) +{ + struct device *dev = &dfl_dev->dev; + struct uart_8250_port uart; + struct dfl_uart *dfluart; + int ret; + + memset(&uart, 0, sizeof(uart)); + uart.port.flags = UPF_IOREMAP; + uart.port.mapbase = dfl_dev->mmio_res.start; + uart.port.mapsize = resource_size(&dfl_dev->mmio_res); + + ret = dfl_uart_get_params(dfl_dev, &uart); + + if (ret < 0) + return dev_err_probe(dev, ret, "failed uart feature walk\n"); + + dev_dbg(dev, "nr_irqs %d %p\n", dfl_dev->num_irqs, dfl_dev->irqs); + + if (dfl_dev->num_irqs == 1) + uart.port.irq = dfl_dev->irqs[0]; + + dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL); + if (!dfluart) + return -ENOMEM; + + dfluart->line = serial8250_register_8250_port(&uart); + if (dfluart->line < 0) + return dev_err_probe(dev, dfluart->line, "unable to register 8250 port.\n"); + + dev_set_drvdata(dev, dfluart); + + return 0; +} + +static void dfl_uart_remove(struct dfl_device *dfl_dev) +{ + struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev); + + serial8250_unregister_port(dfluart->line); +} + +#define FME_FEATURE_ID_UART 0x24 + +static const struct dfl_device_id dfl_uart_ids[] = { + { FME_ID, FME_FEATURE_ID_UART }, + { } +}; +MODULE_DEVICE_TABLE(dfl, dfl_uart_ids); + +static struct dfl_driver dfl_uart_driver = { + .drv = { + .name = "dfl-uart", + }, + .id_table = dfl_uart_ids, + .probe = dfl_uart_probe, + .remove = dfl_uart_remove, +}; +module_dfl_driver(dfl_uart_driver); + +MODULE_DESCRIPTION("DFL Intel UART driver"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index XXXXXXX..XXXXXXX 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -XXX,XX +XXX,XX @@ config SERIAL_8250_FSL erratum for Freescale 16550 UARTs in the 8250 driver. It also enables support for ACPI enumeration. +config SERIAL_8250_DFL + tristate "DFL bus driver for Altera 16550 UART" + depends on SERIAL_8250 && FPGA_DFL + help + This option enables support for a Device Feature List (DFL) bus + driver for the Altera 16650 UART. One or more Altera 16650 UARTs + can be instantiated in a FPGA and then be discovered during + enumeration of the DFL bus. + + To compile this driver as a module, chose M here: the + module will be called 8250_dfl. + config SERIAL_8250_DW tristate "Support for Synopsys DesignWare 8250 quirks" depends on SERIAL_8250 diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index XXXXXXX..XXXXXXX 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o +obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o -- 2.25.1