From nobody Mon Apr 6 11:11:32 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 703A6C433FE for ; Tue, 4 Oct 2022 08:13:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230131AbiJDINC (ORCPT ); Tue, 4 Oct 2022 04:13:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229728AbiJDIL6 (ORCPT ); Tue, 4 Oct 2022 04:11:58 -0400 Received: from smtp-out2.suse.de (smtp-out2.suse.de [IPv6:2001:67c:2178:6::1d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3567A26FA for ; Tue, 4 Oct 2022 01:11:30 -0700 (PDT) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 3326E1F8DD; Tue, 4 Oct 2022 08:11:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1664871089; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ZzONkjUJmPZz/3+LUsNTypMHrROWbwKy8vJfF8tbKIc=; b=eTmHI6DYRJS0gdQ2DNRdK3aGFm2xivDyF+fejg1I61bBX15V/iv5oQKcrkQQORZyXsplTH fVlRcwMb1zKNnBh90OwXKf6uutRbX9TVA0D6vHITRW3XRgeNIx7wslGzDu0Mtidf1ZaCf+ tgcb4DmCcWuxI/Y87ycvXko/wdQ9fnI= Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id EC61F139EF; Tue, 4 Oct 2022 08:11:28 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id r+VoOLDqO2OSSAAAMHmgww (envelope-from ); Tue, 04 Oct 2022 08:11:28 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH v4 11/16] x86/mtrr: let cache_aps_delayed_init replace mtrr_aps_delayed_init Date: Tue, 4 Oct 2022 10:10:18 +0200 Message-Id: <20221004081023.32402-12-jgross@suse.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20221004081023.32402-1-jgross@suse.com> References: <20221004081023.32402-1-jgross@suse.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to prepare decoupling MTRR and PAT replace the MTRR specific mtrr_aps_delayed_init flag with a more generic cache_aps_delayed_init one. Signed-off-by: Juergen Gross --- V2: - new patch V4: - reestablish function to set cache_aps_delayed_init (Borislav Petkov) --- arch/x86/include/asm/cacheinfo.h | 3 +++ arch/x86/include/asm/mtrr.h | 2 -- arch/x86/kernel/cpu/cacheinfo.c | 7 +++++++ arch/x86/kernel/cpu/mtrr/mtrr.c | 17 ++++------------- arch/x86/kernel/smpboot.c | 5 +++-- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/x86/include/asm/cacheinfo.h b/arch/x86/include/asm/cachei= nfo.h index 978bac70fd49..1339bf0908dc 100644 --- a/arch/x86/include/asm/cacheinfo.h +++ b/arch/x86/include/asm/cacheinfo.h @@ -7,11 +7,14 @@ extern unsigned int memory_caching_control; #define CACHE_MTRR 0x01 #define CACHE_PAT 0x02 =20 +extern bool cache_aps_delayed_init; + void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu); void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu); =20 void cache_disable(void); void cache_enable(void); void cache_cpu_init(void); +void set_cache_aps_delayed_init(void); =20 #endif /* _ASM_X86_CACHEINFO_H */ diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 986249a2b9b6..5d31219c8529 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -43,7 +43,6 @@ extern int mtrr_del(int reg, unsigned long base, unsigned= long size); extern int mtrr_del_page(int reg, unsigned long base, unsigned long size); extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi); extern void mtrr_ap_init(void); -extern void set_mtrr_aps_delayed_init(void); extern void mtrr_aps_init(void); extern void mtrr_bp_restore(void); extern int mtrr_trim_uncached_memory(unsigned long end_pfn); @@ -87,7 +86,6 @@ static inline void mtrr_centaur_report_mcr(int mcr, u32 l= o, u32 hi) { } #define mtrr_ap_init() do {} while (0) -#define set_mtrr_aps_delayed_init() do {} while (0) #define mtrr_aps_init() do {} while (0) #define mtrr_bp_restore() do {} while (0) #define mtrr_disable() do {} while (0) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 49b60a427fc9..330aa412be63 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -1137,3 +1137,10 @@ void cache_cpu_init(void) cache_enable(); local_irq_restore(flags); } + +bool cache_aps_delayed_init; + +void set_cache_aps_delayed_init(void) +{ + cache_aps_delayed_init =3D true; +} diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtr= r.c index 7eed5387e828..68376c924b75 100644 --- a/arch/x86/kernel/cpu/mtrr/mtrr.c +++ b/arch/x86/kernel/cpu/mtrr/mtrr.c @@ -64,7 +64,6 @@ unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES]; static DEFINE_MUTEX(mtrr_mutex); =20 u64 size_or_mask, size_and_mask; -static bool mtrr_aps_delayed_init; =20 static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM] __ro_after_init; =20 @@ -171,7 +170,7 @@ static int mtrr_rendezvous_handler(void *info) if (data->smp_reg !=3D ~0U) { mtrr_if->set(data->smp_reg, data->smp_base, data->smp_size, data->smp_type); - } else if (mtrr_aps_delayed_init || !cpu_online(smp_processor_id())) { + } else if (cache_aps_delayed_init || !cpu_online(smp_processor_id())) { cache_cpu_init(); } return 0; @@ -778,7 +777,7 @@ void __init mtrr_bp_init(void) =20 void mtrr_ap_init(void) { - if (!memory_caching_control || mtrr_aps_delayed_init) + if (!memory_caching_control || cache_aps_delayed_init) return; =20 /* @@ -812,14 +811,6 @@ void mtrr_save_state(void) smp_call_function_single(first_cpu, mtrr_save_fixed_ranges, NULL, 1); } =20 -void set_mtrr_aps_delayed_init(void) -{ - if (!memory_caching_control) - return; - - mtrr_aps_delayed_init =3D true; -} - /* * Delayed MTRR initialization for all AP's */ @@ -833,11 +824,11 @@ void mtrr_aps_init(void) * by doing set_mtrr_aps_delayed_init(), prior to this point. If not, * then we are done. */ - if (!mtrr_aps_delayed_init) + if (!cache_aps_delayed_init) return; =20 set_mtrr(~0U, 0, 0, 0); - mtrr_aps_delayed_init =3D false; + cache_aps_delayed_init =3D false; } =20 void mtrr_bp_restore(void) diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index f24227bc3220..de2082c21e8b 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -58,6 +58,7 @@ #include =20 #include +#include #include #include #include @@ -1428,7 +1429,7 @@ void __init native_smp_prepare_cpus(unsigned int max_= cpus) =20 uv_system_init(); =20 - set_mtrr_aps_delayed_init(); + set_cache_aps_delayed_init(); =20 smp_quirk_init_udelay(); =20 @@ -1439,7 +1440,7 @@ void __init native_smp_prepare_cpus(unsigned int max_= cpus) =20 void arch_thaw_secondary_cpus_begin(void) { - set_mtrr_aps_delayed_init(); + set_cache_aps_delayed_init(); } =20 void arch_thaw_secondary_cpus_end(void) --=20 2.35.3