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[109.15.145.210]) by smtp.googlemail.com with ESMTPSA id j2-20020adfd202000000b002285f73f11dsm15361698wrh.81.2022.10.04.04.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 04:11:29 -0700 (PDT) From: Amjad Ouled-Ameur Date: Tue, 04 Oct 2022 13:10:36 +0200 Subject: [PATCH v2 1/2] spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221004-up-aml-fix-spi-v2-1-3e8ae91a1925@baylibre.com> References: <20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@baylibre.com> To: Krzysztof Kozlowski , Neil Armstrong , Rob Herring , Martin Blumenstingl , Kevin Hilman , Jerome Brunet , Mark Brown Cc: Neil Armstrong , Da Xue , linux-kernel@vger.kernel.org, Amjad Ouled-Ameur , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1664881888; l=1463; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=Ke2EUTvINs95mUpMERJPIoATA/4M6T38d1rluEloC5g=; b=2poaN2OdU4FG83mvQ9Vu23Qhg4fzsx1Ttji06klA6qEItdVkv4ij/xC7b5ya7IZxQTnI4p/+8wxU rRm7TLkJCRCqkcQq92Xu2BH2C28nvEhr4dc8JPV03tM9CKmSaODS X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SPI pins of the SPICC Controller in Meson-GX needs to be controlled by pin biais when idle. Therefore define three pinctrl names: - default: SPI pins are controlled by spi function. - idle-high: SCLK pin is pulled-up, but MOSI/MISO are still controlled by spi function. - idle-low: SCLK pin is pulled-down, but MOSI/MISO are still controlled by spi function. Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur --- .../devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml | 15 +++++++++++= ++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.y= aml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index 0c10f7678178..53013e27f507 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -43,6 +43,14 @@ properties: minItems: 1 maxItems: 2 =20 + pinctrl-0: + minItems: 1 + + pinctrl-1: + maxItems: 1 + + pinctrl-names: true + if: properties: compatible: @@ -69,6 +77,13 @@ else: items: - const: core =20 + pinctrl-names: + minItems: 1 + items: + - const: default + - const: idle-high + - const: idle-low + required: - compatible - reg --=20 b4 0.10.1 From nobody Mon Apr 6 16:31:02 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40034C433FE for ; Tue, 4 Oct 2022 11:11:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229982AbiJDLL4 (ORCPT ); Tue, 4 Oct 2022 07:11:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229938AbiJDLLf (ORCPT ); Tue, 4 Oct 2022 07:11:35 -0400 Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F51656BA5 for ; Tue, 4 Oct 2022 04:11:32 -0700 (PDT) Received: by mail-wm1-x32d.google.com with SMTP id 130-20020a1c0288000000b003b494ffc00bso10091464wmc.0 for ; Tue, 04 Oct 2022 04:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9UJJeF3sZho4I3jRzyDgsCpW+xzw8EC4+Woo4EIRjhI=; b=KHLlACe35Mt0YeI5e0xlhWAhl2sdUfS56qWu5smFZ4A68YYNa4E61YRaBQtFSrAEXY yyh6xYRXK4APj0XRiQJvvhee9i1zHNJDqEtVZpZfDBd8lz52N7J2vk1GUeOYgjeP/2dn wQuXDFJuH8zp9ujEVAB83+I1eTbBpsQYE/yB3U76hnYJdxYS6q+NCWRH76b6frzVzgQz +k9UFPJSsLjax5MtvJuMlqz/4RPhQ2gVWaiCqFM1WltK9j9J+Tj5YdJx4QB9w7cvtlmF 1+k6bFa43fbpFS4vzjZWBHularItcdxR4osuQrkGJUV8ypb06XAX72nurvhEWZ8nHneq Rx/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9UJJeF3sZho4I3jRzyDgsCpW+xzw8EC4+Woo4EIRjhI=; b=0DeHMwmqBw9izL5juySSK21KUJ0LU7cUNNqeLGW7YT39XzIsv7wBKenxliQdXdobbE WbYxSlaglAdQRfIOk7P4/QE9oxOuZSkFz3bwssYO5DzyB0ukGcxx7uEpOC4ainCRAc74 zOmVyFnLdShPXLhCVG960flUtwNYDahnNFa73Ykf8f4NCR/2ptCK5Kwdnw/DUuvNqr2q WG9QoAn/JUAH0Yx1wZnkDcTURJkV9DImFLdn9W99FihDnYWNU5jDpuea5oM11JrGrxHK AlL6NSOwEFpXjUVXzgqgBYKY0xndnH3M0leBRKFn4urpSDQ/YN8qGYWZS+7k2WjyF7mi Jjlw== X-Gm-Message-State: ACrzQf2Gk1ukOzVcn1Z0MJGwvJLPgwY6Qx0BbM0OtpUw4CVg4PCLBmUo 8/MAVBJq+SOeIhCDrXntSFmJHQ== X-Google-Smtp-Source: AMsMyM4lprZEpHTZymzZDyAyeL37GQbNRWZDIhkLoxsLstNxTH5VirriI4pGn0cdfLfduLDfEj2H3w== X-Received: by 2002:a05:600c:1f06:b0:3b4:86e8:bd21 with SMTP id bd6-20020a05600c1f0600b003b486e8bd21mr10028543wmb.7.1664881890873; Tue, 04 Oct 2022 04:11:30 -0700 (PDT) Received: from [127.0.1.1] (210.145.15.109.rev.sfr.net. [109.15.145.210]) by smtp.googlemail.com with ESMTPSA id j2-20020adfd202000000b002285f73f11dsm15361698wrh.81.2022.10.04.04.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 04:11:30 -0700 (PDT) From: Amjad Ouled-Ameur Date: Tue, 04 Oct 2022 13:10:37 +0200 Subject: [PATCH v2 2/2] spi: meson-spicc: Use pinctrl to drive CLK line when idle MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20221004-up-aml-fix-spi-v2-2-3e8ae91a1925@baylibre.com> References: <20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@baylibre.com> In-Reply-To: <20221004-up-aml-fix-spi-v2-0-3e8ae91a1925@baylibre.com> To: Krzysztof Kozlowski , Neil Armstrong , Rob Herring , Martin Blumenstingl , Kevin Hilman , Jerome Brunet , Mark Brown Cc: Neil Armstrong , Da Xue , linux-kernel@vger.kernel.org, Amjad Ouled-Ameur , linux-spi@vger.kernel.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.10.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1664881888; l=4316; i=aouledameur@baylibre.com; s=20220920; h=from:subject:message-id; bh=nQpkgGjqWbrM00eFiyFqQsdlJkaQwuIgVz9GJtl+aH8=; b=l2gvdzyi3u1EecI5XIadzmWGWdV37GSawLpg4eQliIlv74HpWJ8aYWZjLW4I8iU8mgyE0FCBBwH3 7FR3jqPEDOVxf7WWD7pWTVmbV1IXXGNAk+3hjfEnoMJ/h/hKrZhS X-Developer-Key: i=aouledameur@baylibre.com; a=ed25519; pk=HgYWawSL4qLGPx+RzJ+Cuu+V8Pi/KQnDDm1wjWPMOFE= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Between SPI transactions, all SPI pins are in HiZ state. When using the SS signal from the SPICC controller it's not an issue because when the transaction resumes all pins come back to the right state at the same time as SS. The problem is when we use CS as a GPIO. In fact, between the GPIO CS state change and SPI pins state change from idle, you can have a missing or spurious clock transition. Set a bias on the clock depending on the clock polarity requested before CS goes active, by passing a special "idle-low" and "idle-high" pinctrl state and setting the right state at a start of a message Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur --- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 14 +++++++++++ drivers/spi/spi-meson-spicc.c | 39 ++++++++++++++++++++++++++= +++- 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/d= ts/amlogic/meson-gxl.dtsi index c3ac531c4f84..04e9d0f1bde0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -429,6 +429,20 @@ mux { }; }; =20 + spi_idle_high_pins: spi-idle-high-pins { + mux { + groups =3D "spi_sclk"; + bias-pull-up; + }; + }; + + spi_idle_low_pins: spi-idle-low-pins { + mux { + groups =3D "spi_sclk"; + bias-pull-down; + }; + }; + spi_ss0_pins: spi-ss0 { mux { groups =3D "spi_ss0"; diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c index e4cb52e1fe26..de89577319ec 100644 --- a/drivers/spi/spi-meson-spicc.c +++ b/drivers/spi/spi-meson-spicc.c @@ -21,6 +21,7 @@ #include #include #include +#include =20 /* * The Meson SPICC controller could support DMA based transfers, but is not @@ -167,6 +168,9 @@ struct meson_spicc_device { unsigned long tx_remain; unsigned long rx_remain; unsigned long xfer_remain; + struct pinctrl *pinctrl; + struct pinctrl_state *pins_idle_high; + struct pinctrl_state *pins_idle_low; }; =20 #define pow2_clk_to_spicc(_div) container_of(_div, struct meson_spicc_devi= ce, pow2_div) @@ -175,8 +179,22 @@ static void meson_spicc_oen_enable(struct meson_spicc_= device *spicc) { u32 conf; =20 - if (!spicc->data->has_oen) + if (!spicc->data->has_oen) { + /* Try to get pinctrl states for idle high/low */ + spicc->pins_idle_high =3D pinctrl_lookup_state(spicc->pinctrl, + "idle-high"); + if (IS_ERR(spicc->pins_idle_high)) { + dev_warn(&spicc->pdev->dev, "can't get idle-high pinctrl\n"); + spicc->pins_idle_high =3D NULL; + } + spicc->pins_idle_low =3D pinctrl_lookup_state(spicc->pinctrl, + "idle-low"); + if (IS_ERR(spicc->pins_idle_low)) { + dev_warn(&spicc->pdev->dev, "can't get idle-low pinctrl\n"); + spicc->pins_idle_low =3D NULL; + } return; + } =20 conf =3D readl_relaxed(spicc->base + SPICC_ENH_CTL0) | SPICC_ENH_MOSI_OEN | SPICC_ENH_CLK_OEN | SPICC_ENH_CS_OEN; @@ -441,6 +459,16 @@ static int meson_spicc_prepare_message(struct spi_mast= er *master, else conf &=3D ~SPICC_POL; =20 + if (!spicc->data->has_oen) { + if (spi->mode & SPI_CPOL) { + if (spicc->pins_idle_high) + pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_high); + } else { + if (spicc->pins_idle_low) + pinctrl_select_state(spicc->pinctrl, spicc->pins_idle_low); + } + } + if (spi->mode & SPI_CPHA) conf |=3D SPICC_PHA; else @@ -487,6 +515,9 @@ static int meson_spicc_unprepare_transfer(struct spi_ma= ster *master) /* Set default configuration, keeping datarate field */ writel_relaxed(conf, spicc->base + SPICC_CONREG); =20 + if (!spicc->data->has_oen) + pinctrl_select_default_state(&spicc->pdev->dev); + return 0; } =20 @@ -798,6 +829,12 @@ static int meson_spicc_probe(struct platform_device *p= dev) goto out_core_clk; } =20 + spicc->pinctrl =3D devm_pinctrl_get(&pdev->dev); + if (IS_ERR(spicc->pinctrl)) { + ret =3D PTR_ERR(spicc->pinctrl); + goto out_clk; + } + device_reset_optional(&pdev->dev); =20 master->num_chipselect =3D 4; --=20 b4 0.10.1